From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>,
qemu-devel@nongnu.org,
Daniel Henrique Barboza <danielhb413@gmail.com>,
Glenn Miles <milesg@linux.vnet.ibm.com>
Subject: [PATCH 02/14] target/ppc: Remove redundant MEMOP_GET_SIZE macro
Date: Sat, 18 May 2024 19:31:44 +1000 [thread overview]
Message-ID: <20240518093157.407144-3-npiggin@gmail.com> (raw)
In-Reply-To: <20240518093157.407144-1-npiggin@gmail.com>
There is a memop_size() function for this.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/translate.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 0882fe2fd2..cf2404330b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2904,8 +2904,6 @@ static void gen_isync(DisasContext *ctx)
ctx->base.is_jmp = DISAS_EXIT_UPDATE;
}
-#define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
-
static void gen_load_locked(DisasContext *ctx, MemOp memop)
{
TCGv gpr = cpu_gpr[rD(ctx->opcode)];
@@ -2938,7 +2936,7 @@ static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
TCGv u = tcg_temp_new();
tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
- tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop));
+ tcg_gen_addi_tl(t2, EA, memop_size(memop));
tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
tcg_gen_addi_tl(u, t, addend);
@@ -2948,7 +2946,7 @@ static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
/* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
- tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1));
+ tcg_gen_movi_tl(u, 1 << (memop_size(memop) * 8 - 1));
tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u);
}
@@ -3110,7 +3108,7 @@ static void gen_st_atomic(DisasContext *ctx, MemOp memop)
TCGv ea_plus_s = tcg_temp_new();
tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
- tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop));
+ tcg_gen_addi_tl(ea_plus_s, EA, memop_size(memop));
tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
--
2.43.0
next prev parent reply other threads:[~2024-05-18 9:34 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-18 9:31 [PATCH 00/14] target/ppc: Various TCG emulation patches Nicholas Piggin
2024-05-18 9:31 ` [PATCH 01/14] target/ppc: larx/stcx generation need only apply DEF_MEMOP() once Nicholas Piggin
2024-05-18 10:58 ` Richard Henderson
2024-05-18 9:31 ` Nicholas Piggin [this message]
2024-05-18 9:57 ` [PATCH 02/14] target/ppc: Remove redundant MEMOP_GET_SIZE macro BALATON Zoltan
2024-05-18 10:59 ` Richard Henderson
2024-05-18 9:31 ` [PATCH 03/14] target/ppc: Make checkstop actually stop the system Nicholas Piggin
2024-05-18 9:31 ` [PATCH 04/14] target/ppc: improve checkstop logging Nicholas Piggin
2024-05-18 9:31 ` [PATCH 05/14] target/ppc: Implement attn instruction on BookS 64-bit processors Nicholas Piggin
2024-05-18 11:05 ` Richard Henderson
2024-05-20 7:18 ` Nicholas Piggin
2024-05-18 11:07 ` Richard Henderson
2024-05-20 7:22 ` Nicholas Piggin
2024-05-18 9:31 ` [PATCH 06/14] target/ppc: BookE DECAR SPR is 32-bit Nicholas Piggin
2024-05-18 9:31 ` [PATCH 07/14] target/ppc: Wire up BookE ATB registers for e500 family Nicholas Piggin
2024-05-18 9:31 ` [PATCH 08/14] target/ppc: Add PPR32 SPR Nicholas Piggin
2024-05-18 9:31 ` [PATCH 09/14] target/ppc: add helper to write per-LPAR SPRs Nicholas Piggin
2024-05-18 11:26 ` Richard Henderson
2024-05-20 7:23 ` Nicholas Piggin
2024-05-18 9:31 ` [PATCH 10/14] target/ppc: Add SMT support to simple SPRs Nicholas Piggin
2024-05-18 9:31 ` [PATCH 11/14] target/ppc: Add SMT support to PTCR SPR Nicholas Piggin
2024-05-18 9:31 ` [PATCH 12/14] target/ppc: Implement LDBAR, TTR SPRs Nicholas Piggin
2024-05-18 9:31 ` [PATCH 13/14] target/ppc: Implement SPRC/SPRD SPRs Nicholas Piggin
2024-05-18 9:31 ` [PATCH 14/14] target/ppc: add SMT support to msgsnd broadcast Nicholas Piggin
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