From: Andrew Jones <ajones@ventanamicro.com>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH 1/1] RISC-V: KVM: No need to use mask when hart-index-bit is 0
Date: Wed, 22 May 2024 11:00:12 +0200 [thread overview]
Message-ID: <20240522-74009df58fb51008bae6cbaf@orel> (raw)
In-Reply-To: <20240415064905.25184-1-yongxuan.wang@sifive.com>
On Mon, Apr 15, 2024 at 02:49:04PM GMT, Yong-Xuan Wang wrote:
> When the maximum hart number within groups is 1, hart-index-bit is set to
> 0. Consequently, there is no need to restore the hart ID from IMSIC
> addresses and hart-index-bit settings. Currently, QEMU and kvmtool do not
> pass correct hart-index-bit values when the maximum hart number is a
> power of 2, thereby avoiding this issue. Corresponding patches for QEMU
> and kvmtool will also be dispatched.
>
> Fixes: 89d01306e34d ("RISC-V: KVM: Implement device interface for AIA irqchip")
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
> arch/riscv/kvm/aia_device.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/kvm/aia_device.c b/arch/riscv/kvm/aia_device.c
> index 0eb689351b7d..5cd407c6a8e4 100644
> --- a/arch/riscv/kvm/aia_device.c
> +++ b/arch/riscv/kvm/aia_device.c
> @@ -237,10 +237,11 @@ static gpa_t aia_imsic_ppn(struct kvm_aia *aia, gpa_t addr)
>
> static u32 aia_imsic_hart_index(struct kvm_aia *aia, gpa_t addr)
> {
> - u32 hart, group = 0;
> + u32 hart = 0, group = 0;
>
> - hart = (addr >> (aia->nr_guest_bits + IMSIC_MMIO_PAGE_SHIFT)) &
> - GENMASK_ULL(aia->nr_hart_bits - 1, 0);
> + if (aia->nr_hart_bits)
> + hart = (addr >> (aia->nr_guest_bits + IMSIC_MMIO_PAGE_SHIFT)) &
> + GENMASK_ULL(aia->nr_hart_bits - 1, 0);
> if (aia->nr_group_bits)
> group = (addr >> aia->nr_group_shift) &
> GENMASK_ULL(aia->nr_group_bits - 1, 0);
> --
> 2.17.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <ajones@ventanamicro.com>
To: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Cc: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
greentime.hu@sifive.com, vincent.chen@sifive.com,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/1] RISC-V: KVM: No need to use mask when hart-index-bit is 0
Date: Wed, 22 May 2024 11:00:12 +0200 [thread overview]
Message-ID: <20240522-74009df58fb51008bae6cbaf@orel> (raw)
In-Reply-To: <20240415064905.25184-1-yongxuan.wang@sifive.com>
On Mon, Apr 15, 2024 at 02:49:04PM GMT, Yong-Xuan Wang wrote:
> When the maximum hart number within groups is 1, hart-index-bit is set to
> 0. Consequently, there is no need to restore the hart ID from IMSIC
> addresses and hart-index-bit settings. Currently, QEMU and kvmtool do not
> pass correct hart-index-bit values when the maximum hart number is a
> power of 2, thereby avoiding this issue. Corresponding patches for QEMU
> and kvmtool will also be dispatched.
>
> Fixes: 89d01306e34d ("RISC-V: KVM: Implement device interface for AIA irqchip")
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
> arch/riscv/kvm/aia_device.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/kvm/aia_device.c b/arch/riscv/kvm/aia_device.c
> index 0eb689351b7d..5cd407c6a8e4 100644
> --- a/arch/riscv/kvm/aia_device.c
> +++ b/arch/riscv/kvm/aia_device.c
> @@ -237,10 +237,11 @@ static gpa_t aia_imsic_ppn(struct kvm_aia *aia, gpa_t addr)
>
> static u32 aia_imsic_hart_index(struct kvm_aia *aia, gpa_t addr)
> {
> - u32 hart, group = 0;
> + u32 hart = 0, group = 0;
>
> - hart = (addr >> (aia->nr_guest_bits + IMSIC_MMIO_PAGE_SHIFT)) &
> - GENMASK_ULL(aia->nr_hart_bits - 1, 0);
> + if (aia->nr_hart_bits)
> + hart = (addr >> (aia->nr_guest_bits + IMSIC_MMIO_PAGE_SHIFT)) &
> + GENMASK_ULL(aia->nr_hart_bits - 1, 0);
> if (aia->nr_group_bits)
> group = (addr >> aia->nr_group_shift) &
> GENMASK_ULL(aia->nr_group_bits - 1, 0);
> --
> 2.17.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <ajones@ventanamicro.com>
To: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Cc: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
greentime.hu@sifive.com, vincent.chen@sifive.com,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/1] RISC-V: KVM: No need to use mask when hart-index-bit is 0
Date: Wed, 22 May 2024 11:00:12 +0200 [thread overview]
Message-ID: <20240522-74009df58fb51008bae6cbaf@orel> (raw)
In-Reply-To: <20240415064905.25184-1-yongxuan.wang@sifive.com>
On Mon, Apr 15, 2024 at 02:49:04PM GMT, Yong-Xuan Wang wrote:
> When the maximum hart number within groups is 1, hart-index-bit is set to
> 0. Consequently, there is no need to restore the hart ID from IMSIC
> addresses and hart-index-bit settings. Currently, QEMU and kvmtool do not
> pass correct hart-index-bit values when the maximum hart number is a
> power of 2, thereby avoiding this issue. Corresponding patches for QEMU
> and kvmtool will also be dispatched.
>
> Fixes: 89d01306e34d ("RISC-V: KVM: Implement device interface for AIA irqchip")
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
> arch/riscv/kvm/aia_device.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/kvm/aia_device.c b/arch/riscv/kvm/aia_device.c
> index 0eb689351b7d..5cd407c6a8e4 100644
> --- a/arch/riscv/kvm/aia_device.c
> +++ b/arch/riscv/kvm/aia_device.c
> @@ -237,10 +237,11 @@ static gpa_t aia_imsic_ppn(struct kvm_aia *aia, gpa_t addr)
>
> static u32 aia_imsic_hart_index(struct kvm_aia *aia, gpa_t addr)
> {
> - u32 hart, group = 0;
> + u32 hart = 0, group = 0;
>
> - hart = (addr >> (aia->nr_guest_bits + IMSIC_MMIO_PAGE_SHIFT)) &
> - GENMASK_ULL(aia->nr_hart_bits - 1, 0);
> + if (aia->nr_hart_bits)
> + hart = (addr >> (aia->nr_guest_bits + IMSIC_MMIO_PAGE_SHIFT)) &
> + GENMASK_ULL(aia->nr_hart_bits - 1, 0);
> if (aia->nr_group_bits)
> group = (addr >> aia->nr_group_shift) &
> GENMASK_ULL(aia->nr_group_bits - 1, 0);
> --
> 2.17.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2024-05-22 9:00 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-15 6:49 [PATCH 1/1] RISC-V: KVM: No need to use mask when hart-index-bit is 0 Yong-Xuan Wang
2024-04-15 6:49 ` Yong-Xuan Wang
2024-04-15 6:49 ` Yong-Xuan Wang
2024-05-22 8:24 ` Yong-Xuan Wang
2024-05-22 8:24 ` Yong-Xuan Wang
2024-05-22 8:24 ` Yong-Xuan Wang
2024-05-22 9:00 ` Andrew Jones [this message]
2024-05-22 9:00 ` Andrew Jones
2024-05-22 9:00 ` Andrew Jones
2024-05-31 4:34 ` Anup Patel
2024-05-31 4:34 ` Anup Patel
2024-05-31 4:34 ` Anup Patel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240522-74009df58fb51008bae6cbaf@orel \
--to=ajones@ventanamicro.com \
--cc=kvm-riscv@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.