From: Sunil V L <sunilvl@ventanamicro.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Andrew Jones <ajones@ventanamicro.com>,
Sunil V L <sunilvl@ventanamicro.com>
Subject: [PATCH 2/3] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
Date: Tue, 28 May 2024 13:01:02 +0530 [thread overview]
Message-ID: <20240528073103.1075812-3-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20240528073103.1075812-1-sunilvl@ventanamicro.com>
PLIC and APLIC should be in namespace as well. So, add them using the
defined HID.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
hw/riscv/virt-acpi-build.c | 47 ++++++++++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 832a3acb8d..47ec78e432 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -141,6 +141,52 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
}
}
+static void acpi_dsdt_add_plic_aplic(Aml *scope, RISCVVirtState *s)
+{
+ MachineState *ms = MACHINE(s);
+ uint64_t plic_aplic_addr;
+ uint32_t gsi_base;
+ uint8_t socket;
+
+ if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+ /* PLICs */
+ for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+ plic_aplic_addr = s->memmap[VIRT_PLIC].base +
+ s->memmap[VIRT_PLIC].size * socket;
+ gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+ Aml *dev = aml_device("IC%.02X", socket);
+ aml_append(dev, aml_name_decl("_HID", aml_string("RSCV0001")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(socket)));
+ aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base)));
+
+ Aml *crs = aml_resource_template();
+ aml_append(crs, aml_memory32_fixed(plic_aplic_addr,
+ s->memmap[VIRT_PLIC].size,
+ AML_READ_WRITE));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+ }
+ } else {
+ /* APLICs */
+ for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+ plic_aplic_addr = s->memmap[VIRT_APLIC_S].base +
+ s->memmap[VIRT_APLIC_S].size * socket;
+ gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+ Aml *dev = aml_device("IC%.02X", socket);
+ aml_append(dev, aml_name_decl("_HID", aml_string("RSCV0002")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(socket)));
+ aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base)));
+
+ Aml *crs = aml_resource_template();
+ aml_append(crs, aml_memory32_fixed(plic_aplic_addr,
+ s->memmap[VIRT_APLIC_S].size,
+ AML_READ_WRITE));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+ }
+ }
+}
+
static void
acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
uint32_t uart_irq)
@@ -411,6 +457,7 @@ static void build_dsdt(GArray *table_data,
socket_count = riscv_socket_count(ms);
+ acpi_dsdt_add_plic_aplic(scope, s);
acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ);
if (socket_count == 1) {
--
2.40.1
next prev parent reply other threads:[~2024-05-28 7:31 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-28 7:31 [PATCH 0/3] RISC-V: ACPI: Namespace updates Sunil V L
2024-05-28 7:31 ` [PATCH 1/3] gpex-acpi: Support PCI link devices outside the host bridge Sunil V L
2024-06-04 23:06 ` Alistair Francis
2024-06-05 8:23 ` Michael S. Tsirkin
2024-06-05 11:43 ` Sunil V L
2024-05-28 7:31 ` Sunil V L [this message]
2024-06-04 23:08 ` [PATCH 2/3] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC Alistair Francis
2024-05-28 7:31 ` [PATCH 3/3] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART Sunil V L
2024-06-04 23:09 ` Alistair Francis
2024-06-05 14:48 ` Igor Mammedov
2024-06-06 9:49 ` Sunil V L
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