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* [PATCH] RISC-V: Implement ioremap_wc/wt
@ 2024-05-31 10:04 ` Qingfang Deng
  0 siblings, 0 replies; 6+ messages in thread
From: Qingfang Deng @ 2024-05-31 10:04 UTC (permalink / raw)
  To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Samuel Holland,
	Qingfang Deng, Eric Chan, Andrea Parri, linux-riscv, linux-kernel

From: Qingfang Deng <qingfang.deng@siflower.com.cn>

Currently on RISC-V, ioremap_wc/wt uses the default ioremap
implementation, which maps the memory as strongly-ordered non-cacheable
IO memory on systems with Svpbmt.

To improve performance, map the memory as weakly-ordered non-cacheable
normal memory.

Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn>
---
 arch/riscv/include/asm/io.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index 1c5c641075d2..582503e0f508 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -133,6 +133,14 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
 #define outsq(addr, buffer, count) __outsq(PCI_IOBASE + (addr), buffer, count)
 #endif
 
+#ifdef CONFIG_MMU
+#define ioremap_wc(addr, size) \
+	ioremap_prot((addr), (size), \
+		     (_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE)
+
+#define ioremap_wt ioremap_wc
+#endif
+
 #include <asm-generic/io.h>
 
 #ifdef CONFIG_MMU
-- 
2.34.1


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http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH] RISC-V: Implement ioremap_wc/wt
@ 2024-05-31 10:04 ` Qingfang Deng
  0 siblings, 0 replies; 6+ messages in thread
From: Qingfang Deng @ 2024-05-31 10:04 UTC (permalink / raw)
  To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Samuel Holland,
	Qingfang Deng, Eric Chan, Andrea Parri, linux-riscv, linux-kernel

From: Qingfang Deng <qingfang.deng@siflower.com.cn>

Currently on RISC-V, ioremap_wc/wt uses the default ioremap
implementation, which maps the memory as strongly-ordered non-cacheable
IO memory on systems with Svpbmt.

To improve performance, map the memory as weakly-ordered non-cacheable
normal memory.

Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn>
---
 arch/riscv/include/asm/io.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index 1c5c641075d2..582503e0f508 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -133,6 +133,14 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
 #define outsq(addr, buffer, count) __outsq(PCI_IOBASE + (addr), buffer, count)
 #endif
 
+#ifdef CONFIG_MMU
+#define ioremap_wc(addr, size) \
+	ioremap_prot((addr), (size), \
+		     (_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE)
+
+#define ioremap_wt ioremap_wc
+#endif
+
 #include <asm-generic/io.h>
 
 #ifdef CONFIG_MMU
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [External] [PATCH] RISC-V: Implement ioremap_wc/wt
  2024-05-31 10:04 ` Qingfang Deng
@ 2024-06-06  6:48   ` yunhui cui
  -1 siblings, 0 replies; 6+ messages in thread
From: yunhui cui @ 2024-06-06  6:48 UTC (permalink / raw)
  To: Qingfang Deng
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Samuel Holland,
	Qingfang Deng, Eric Chan, Andrea Parri, linux-riscv, linux-kernel

 Hi Qingfang,


On Fri, May 31, 2024 at 6:04 PM Qingfang Deng <dqfext@gmail.com> wrote:
>
> From: Qingfang Deng <qingfang.deng@siflower.com.cn>
>
> Currently on RISC-V, ioremap_wc/wt uses the default ioremap
> implementation, which maps the memory as strongly-ordered non-cacheable
> IO memory on systems with Svpbmt.
>
> To improve performance, map the memory as weakly-ordered non-cacheable
> normal memory.
>
> Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn>
> ---
>  arch/riscv/include/asm/io.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
> index 1c5c641075d2..582503e0f508 100644
> --- a/arch/riscv/include/asm/io.h
> +++ b/arch/riscv/include/asm/io.h
> @@ -133,6 +133,14 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
>  #define outsq(addr, buffer, count) __outsq(PCI_IOBASE + (addr), buffer, count)
>  #endif
>
> +#ifdef CONFIG_MMU
> +#define ioremap_wc(addr, size) \
> +       ioremap_prot((addr), (size), \
> +                    (_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE)

> +
> +#define ioremap_wt ioremap_wc
> +#endif
> +
>  #include <asm-generic/io.h>
>
>  #ifdef CONFIG_MMU
> --
> 2.34.1
>
>

Can you provide specific test data for performance improvement?

Thanks,
Yunhui

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [External] [PATCH] RISC-V: Implement ioremap_wc/wt
@ 2024-06-06  6:48   ` yunhui cui
  0 siblings, 0 replies; 6+ messages in thread
From: yunhui cui @ 2024-06-06  6:48 UTC (permalink / raw)
  To: Qingfang Deng
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Samuel Holland,
	Qingfang Deng, Eric Chan, Andrea Parri, linux-riscv, linux-kernel

 Hi Qingfang,


On Fri, May 31, 2024 at 6:04 PM Qingfang Deng <dqfext@gmail.com> wrote:
>
> From: Qingfang Deng <qingfang.deng@siflower.com.cn>
>
> Currently on RISC-V, ioremap_wc/wt uses the default ioremap
> implementation, which maps the memory as strongly-ordered non-cacheable
> IO memory on systems with Svpbmt.
>
> To improve performance, map the memory as weakly-ordered non-cacheable
> normal memory.
>
> Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn>
> ---
>  arch/riscv/include/asm/io.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
> index 1c5c641075d2..582503e0f508 100644
> --- a/arch/riscv/include/asm/io.h
> +++ b/arch/riscv/include/asm/io.h
> @@ -133,6 +133,14 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
>  #define outsq(addr, buffer, count) __outsq(PCI_IOBASE + (addr), buffer, count)
>  #endif
>
> +#ifdef CONFIG_MMU
> +#define ioremap_wc(addr, size) \
> +       ioremap_prot((addr), (size), \
> +                    (_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE)

> +
> +#define ioremap_wt ioremap_wc
> +#endif
> +
>  #include <asm-generic/io.h>
>
>  #ifdef CONFIG_MMU
> --
> 2.34.1
>
>

Can you provide specific test data for performance improvement?

Thanks,
Yunhui

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [External] [PATCH] RISC-V: Implement ioremap_wc/wt
  2024-06-06  6:48   ` yunhui cui
@ 2025-07-22  3:00     ` yunhui cui
  -1 siblings, 0 replies; 6+ messages in thread
From: yunhui cui @ 2025-07-22  3:00 UTC (permalink / raw)
  To: Qingfang Deng
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Samuel Holland,
	Qingfang Deng, Eric Chan, Andrea Parri, linux-riscv, linux-kernel

Hi Qingfang,

On Thu, Jun 6, 2024 at 2:48 PM yunhui cui <cuiyunhui@bytedance.com> wrote:
>
>  Hi Qingfang,
>
>
> On Fri, May 31, 2024 at 6:04 PM Qingfang Deng <dqfext@gmail.com> wrote:
> >
> > From: Qingfang Deng <qingfang.deng@siflower.com.cn>
> >
> > Currently on RISC-V, ioremap_wc/wt uses the default ioremap
> > implementation, which maps the memory as strongly-ordered non-cacheable
> > IO memory on systems with Svpbmt.
> >
> > To improve performance, map the memory as weakly-ordered non-cacheable
> > normal memory.
> >
> > Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn>
> > ---
> >  arch/riscv/include/asm/io.h | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
> > index 1c5c641075d2..582503e0f508 100644
> > --- a/arch/riscv/include/asm/io.h
> > +++ b/arch/riscv/include/asm/io.h
> > @@ -133,6 +133,14 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
> >  #define outsq(addr, buffer, count) __outsq(PCI_IOBASE + (addr), buffer, count)
> >  #endif
> >
> > +#ifdef CONFIG_MMU
> > +#define ioremap_wc(addr, size) \
> > +       ioremap_prot((addr), (size), \
> > +                    (_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE)

Compared with IO attributes, NC attributes can improve performance,
specifically in these aspects: Relaxed Order, Gathering, Supports Read
Speculation, Supports Unaligned Access. Therefore, it is necessary to
implement ioremap_wc().

> > +
> > +#define ioremap_wt ioremap_wc

From the perspective of arm64, ioremap_wt should have IO attributes
rather than NC attributes, so this line should be removed.

> > +#endif
> > +
> >  #include <asm-generic/io.h>
> >
> >  #ifdef CONFIG_MMU
> > --
> > 2.34.1
> >
> >
>
> Can you provide specific test data for performance improvement?
>
> Thanks,
> Yunhui

Thanks,
Yunhui

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [External] [PATCH] RISC-V: Implement ioremap_wc/wt
@ 2025-07-22  3:00     ` yunhui cui
  0 siblings, 0 replies; 6+ messages in thread
From: yunhui cui @ 2025-07-22  3:00 UTC (permalink / raw)
  To: Qingfang Deng
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Samuel Holland,
	Qingfang Deng, Eric Chan, Andrea Parri, linux-riscv, linux-kernel

Hi Qingfang,

On Thu, Jun 6, 2024 at 2:48 PM yunhui cui <cuiyunhui@bytedance.com> wrote:
>
>  Hi Qingfang,
>
>
> On Fri, May 31, 2024 at 6:04 PM Qingfang Deng <dqfext@gmail.com> wrote:
> >
> > From: Qingfang Deng <qingfang.deng@siflower.com.cn>
> >
> > Currently on RISC-V, ioremap_wc/wt uses the default ioremap
> > implementation, which maps the memory as strongly-ordered non-cacheable
> > IO memory on systems with Svpbmt.
> >
> > To improve performance, map the memory as weakly-ordered non-cacheable
> > normal memory.
> >
> > Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn>
> > ---
> >  arch/riscv/include/asm/io.h | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
> > index 1c5c641075d2..582503e0f508 100644
> > --- a/arch/riscv/include/asm/io.h
> > +++ b/arch/riscv/include/asm/io.h
> > @@ -133,6 +133,14 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
> >  #define outsq(addr, buffer, count) __outsq(PCI_IOBASE + (addr), buffer, count)
> >  #endif
> >
> > +#ifdef CONFIG_MMU
> > +#define ioremap_wc(addr, size) \
> > +       ioremap_prot((addr), (size), \
> > +                    (_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE)

Compared with IO attributes, NC attributes can improve performance,
specifically in these aspects: Relaxed Order, Gathering, Supports Read
Speculation, Supports Unaligned Access. Therefore, it is necessary to
implement ioremap_wc().

> > +
> > +#define ioremap_wt ioremap_wc

From the perspective of arm64, ioremap_wt should have IO attributes
rather than NC attributes, so this line should be removed.

> > +#endif
> > +
> >  #include <asm-generic/io.h>
> >
> >  #ifdef CONFIG_MMU
> > --
> > 2.34.1
> >
> >
>
> Can you provide specific test data for performance improvement?
>
> Thanks,
> Yunhui

Thanks,
Yunhui

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-07-22  3:01 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-05-31 10:04 [PATCH] RISC-V: Implement ioremap_wc/wt Qingfang Deng
2024-05-31 10:04 ` Qingfang Deng
2024-06-06  6:48 ` [External] " yunhui cui
2024-06-06  6:48   ` yunhui cui
2025-07-22  3:00   ` yunhui cui
2025-07-22  3:00     ` yunhui cui

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