From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org,
acpica-devel@lists.linux.dev
Cc: "Catalin Marinas" <catalin.marinas@arm.com>,
"Will Deacon" <will@kernel.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"Len Brown" <lenb@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Anup Patel" <anup@brainfault.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Robert Moore" <robert.moore@intel.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
"Marc Zyngier" <maz@kernel.org>,
"Atish Kumar Patra" <atishp@rivosinc.com>,
"Haibo1 Xu" <haibo1.xu@intel.com>,
"Björn Töpel" <bjorn@kernel.org>,
"Sunil V L" <sunilvl@ventanamicro.com>
Subject: [PATCH v6 07/17] ACPI: bus: Add RINTC IRQ model for RISC-V
Date: Sat, 1 Jun 2024 20:34:01 +0530 [thread overview]
Message-ID: <20240601150411.1929783-8-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com>
Add the IRQ model for RISC-V INTC so that acpi_set_irq_model can use this
for RISC-V.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
drivers/acpi/bus.c | 3 +++
include/linux/acpi.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index 8d0710ade8c6..d5286e39668e 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -1201,6 +1201,9 @@ static int __init acpi_bus_init_irq(void)
case ACPI_IRQ_MODEL_LPIC:
message = "LPIC";
break;
+ case ACPI_IRQ_MODEL_RINTC:
+ message = "RINTC";
+ break;
default:
pr_info("Unknown interrupt routing model\n");
return -ENODEV;
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 0c6d9539f737..3dd67ee09c39 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -107,6 +107,7 @@ enum acpi_irq_model_id {
ACPI_IRQ_MODEL_PLATFORM,
ACPI_IRQ_MODEL_GIC,
ACPI_IRQ_MODEL_LPIC,
+ ACPI_IRQ_MODEL_RINTC,
ACPI_IRQ_MODEL_COUNT
};
--
2.40.1
WARNING: multiple messages have this Message-ID (diff)
From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org,
acpica-devel@lists.linux.dev
Cc: "Marc Zyngier" <maz@kernel.org>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Haibo1 Xu" <haibo1.xu@intel.com>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Anup Patel" <anup@brainfault.org>,
"Atish Kumar Patra" <atishp@rivosinc.com>,
"Robert Moore" <robert.moore@intel.com>,
"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Björn Töpel" <bjorn@kernel.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Will Deacon" <will@kernel.org>, "Len Brown" <lenb@kernel.org>
Subject: [PATCH v6 07/17] ACPI: bus: Add RINTC IRQ model for RISC-V
Date: Sat, 1 Jun 2024 20:34:01 +0530 [thread overview]
Message-ID: <20240601150411.1929783-8-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com>
Add the IRQ model for RISC-V INTC so that acpi_set_irq_model can use this
for RISC-V.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
drivers/acpi/bus.c | 3 +++
include/linux/acpi.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index 8d0710ade8c6..d5286e39668e 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -1201,6 +1201,9 @@ static int __init acpi_bus_init_irq(void)
case ACPI_IRQ_MODEL_LPIC:
message = "LPIC";
break;
+ case ACPI_IRQ_MODEL_RINTC:
+ message = "RINTC";
+ break;
default:
pr_info("Unknown interrupt routing model\n");
return -ENODEV;
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 0c6d9539f737..3dd67ee09c39 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -107,6 +107,7 @@ enum acpi_irq_model_id {
ACPI_IRQ_MODEL_PLATFORM,
ACPI_IRQ_MODEL_GIC,
ACPI_IRQ_MODEL_LPIC,
+ ACPI_IRQ_MODEL_RINTC,
ACPI_IRQ_MODEL_COUNT
};
--
2.40.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org,
acpica-devel@lists.linux.dev
Cc: "Catalin Marinas" <catalin.marinas@arm.com>,
"Will Deacon" <will@kernel.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"Len Brown" <lenb@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Anup Patel" <anup@brainfault.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Robert Moore" <robert.moore@intel.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
"Marc Zyngier" <maz@kernel.org>,
"Atish Kumar Patra" <atishp@rivosinc.com>,
"Haibo1 Xu" <haibo1.xu@intel.com>,
"Björn Töpel" <bjorn@kernel.org>,
"Sunil V L" <sunilvl@ventanamicro.com>
Subject: [PATCH v6 07/17] ACPI: bus: Add RINTC IRQ model for RISC-V
Date: Sat, 1 Jun 2024 20:34:01 +0530 [thread overview]
Message-ID: <20240601150411.1929783-8-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com>
Add the IRQ model for RISC-V INTC so that acpi_set_irq_model can use this
for RISC-V.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
drivers/acpi/bus.c | 3 +++
include/linux/acpi.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index 8d0710ade8c6..d5286e39668e 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -1201,6 +1201,9 @@ static int __init acpi_bus_init_irq(void)
case ACPI_IRQ_MODEL_LPIC:
message = "LPIC";
break;
+ case ACPI_IRQ_MODEL_RINTC:
+ message = "RINTC";
+ break;
default:
pr_info("Unknown interrupt routing model\n");
return -ENODEV;
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 0c6d9539f737..3dd67ee09c39 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -107,6 +107,7 @@ enum acpi_irq_model_id {
ACPI_IRQ_MODEL_PLATFORM,
ACPI_IRQ_MODEL_GIC,
ACPI_IRQ_MODEL_LPIC,
+ ACPI_IRQ_MODEL_RINTC,
ACPI_IRQ_MODEL_COUNT
};
--
2.40.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-06-01 15:05 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-01 15:03 [PATCH v6 00/17] RISC-V: ACPI: Add external interrupt controller support Sunil V L
2024-06-01 15:03 ` Sunil V L
2024-06-01 15:03 ` Sunil V L
2024-06-01 15:03 ` [PATCH v6 01/17] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Sunil V L
2024-06-01 15:03 ` Sunil V L
2024-06-01 15:03 ` Sunil V L
2024-06-01 15:03 ` [PATCH v6 02/17] ACPI: scan: Add a weak function to reorder the IRQCHIP probe Sunil V L
2024-06-01 15:03 ` Sunil V L
2024-06-01 15:03 ` Sunil V L
2024-06-01 15:03 ` [PATCH v6 03/17] ACPI: bus: Add acpi_riscv_init function Sunil V L
2024-06-01 15:03 ` Sunil V L
2024-06-01 15:03 ` Sunil V L
2024-06-01 15:03 ` [PATCH v6 04/17] ACPI: scan: Refactor dependency creation Sunil V L
2024-06-01 15:03 ` Sunil V L
2024-06-01 15:03 ` Sunil V L
2024-06-01 15:03 ` [PATCH v6 05/17] ACPI: scan: Add RISC-V interrupt controllers to honor list Sunil V L
2024-06-01 15:03 ` Sunil V L
2024-06-01 15:03 ` Sunil V L
2024-06-01 15:04 ` [PATCH v6 06/17] ACPI: scan: Define weak function to populate dependencies Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` Sunil V L [this message]
2024-06-01 15:04 ` [PATCH v6 07/17] ACPI: bus: Add RINTC IRQ model for RISC-V Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` [PATCH v6 08/17] ACPI: pci_link: Clear the dependencies after probe Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` [PATCH v6 09/17] ACPI: RISC-V: Implement PCI related functionality Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` [PATCH v6 10/17] ACPI: RISC-V: Implement function to reorder irqchip probe entries Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-06 22:07 ` Bjorn Helgaas
2024-06-06 22:07 ` Bjorn Helgaas
2024-06-06 22:07 ` Bjorn Helgaas
2024-07-10 13:55 ` Sunil V L
2024-07-10 13:55 ` Sunil V L
2024-06-01 15:04 ` [PATCH v6 11/17] ACPI: RISC-V: Initialize GSI mapping structures Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-06 22:32 ` Bjorn Helgaas
2024-06-06 22:32 ` Bjorn Helgaas
2024-06-06 22:32 ` Bjorn Helgaas
2024-07-10 10:45 ` Lorenzo Pieralisi
2024-07-10 10:45 ` Lorenzo Pieralisi
2024-07-10 13:42 ` Sunil V L
2024-07-10 13:42 ` Sunil V L
2024-06-01 15:04 ` [PATCH v6 12/17] ACPI: RISC-V: Implement function to add implicit dependencies Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` [PATCH v6 13/17] irqchip/riscv-intc: Add ACPI support for AIA Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` [PATCH v6 14/17] irqchip/riscv-imsic-state: Create separate function for DT Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` [PATCH v6 15/17] irqchip/riscv-imsic: Add ACPI support Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` [PATCH v6 16/17] irqchip/riscv-aplic: " Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` [PATCH v6 17/17] irqchip/sifive-plic: " Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-01 15:04 ` Sunil V L
2024-06-25 7:25 ` [PATCH v6 00/17] RISC-V: ACPI: Add external interrupt controller support Thomas Gleixner
2024-06-25 7:25 ` Thomas Gleixner
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