* [PATCH v1 1/4] dt-bindings: clock: jh7110: Sync with Linux
2024-06-03 13:27 [PATCH v1 0/4] Sync StarFive JH7110 clock and reset dt-bindings with Linux Hal Feng
@ 2024-06-03 13:27 ` Hal Feng
2024-06-03 13:27 ` [PATCH v1 2/4] dt-bindings: reset: " Hal Feng
` (3 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Hal Feng @ 2024-06-03 13:27 UTC (permalink / raw)
To: Leo Yu-Chi Liang, Tom Rini, Lukasz Majewski, Sean Anderson,
Rick Chen, Heinrich Schuchardt, Nam Cao, Bo Gan, Yanhong Wang,
Emil Renner Berthing, Minda Chen, Hal Feng
Cc: u-boot
Sync JH7110 clock dt-bindings with Linux, which is the same with
dts/upstream/include/dt-bindings/clock/starfive,jh7110-crg.h
except copyright.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../dt-bindings/clock/starfive,jh7110-crg.h | 180 +++++++++++-------
1 file changed, 112 insertions(+), 68 deletions(-)
diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
index b51e3829ff..4eabb05473 100644
--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
@@ -5,19 +5,21 @@
* Author: Yanhong Wang <yanhong.wang@starfivetech.com>
*/
-#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
-#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
+#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
+#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
-#define JH7110_SYSCLK_PLL0_OUT 0
-#define JH7110_SYSCLK_PLL1_OUT 1
-#define JH7110_SYSCLK_PLL2_OUT 2
+/* PLL clocks */
+#define JH7110_PLLCLK_PLL0_OUT 0
+#define JH7110_PLLCLK_PLL1_OUT 1
+#define JH7110_PLLCLK_PLL2_OUT 2
#define JH7110_PLLCLK_END 3
+/* SYSCRG clocks */
#define JH7110_SYSCLK_CPU_ROOT 0
#define JH7110_SYSCLK_CPU_CORE 1
#define JH7110_SYSCLK_CPU_BUS 2
#define JH7110_SYSCLK_GPU_ROOT 3
-#define JH7110_SYSCLK_PERH_ROOT 4
+#define JH7110_SYSCLK_PERH_ROOT 4
#define JH7110_SYSCLK_BUS_ROOT 5
#define JH7110_SYSCLK_NOCSTG_BUS 6
#define JH7110_SYSCLK_AXI_CFG0 7
@@ -26,9 +28,9 @@
#define JH7110_SYSCLK_AHB1 10
#define JH7110_SYSCLK_APB_BUS 11
#define JH7110_SYSCLK_APB0 12
-#define JH7110_SYSCLK_PLL0_DIV2 13
-#define JH7110_SYSCLK_PLL1_DIV2 14
-#define JH7110_SYSCLK_PLL2_DIV2 15
+#define JH7110_SYSCLK_PLL0_DIV2 13
+#define JH7110_SYSCLK_PLL1_DIV2 14
+#define JH7110_SYSCLK_PLL2_DIV2 15
#define JH7110_SYSCLK_AUDIO_ROOT 16
#define JH7110_SYSCLK_MCLK_INNER 17
#define JH7110_SYSCLK_MCLK 18
@@ -50,12 +52,12 @@
#define JH7110_SYSCLK_TRACE2 34
#define JH7110_SYSCLK_TRACE3 35
#define JH7110_SYSCLK_TRACE4 36
-#define JH7110_SYSCLK_TRACE_COM 37
+#define JH7110_SYSCLK_TRACE_COM 37
#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38
#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39
#define JH7110_SYSCLK_OSC_DIV2 40
-#define JH7110_SYSCLK_PLL1_DIV4 41
-#define JH7110_SYSCLK_PLL1_DIV8 42
+#define JH7110_SYSCLK_PLL1_DIV4 41
+#define JH7110_SYSCLK_PLL1_DIV8 42
#define JH7110_SYSCLK_DDR_BUS 43
#define JH7110_SYSCLK_DDR_AXI 44
#define JH7110_SYSCLK_GPU_CORE 45
@@ -64,21 +66,21 @@
#define JH7110_SYSCLK_GPU_APB 48
#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49
#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50
-#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51
-#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52
+#define JH7110_SYSCLK_ISP_TOP_CORE 51
+#define JH7110_SYSCLK_ISP_TOP_AXI 52
#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53
#define JH7110_SYSCLK_HIFI4_CORE 54
-#define JH7110_SYSCLK_HIFI4_AXI 55
-#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN 56
-#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57
+#define JH7110_SYSCLK_HIFI4_AXI 55
+#define JH7110_SYSCLK_AXI_CFG1_MAIN 56
+#define JH7110_SYSCLK_AXI_CFG1_AHB 57
#define JH7110_SYSCLK_VOUT_SRC 58
#define JH7110_SYSCLK_VOUT_AXI 59
#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60
-#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB 61
-#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI 62
-#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK 63
-#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64
-#define JH7110_SYSCLK_JPEGC_AXI 65
+#define JH7110_SYSCLK_VOUT_TOP_AHB 61
+#define JH7110_SYSCLK_VOUT_TOP_AXI 62
+#define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK 63
+#define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF 64
+#define JH7110_SYSCLK_JPEGC_AXI 65
#define JH7110_SYSCLK_CODAJ12_AXI 66
#define JH7110_SYSCLK_CODAJ12_CORE 67
#define JH7110_SYSCLK_CODAJ12_APB 68
@@ -87,8 +89,8 @@
#define JH7110_SYSCLK_WAVE511_BPU 71
#define JH7110_SYSCLK_WAVE511_VCE 72
#define JH7110_SYSCLK_WAVE511_APB 73
-#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74
-#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN 75
+#define JH7110_SYSCLK_VDEC_JPG 74
+#define JH7110_SYSCLK_VDEC_MAIN 75
#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76
#define JH7110_SYSCLK_VENC_AXI 77
#define JH7110_SYSCLK_WAVE420L_AXI 78
@@ -96,37 +98,37 @@
#define JH7110_SYSCLK_WAVE420L_VCE 80
#define JH7110_SYSCLK_WAVE420L_APB 81
#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82
-#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV 83
-#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN 84
-#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4 85
+#define JH7110_SYSCLK_AXI_CFG0_MAIN_DIV 83
+#define JH7110_SYSCLK_AXI_CFG0_MAIN 84
+#define JH7110_SYSCLK_AXI_CFG0_HIFI4 85
#define JH7110_SYSCLK_AXIMEM2_AXI 86
#define JH7110_SYSCLK_QSPI_AHB 87
#define JH7110_SYSCLK_QSPI_APB 88
#define JH7110_SYSCLK_QSPI_REF_SRC 89
#define JH7110_SYSCLK_QSPI_REF 90
-#define JH7110_SYSCLK_SDIO0_AHB 91
-#define JH7110_SYSCLK_SDIO1_AHB 92
+#define JH7110_SYSCLK_SDIO0_AHB 91
+#define JH7110_SYSCLK_SDIO1_AHB 92
#define JH7110_SYSCLK_SDIO0_SDCARD 93
#define JH7110_SYSCLK_SDIO1_SDCARD 94
#define JH7110_SYSCLK_USB_125M 95
#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96
-#define JH7110_SYSCLK_GMAC1_AHB 97
-#define JH7110_SYSCLK_GMAC1_AXI 98
+#define JH7110_SYSCLK_GMAC1_AHB 97
+#define JH7110_SYSCLK_GMAC1_AXI 98
#define JH7110_SYSCLK_GMAC_SRC 99
#define JH7110_SYSCLK_GMAC1_GTXCLK 100
#define JH7110_SYSCLK_GMAC1_RMII_RTX 101
-#define JH7110_SYSCLK_GMAC1_PTP 102
+#define JH7110_SYSCLK_GMAC1_PTP 102
#define JH7110_SYSCLK_GMAC1_RX 103
#define JH7110_SYSCLK_GMAC1_RX_INV 104
#define JH7110_SYSCLK_GMAC1_TX 105
#define JH7110_SYSCLK_GMAC1_TX_INV 106
#define JH7110_SYSCLK_GMAC1_GTXC 107
#define JH7110_SYSCLK_GMAC0_GTXCLK 108
-#define JH7110_SYSCLK_GMAC0_PTP 109
+#define JH7110_SYSCLK_GMAC0_PTP 109
#define JH7110_SYSCLK_GMAC_PHY 110
#define JH7110_SYSCLK_GMAC0_GTXC 111
-#define JH7110_SYSCLK_IOMUX_APB 112
-#define JH7110_SYSCLK_MAILBOX 113
+#define JH7110_SYSCLK_IOMUX_APB 112
+#define JH7110_SYSCLK_MAILBOX_APB 113
#define JH7110_SYSCLK_INT_CTRL_APB 114
#define JH7110_SYSCLK_CAN0_APB 115
#define JH7110_SYSCLK_CAN0_TIMER 116
@@ -137,13 +139,13 @@
#define JH7110_SYSCLK_PWM_APB 121
#define JH7110_SYSCLK_WDT_APB 122
#define JH7110_SYSCLK_WDT_CORE 123
-#define JH7110_SYSCLK_TIMER_APB 124
+#define JH7110_SYSCLK_TIMER_APB 124
#define JH7110_SYSCLK_TIMER0 125
#define JH7110_SYSCLK_TIMER1 126
#define JH7110_SYSCLK_TIMER2 127
#define JH7110_SYSCLK_TIMER3 128
#define JH7110_SYSCLK_TEMP_APB 129
-#define JH7110_SYSCLK_TEMP_CORE 130
+#define JH7110_SYSCLK_TEMP_CORE 130
#define JH7110_SYSCLK_SPI0_APB 131
#define JH7110_SYSCLK_SPI1_APB 132
#define JH7110_SYSCLK_SPI2_APB 133
@@ -158,21 +160,21 @@
#define JH7110_SYSCLK_I2C4_APB 142
#define JH7110_SYSCLK_I2C5_APB 143
#define JH7110_SYSCLK_I2C6_APB 144
-#define JH7110_SYSCLK_UART0_APB 145
+#define JH7110_SYSCLK_UART0_APB 145
#define JH7110_SYSCLK_UART0_CORE 146
-#define JH7110_SYSCLK_UART1_APB 147
+#define JH7110_SYSCLK_UART1_APB 147
#define JH7110_SYSCLK_UART1_CORE 148
-#define JH7110_SYSCLK_UART2_APB 149
+#define JH7110_SYSCLK_UART2_APB 149
#define JH7110_SYSCLK_UART2_CORE 150
-#define JH7110_SYSCLK_UART3_APB 151
+#define JH7110_SYSCLK_UART3_APB 151
#define JH7110_SYSCLK_UART3_CORE 152
-#define JH7110_SYSCLK_UART4_APB 153
+#define JH7110_SYSCLK_UART4_APB 153
#define JH7110_SYSCLK_UART4_CORE 154
-#define JH7110_SYSCLK_UART5_APB 155
+#define JH7110_SYSCLK_UART5_APB 155
#define JH7110_SYSCLK_UART5_CORE 156
#define JH7110_SYSCLK_PWMDAC_APB 157
#define JH7110_SYSCLK_PWMDAC_CORE 158
-#define JH7110_SYSCLK_SPDIF_APB 159
+#define JH7110_SYSCLK_SPDIF_APB 159
#define JH7110_SYSCLK_SPDIF_CORE 160
#define JH7110_SYSCLK_I2STX0_APB 161
#define JH7110_SYSCLK_I2STX0_BCLK_MST 162
@@ -188,7 +190,7 @@
#define JH7110_SYSCLK_I2STX1_BCLK 172
#define JH7110_SYSCLK_I2STX1_BCLK_INV 173
#define JH7110_SYSCLK_I2STX1_LRCK 174
-#define JH7110_SYSCLK_I2SRX_APB 175
+#define JH7110_SYSCLK_I2SRX_APB 175
#define JH7110_SYSCLK_I2SRX_BCLK_MST 176
#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177
#define JH7110_SYSCLK_I2SRX_LRCK_MST 178
@@ -200,12 +202,13 @@
#define JH7110_SYSCLK_TDM_AHB 184
#define JH7110_SYSCLK_TDM_APB 185
#define JH7110_SYSCLK_TDM_INTERNAL 186
-#define JH7110_SYSCLK_TDM_CLK_TDM 187
-#define JH7110_SYSCLK_TDM_CLK_TDM_N 188
+#define JH7110_SYSCLK_TDM_TDM 187
+#define JH7110_SYSCLK_TDM_TDM_INV 188
#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189
#define JH7110_SYSCLK_END 190
+/* AONCRG clocks */
#define JH7110_AONCLK_OSC_DIV4 0
#define JH7110_AONCLK_APB_FUNC 1
#define JH7110_AONCLK_GMAC0_AHB 2
@@ -223,30 +226,31 @@
#define JH7110_AONCLK_END 14
-#define JH7110_STGCLK_HIFI4_CORE 0
-#define JH7110_STGCLK_USB_APB 1
-#define JH7110_STGCLK_USB_UTMI_APB 2
-#define JH7110_STGCLK_USB_AXI 3
-#define JH7110_STGCLK_USB_LPM 4
-#define JH7110_STGCLK_USB_STB 5
-#define JH7110_STGCLK_USB_APP_125 6
-#define JH7110_STGCLK_USB_REFCLK 7
-#define JH7110_STGCLK_PCIE0_AXI 8
+/* STGCRG clocks */
+#define JH7110_STGCLK_HIFI4_CLK_CORE 0
+#define JH7110_STGCLK_USB0_APB 1
+#define JH7110_STGCLK_USB0_UTMI_APB 2
+#define JH7110_STGCLK_USB0_AXI 3
+#define JH7110_STGCLK_USB0_LPM 4
+#define JH7110_STGCLK_USB0_STB 5
+#define JH7110_STGCLK_USB0_APP_125 6
+#define JH7110_STGCLK_USB0_REFCLK 7
+#define JH7110_STGCLK_PCIE0_AXI_MST0 8
#define JH7110_STGCLK_PCIE0_APB 9
#define JH7110_STGCLK_PCIE0_TL 10
-#define JH7110_STGCLK_PCIE1_AXI 11
+#define JH7110_STGCLK_PCIE1_AXI_MST0 11
#define JH7110_STGCLK_PCIE1_APB 12
#define JH7110_STGCLK_PCIE1_TL 13
-#define JH7110_STGCLK_PCIE01_MAIN 14
-#define JH7110_STGCLK_SEC_HCLK 15
-#define JH7110_STGCLK_SEC_MISCAHB 16
-#define JH7110_STGCLK_MTRX_GRP0_MAIN 17
-#define JH7110_STGCLK_MTRX_GRP0_BUS 18
-#define JH7110_STGCLK_MTRX_GRP0_STG 19
-#define JH7110_STGCLK_MTRX_GRP1_MAIN 20
-#define JH7110_STGCLK_MTRX_GRP1_BUS 21
-#define JH7110_STGCLK_MTRX_GRP1_STG 22
-#define JH7110_STGCLK_MTRX_GRP1_HIFI 23
+#define JH7110_STGCLK_PCIE_SLV_MAIN 14
+#define JH7110_STGCLK_SEC_AHB 15
+#define JH7110_STGCLK_SEC_MISC_AHB 16
+#define JH7110_STGCLK_GRP0_MAIN 17
+#define JH7110_STGCLK_GRP0_BUS 18
+#define JH7110_STGCLK_GRP0_STG 19
+#define JH7110_STGCLK_GRP1_MAIN 20
+#define JH7110_STGCLK_GRP1_BUS 21
+#define JH7110_STGCLK_GRP1_STG 22
+#define JH7110_STGCLK_GRP1_HIFI 23
#define JH7110_STGCLK_E2_RTC 24
#define JH7110_STGCLK_E2_CORE 25
#define JH7110_STGCLK_E2_DBG 26
@@ -255,4 +259,44 @@
#define JH7110_STGCLK_END 29
-#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */
+/* ISPCRG clocks */
+#define JH7110_ISPCLK_DOM4_APB_FUNC 0
+#define JH7110_ISPCLK_MIPI_RX0_PXL 1
+#define JH7110_ISPCLK_DVP_INV 2
+#define JH7110_ISPCLK_M31DPHY_CFG_IN 3
+#define JH7110_ISPCLK_M31DPHY_REF_IN 4
+#define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5
+#define JH7110_ISPCLK_VIN_APB 6
+#define JH7110_ISPCLK_VIN_SYS 7
+#define JH7110_ISPCLK_VIN_PIXEL_IF0 8
+#define JH7110_ISPCLK_VIN_PIXEL_IF1 9
+#define JH7110_ISPCLK_VIN_PIXEL_IF2 10
+#define JH7110_ISPCLK_VIN_PIXEL_IF3 11
+#define JH7110_ISPCLK_VIN_P_AXI_WR 12
+#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13
+
+#define JH7110_ISPCLK_END 14
+
+/* VOUTCRG clocks */
+#define JH7110_VOUTCLK_APB 0
+#define JH7110_VOUTCLK_DC8200_PIX 1
+#define JH7110_VOUTCLK_DSI_SYS 2
+#define JH7110_VOUTCLK_TX_ESC 3
+#define JH7110_VOUTCLK_DC8200_AXI 4
+#define JH7110_VOUTCLK_DC8200_CORE 5
+#define JH7110_VOUTCLK_DC8200_AHB 6
+#define JH7110_VOUTCLK_DC8200_PIX0 7
+#define JH7110_VOUTCLK_DC8200_PIX1 8
+#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9
+#define JH7110_VOUTCLK_DSITX_APB 10
+#define JH7110_VOUTCLK_DSITX_SYS 11
+#define JH7110_VOUTCLK_DSITX_DPI 12
+#define JH7110_VOUTCLK_DSITX_TXESC 13
+#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14
+#define JH7110_VOUTCLK_HDMI_TX_MCLK 15
+#define JH7110_VOUTCLK_HDMI_TX_BCLK 16
+#define JH7110_VOUTCLK_HDMI_TX_SYS 17
+
+#define JH7110_VOUTCLK_END 18
+
+#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
--
2.43.2
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v1 2/4] dt-bindings: reset: jh7110: Sync with Linux
2024-06-03 13:27 [PATCH v1 0/4] Sync StarFive JH7110 clock and reset dt-bindings with Linux Hal Feng
2024-06-03 13:27 ` [PATCH v1 1/4] dt-bindings: clock: jh7110: Sync " Hal Feng
@ 2024-06-03 13:27 ` Hal Feng
2024-06-03 13:27 ` [PATCH v1 3/4] clk: starfive: jh7110: Sync clock definitions " Hal Feng
` (2 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Hal Feng @ 2024-06-03 13:27 UTC (permalink / raw)
To: Leo Yu-Chi Liang, Tom Rini, Lukasz Majewski, Sean Anderson,
Rick Chen, Heinrich Schuchardt, Nam Cao, Bo Gan, Yanhong Wang,
Emil Renner Berthing, Minda Chen, Hal Feng
Cc: u-boot
Sync JH7110 reset dt-bindings with Linux, which is the same with
dts/upstream/include/dt-bindings/reset/starfive,jh7110-crg.h
except copyright.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../dt-bindings/reset/starfive,jh7110-crg.h | 144 +++++++++++-------
1 file changed, 88 insertions(+), 56 deletions(-)
diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
index 1d596581da..771b1aecd0 100644
--- a/include/dt-bindings/reset/starfive,jh7110-crg.h
+++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
@@ -5,13 +5,13 @@
* Author: Yanhong Wang <yanhong.wang@starfivetech.com>
*/
-#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
-#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
+#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
+#define __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
/* SYSCRG resets */
-#define JH7110_SYSRST_JTAG2APB 0
-#define JH7110_SYSRST_SYSCON 1
-#define JH7110_SYSRST_IOMUX_APB 2
+#define JH7110_SYSRST_JTAG_APB 0
+#define JH7110_SYSRST_SYSCON_APB 1
+#define JH7110_SYSRST_IOMUX_APB 2
#define JH7110_SYSRST_BUS 3
#define JH7110_SYSRST_DEBUG 4
#define JH7110_SYSRST_CORE0 5
@@ -29,10 +29,10 @@
#define JH7110_SYSRST_TRACE2 17
#define JH7110_SYSRST_TRACE3 18
#define JH7110_SYSRST_TRACE4 19
-#define JH7110_SYSRST_TRACE_COM 20
+#define JH7110_SYSRST_TRACE_COM 20
#define JH7110_SYSRST_GPU_APB 21
#define JH7110_SYSRST_GPU_DOMA 22
-#define JH7110_SYSRST_NOC_BUS_APB_BUS 23
+#define JH7110_SYSRST_NOC_BUS_APB 23
#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24
#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25
#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26
@@ -43,17 +43,17 @@
#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31
#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32
-#define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33
-#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN 34
-#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN 35
-#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV 36
-#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37
+#define JH7110_SYSRST_AXI_CFG1_AHB 33
+#define JH7110_SYSRST_AXI_CFG1_MAIN 34
+#define JH7110_SYSRST_AXI_CFG0_MAIN 35
+#define JH7110_SYSRST_AXI_CFG0_MAIN_DIV 36
+#define JH7110_SYSRST_AXI_CFG0_HIFI4 37
#define JH7110_SYSRST_DDR_AXI 38
#define JH7110_SYSRST_DDR_OSC 39
#define JH7110_SYSRST_DDR_APB 40
-#define JH7110_SYSRST_DOM_ISP_TOP_N 41
-#define JH7110_SYSRST_DOM_ISP_TOP_AXI 42
-#define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43
+#define JH7110_SYSRST_ISP_TOP 41
+#define JH7110_SYSRST_ISP_TOP_AXI 42
+#define JH7110_SYSRST_VOUT_TOP_SRC 43
#define JH7110_SYSRST_CODAJ12_AXI 44
#define JH7110_SYSRST_CODAJ12_CORE 45
#define JH7110_SYSRST_CODAJ12_APB 46
@@ -61,8 +61,8 @@
#define JH7110_SYSRST_WAVE511_BPU 48
#define JH7110_SYSRST_WAVE511_VCE 49
#define JH7110_SYSRST_WAVE511_APB 50
-#define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51
-#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN 52
+#define JH7110_SYSRST_VDEC_JPG 51
+#define JH7110_SYSRST_VDEC_MAIN 52
#define JH7110_SYSRST_AXIMEM0_AXI 53
#define JH7110_SYSRST_WAVE420L_AXI 54
#define JH7110_SYSRST_WAVE420L_BPU 55
@@ -75,11 +75,11 @@
#define JH7110_SYSRST_QSPI_APB 62
#define JH7110_SYSRST_QSPI_REF 63
-#define JH7110_SYSRST_SDIO0_AHB 64
-#define JH7110_SYSRST_SDIO1_AHB 65
-#define JH7110_SYSRST_GMAC1_AXI 66
-#define JH7110_SYSRST_GMAC1_AHB 67
-#define JH7110_SYSRST_MAILBOX 68
+#define JH7110_SYSRST_SDIO0_AHB 64
+#define JH7110_SYSRST_SDIO1_AHB 65
+#define JH7110_SYSRST_GMAC1_AXI 66
+#define JH7110_SYSRST_GMAC1_AHB 67
+#define JH7110_SYSRST_MAILBOX_APB 68
#define JH7110_SYSRST_SPI0_APB 69
#define JH7110_SYSRST_SPI1_APB 70
#define JH7110_SYSRST_SPI2_APB 71
@@ -94,24 +94,24 @@
#define JH7110_SYSRST_I2C4_APB 80
#define JH7110_SYSRST_I2C5_APB 81
#define JH7110_SYSRST_I2C6_APB 82
-#define JH7110_SYSRST_UART0_APB 83
+#define JH7110_SYSRST_UART0_APB 83
#define JH7110_SYSRST_UART0_CORE 84
-#define JH7110_SYSRST_UART1_APB 85
+#define JH7110_SYSRST_UART1_APB 85
#define JH7110_SYSRST_UART1_CORE 86
-#define JH7110_SYSRST_UART2_APB 87
+#define JH7110_SYSRST_UART2_APB 87
#define JH7110_SYSRST_UART2_CORE 88
-#define JH7110_SYSRST_UART3_APB 89
+#define JH7110_SYSRST_UART3_APB 89
#define JH7110_SYSRST_UART3_CORE 90
-#define JH7110_SYSRST_UART4_APB 91
+#define JH7110_SYSRST_UART4_APB 91
#define JH7110_SYSRST_UART4_CORE 92
-#define JH7110_SYSRST_UART5_APB 93
+#define JH7110_SYSRST_UART5_APB 93
#define JH7110_SYSRST_UART5_CORE 94
-#define JH7110_SYSRST_SPDIF_APB 95
+#define JH7110_SYSRST_SPDIF_APB 95
#define JH7110_SYSRST_PWMDAC_APB 96
#define JH7110_SYSRST_PDM_DMIC 97
#define JH7110_SYSRST_PDM_APB 98
-#define JH7110_SYSRST_I2SRX_APB 99
+#define JH7110_SYSRST_I2SRX_APB 99
#define JH7110_SYSRST_I2SRX_BCLK 100
#define JH7110_SYSRST_I2STX0_APB 101
#define JH7110_SYSRST_I2STX0_BCLK 102
@@ -124,26 +124,26 @@
#define JH7110_SYSRST_WDT_APB 109
#define JH7110_SYSRST_WDT_CORE 110
#define JH7110_SYSRST_CAN0_APB 111
-#define JH7110_SYSRST_CAN0_CORE 112
+#define JH7110_SYSRST_CAN0_CORE 112
#define JH7110_SYSRST_CAN0_TIMER 113
#define JH7110_SYSRST_CAN1_APB 114
-#define JH7110_SYSRST_CAN1_CORE 115
+#define JH7110_SYSRST_CAN1_CORE 115
#define JH7110_SYSRST_CAN1_TIMER 116
-#define JH7110_SYSRST_TIMER_APB 117
+#define JH7110_SYSRST_TIMER_APB 117
#define JH7110_SYSRST_TIMER0 118
#define JH7110_SYSRST_TIMER1 119
#define JH7110_SYSRST_TIMER2 120
#define JH7110_SYSRST_TIMER3 121
#define JH7110_SYSRST_INT_CTRL_APB 122
#define JH7110_SYSRST_TEMP_APB 123
-#define JH7110_SYSRST_TEMP_CORE 124
+#define JH7110_SYSRST_TEMP_CORE 124
#define JH7110_SYSRST_JTAG_CERTIFICATION 125
#define JH7110_SYSRST_END 126
/* AONCRG resets */
-#define JH7110_AONRST_GMAC0_AXI 0
-#define JH7110_AONRST_GMAC0_AHB 1
+#define JH7110_AONRST_GMAC0_AXI 0
+#define JH7110_AONRST_GMAC0_AHB 1
#define JH7110_AONRST_IOMUX 2
#define JH7110_AONRST_PMU_APB 3
#define JH7110_AONRST_PMU_WKUP 4
@@ -154,30 +154,62 @@
#define JH7110_AONRST_END 8
/* STGCRG resets */
-#define JH7110_STGRST_SYSCON_PRESETN 0
+#define JH7110_STGRST_SYSCON 0
#define JH7110_STGRST_HIFI4_CORE 1
-#define JH7110_STGRST_HIFI4_AXI 2
-#define JH7110_STGRST_SEC_TOP_HRESETN 3
+#define JH7110_STGRST_HIFI4_AXI 2
+#define JH7110_STGRST_SEC_AHB 3
#define JH7110_STGRST_E24_CORE 4
-#define JH7110_STGRST_DMA1P_AXI 5
-#define JH7110_STGRST_DMA1P_AHB 6
-#define JH7110_STGRST_USB_AXI 7
-#define JH7110_STGRST_USB_APB 8
-#define JH7110_STGRST_USB_UTMI_APB 9
-#define JH7110_STGRST_USB_PWRUP 10
-#define JH7110_STGRST_PCIE0_MST0 11
-#define JH7110_STGRST_PCIE0_SLV0 12
-#define JH7110_STGRST_PCIE0_SLV 13
-#define JH7110_STGRST_PCIE0_BRG 14
+#define JH7110_STGRST_DMA1P_AXI 5
+#define JH7110_STGRST_DMA1P_AHB 6
+#define JH7110_STGRST_USB0_AXI 7
+#define JH7110_STGRST_USB0_APB 8
+#define JH7110_STGRST_USB0_UTMI_APB 9
+#define JH7110_STGRST_USB0_PWRUP 10
+#define JH7110_STGRST_PCIE0_AXI_MST0 11
+#define JH7110_STGRST_PCIE0_AXI_SLV0 12
+#define JH7110_STGRST_PCIE0_AXI_SLV 13
+#define JH7110_STGRST_PCIE0_BRG 14
#define JH7110_STGRST_PCIE0_CORE 15
-#define JH7110_STGRST_PCIE0_APB 16
-#define JH7110_STGRST_PCIE1_MST0 17
-#define JH7110_STGRST_PCIE1_SLV0 18
-#define JH7110_STGRST_PCIE1_SLV 19
-#define JH7110_STGRST_PCIE1_BRG 20
+#define JH7110_STGRST_PCIE0_APB 16
+#define JH7110_STGRST_PCIE1_AXI_MST0 17
+#define JH7110_STGRST_PCIE1_AXI_SLV0 18
+#define JH7110_STGRST_PCIE1_AXI_SLV 19
+#define JH7110_STGRST_PCIE1_BRG 20
#define JH7110_STGRST_PCIE1_CORE 21
-#define JH7110_STGRST_PCIE1_APB 22
+#define JH7110_STGRST_PCIE1_APB 22
#define JH7110_STGRST_END 23
-#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */
+/* ISPCRG resets */
+#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0
+#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C 1
+#define JH7110_ISPRST_M31DPHY_HW 2
+#define JH7110_ISPRST_M31DPHY_B09_AON 3
+#define JH7110_ISPRST_VIN_APB 4
+#define JH7110_ISPRST_VIN_PIXEL_IF0 5
+#define JH7110_ISPRST_VIN_PIXEL_IF1 6
+#define JH7110_ISPRST_VIN_PIXEL_IF2 7
+#define JH7110_ISPRST_VIN_PIXEL_IF3 8
+#define JH7110_ISPRST_VIN_SYS 9
+#define JH7110_ISPRST_VIN_P_AXI_RD 10
+#define JH7110_ISPRST_VIN_P_AXI_WR 11
+
+#define JH7110_ISPRST_END 12
+
+/* VOUTCRG resets */
+#define JH7110_VOUTRST_DC8200_AXI 0
+#define JH7110_VOUTRST_DC8200_AHB 1
+#define JH7110_VOUTRST_DC8200_CORE 2
+#define JH7110_VOUTRST_DSITX_DPI 3
+#define JH7110_VOUTRST_DSITX_APB 4
+#define JH7110_VOUTRST_DSITX_RXESC 5
+#define JH7110_VOUTRST_DSITX_SYS 6
+#define JH7110_VOUTRST_DSITX_TXBYTEHS 7
+#define JH7110_VOUTRST_DSITX_TXESC 8
+#define JH7110_VOUTRST_HDMI_TX_HDMI 9
+#define JH7110_VOUTRST_MIPITX_DPHY_SYS 10
+#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS 11
+
+#define JH7110_VOUTRST_END 12
+
+#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
--
2.43.2
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v1 3/4] clk: starfive: jh7110: Sync clock definitions with Linux
2024-06-03 13:27 [PATCH v1 0/4] Sync StarFive JH7110 clock and reset dt-bindings with Linux Hal Feng
2024-06-03 13:27 ` [PATCH v1 1/4] dt-bindings: clock: jh7110: Sync " Hal Feng
2024-06-03 13:27 ` [PATCH v1 2/4] dt-bindings: reset: " Hal Feng
@ 2024-06-03 13:27 ` Hal Feng
2024-06-03 13:27 ` [PATCH v1 4/4] riscv: dts: jh7110: Sync clock and reset " Hal Feng
2024-06-03 20:32 ` [PATCH v1 0/4] Sync StarFive JH7110 clock and reset dt-bindings " E Shattow
4 siblings, 0 replies; 10+ messages in thread
From: Hal Feng @ 2024-06-03 13:27 UTC (permalink / raw)
To: Leo Yu-Chi Liang, Tom Rini, Lukasz Majewski, Sean Anderson,
Rick Chen, Heinrich Schuchardt, Nam Cao, Bo Gan, Yanhong Wang,
Emil Renner Berthing, Minda Chen, Hal Feng
Cc: u-boot
The JH7110 clock dt-bindings is synchronized with Linux,
so update the clock definitions in drivers accordingly.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
drivers/clk/starfive/clk-jh7110-pll.c | 6 ++--
drivers/clk/starfive/clk-jh7110.c | 44 +++++++++++++--------------
2 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c
index 1568a1f4cd..96beacb4fa 100644
--- a/drivers/clk/starfive/clk-jh7110-pll.c
+++ b/drivers/clk/starfive/clk-jh7110-pll.c
@@ -375,13 +375,13 @@ static int jh7110_pll_clk_probe(struct udevice *dev)
if (sysreg == FDT_ADDR_T_NONE)
return -EINVAL;
- clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL0_OUT),
+ clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL0_OUT),
starfive_jh7110_pll("pll0_out", "oscillator", reg,
(void __iomem *)sysreg, &starfive_jh7110_pll0));
- clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL1_OUT),
+ clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL1_OUT),
starfive_jh7110_pll("pll1_out", "oscillator", reg,
(void __iomem *)sysreg, &starfive_jh7110_pll1));
- clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL2_OUT),
+ clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL2_OUT),
starfive_jh7110_pll("pll2_out", "oscillator", reg,
(void __iomem *)sysreg, &starfive_jh7110_pll2));
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c
index a38694809a..523342128e 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -496,37 +496,37 @@ static int jh7110_stgcrg_init(struct udevice *dev)
{
struct jh7110_clk_priv *priv = dev_get_priv(dev);
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APB),
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_APB),
starfive_clk_gate(priv->reg,
"usb_apb", "apb_bus",
- OFFSET(JH7110_STGCLK_USB_APB)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_UTMI_APB),
+ OFFSET(JH7110_STGCLK_USB0_APB)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_UTMI_APB),
starfive_clk_gate(priv->reg,
"usb_utmi_apb", "apb_bus",
- OFFSET(JH7110_STGCLK_USB_UTMI_APB)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_AXI),
+ OFFSET(JH7110_STGCLK_USB0_UTMI_APB)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_AXI),
starfive_clk_gate(priv->reg,
"usb_axi", "stg_axiahb",
- OFFSET(JH7110_STGCLK_USB_AXI)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_LPM),
+ OFFSET(JH7110_STGCLK_USB0_AXI)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_LPM),
starfive_clk_gate_divider(priv->reg,
"usb_lpm", "oscillator",
- OFFSET(JH7110_STGCLK_USB_LPM), 2));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_STB),
+ OFFSET(JH7110_STGCLK_USB0_LPM), 2));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_STB),
starfive_clk_gate_divider(priv->reg,
"usb_stb", "oscillator",
- OFFSET(JH7110_STGCLK_USB_STB), 3));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APP_125),
+ OFFSET(JH7110_STGCLK_USB0_STB), 3));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_APP_125),
starfive_clk_gate(priv->reg,
"usb_app_125", "usb_125m",
- OFFSET(JH7110_STGCLK_USB_APP_125)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_REFCLK),
+ OFFSET(JH7110_STGCLK_USB0_APP_125)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_REFCLK),
starfive_clk_divider(priv->reg, "usb_refclk", "oscillator",
- OFFSET(JH7110_STGCLK_USB_REFCLK), 2));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI),
+ OFFSET(JH7110_STGCLK_USB0_REFCLK), 2));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI_MST0),
starfive_clk_gate(priv->reg,
"pcie0_axi", "stg_axiahb",
- OFFSET(JH7110_STGCLK_PCIE0_AXI)));
+ OFFSET(JH7110_STGCLK_PCIE0_AXI_MST0)));
clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_APB),
starfive_clk_gate(priv->reg,
"pcie0_apb", "apb_bus",
@@ -535,10 +535,10 @@ static int jh7110_stgcrg_init(struct udevice *dev)
starfive_clk_gate(priv->reg,
"pcie0_tl", "stg_axiahb",
OFFSET(JH7110_STGCLK_PCIE0_TL)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI),
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI_MST0),
starfive_clk_gate(priv->reg,
"pcie1_axi", "stg_axiahb",
- OFFSET(JH7110_STGCLK_PCIE1_AXI)));
+ OFFSET(JH7110_STGCLK_PCIE1_AXI_MST0)));
clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_APB),
starfive_clk_gate(priv->reg,
"pcie1_apb", "apb_bus",
@@ -549,14 +549,14 @@ static int jh7110_stgcrg_init(struct udevice *dev)
OFFSET(JH7110_STGCLK_PCIE1_TL)));
/* Security clocks */
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK),
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_AHB),
starfive_clk_gate(priv->reg,
"sec_ahb", "stg_axiahb",
- OFFSET(JH7110_STGCLK_SEC_HCLK)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB),
+ OFFSET(JH7110_STGCLK_SEC_AHB)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISC_AHB),
starfive_clk_gate(priv->reg,
"sec_misc_ahb", "stg_axiahb",
- OFFSET(JH7110_STGCLK_SEC_MISCAHB)));
+ OFFSET(JH7110_STGCLK_SEC_MISC_AHB)));
return 0;
}
--
2.43.2
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v1 4/4] riscv: dts: jh7110: Sync clock and reset definitions with Linux
2024-06-03 13:27 [PATCH v1 0/4] Sync StarFive JH7110 clock and reset dt-bindings with Linux Hal Feng
` (2 preceding siblings ...)
2024-06-03 13:27 ` [PATCH v1 3/4] clk: starfive: jh7110: Sync clock definitions " Hal Feng
@ 2024-06-03 13:27 ` Hal Feng
2024-06-03 20:32 ` [PATCH v1 0/4] Sync StarFive JH7110 clock and reset dt-bindings " E Shattow
4 siblings, 0 replies; 10+ messages in thread
From: Hal Feng @ 2024-06-03 13:27 UTC (permalink / raw)
To: Leo Yu-Chi Liang, Tom Rini, Lukasz Majewski, Sean Anderson,
Rick Chen, Heinrich Schuchardt, Nam Cao, Bo Gan, Yanhong Wang,
Emil Renner Berthing, Minda Chen, Hal Feng
Cc: u-boot
The JH7110 clock and reset dt-bindings are synchronized with Linux,
so update the clock and reset definitions in device tree accordingly.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../dts/jh7110-starfive-visionfive-2.dtsi | 6 ++--
arch/riscv/dts/jh7110-u-boot.dtsi | 2 +-
arch/riscv/dts/jh7110.dtsi | 28 +++++++++----------
3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index e11babc1cd..2666fd4696 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -334,9 +334,9 @@
<&syscrg JH7110_SYSCLK_BUS_ROOT>,
<&syscrg JH7110_SYSCLK_PERH_ROOT>,
<&syscrg JH7110_SYSCLK_QSPI_REF>;
- assigned-clock-parents = <&pllclk JH7110_SYSCLK_PLL0_OUT>,
- <&pllclk JH7110_SYSCLK_PLL2_OUT>,
- <&pllclk JH7110_SYSCLK_PLL2_OUT>,
+ assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
+ <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+ <&pllclk JH7110_PLLCLK_PLL2_OUT>,
<&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
assigned-clock-rates = <0>, <0>, <0>, <0>;
};
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index c09d5c9170..56530cf4c2 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -62,7 +62,7 @@
<&syscrg JH7110_SYSRST_DDR_OSC>,
<&syscrg JH7110_SYSRST_DDR_APB>;
reset-names = "axi", "osc", "apb";
- clocks = <&syscrg JH7110_SYSCLK_PLL1_OUT>;
+ clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
clock-names = "pll1_out";
clock-frequency = <2133>;
};
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 2cdc683d49..dbce57c421 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -503,9 +503,9 @@
<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
<&tdm_ext>, <&mclk_ext>,
- <&pllclk JH7110_SYSCLK_PLL0_OUT>,
- <&pllclk JH7110_SYSCLK_PLL1_OUT>,
- <&pllclk JH7110_SYSCLK_PLL2_OUT>;
+ <&pllclk JH7110_PLLCLK_PLL0_OUT>,
+ <&pllclk JH7110_PLLCLK_PLL1_OUT>,
+ <&pllclk JH7110_PLLCLK_PLL2_OUT>;
clock-names = "osc", "gmac1_rmii_refin",
"gmac1_rgmii_rxin",
"i2stx_bclk_ext", "i2stx_lrck_ext",
@@ -646,10 +646,10 @@
rng: rng@1600c000 {
compatible = "starfive,jh7110-trng";
reg = <0x0 0x1600C000 0x0 0x4000>;
- clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
- <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
+ clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
+ <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
clock-names = "hclk", "ahb";
- resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
+ resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
interrupts = <30>;
};
@@ -707,12 +707,12 @@
bus-range = <0x0 0xff>;
clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
<&stgcrg JH7110_STGCLK_PCIE0_TL>,
- <&stgcrg JH7110_STGCLK_PCIE0_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
<&stgcrg JH7110_STGCLK_PCIE0_APB>;
clock-names = "noc", "tl", "axi", "apb";
- resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
- <&stgcrg JH7110_STGRST_PCIE0_SLV0>,
- <&stgcrg JH7110_STGRST_PCIE0_SLV>,
+ resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
+ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
+ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
<&stgcrg JH7110_STGRST_PCIE0_BRG>,
<&stgcrg JH7110_STGRST_PCIE0_CORE>,
<&stgcrg JH7110_STGRST_PCIE0_APB>;
@@ -744,12 +744,12 @@
bus-range = <0x0 0xff>;
clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
<&stgcrg JH7110_STGCLK_PCIE1_TL>,
- <&stgcrg JH7110_STGCLK_PCIE1_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
<&stgcrg JH7110_STGCLK_PCIE1_APB>;
clock-names = "noc", "tl", "axi", "apb";
- resets = <&stgcrg JH7110_STGRST_PCIE1_MST0>,
- <&stgcrg JH7110_STGRST_PCIE1_SLV0>,
- <&stgcrg JH7110_STGRST_PCIE1_SLV>,
+ resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
+ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
+ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
<&stgcrg JH7110_STGRST_PCIE1_BRG>,
<&stgcrg JH7110_STGRST_PCIE1_CORE>,
<&stgcrg JH7110_STGRST_PCIE1_APB>;
--
2.43.2
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v1 0/4] Sync StarFive JH7110 clock and reset dt-bindings with Linux
2024-06-03 13:27 [PATCH v1 0/4] Sync StarFive JH7110 clock and reset dt-bindings with Linux Hal Feng
` (3 preceding siblings ...)
2024-06-03 13:27 ` [PATCH v1 4/4] riscv: dts: jh7110: Sync clock and reset " Hal Feng
@ 2024-06-03 20:32 ` E Shattow
2024-06-05 1:56 ` Hal Feng
4 siblings, 1 reply; 10+ messages in thread
From: E Shattow @ 2024-06-03 20:32 UTC (permalink / raw)
To: Hal Feng
Cc: Leo Yu-Chi Liang, Tom Rini, Lukasz Majewski, Sean Anderson,
Rick Chen, Heinrich Schuchardt, Nam Cao, Bo Gan, Yanhong Wang,
Emil Renner Berthing, Minda Chen, u-boot
Hi Hal,
Instead of manual dt-bindings sync can we please adopt OF_UPSTREAM for JH7110 ?
-E
On Mon, Jun 3, 2024 at 6:57 AM Hal Feng <hal.feng@starfivetech.com> wrote:
>
> There are differences in clock / reset dt-bindings between U-Boot and
> Linux. Sync them, so it is feasible to use OF_UPSTREAM for StarFive
> JH7110 SoC.
>
> Hal Feng (4):
> dt-bindings: clock: jh7110: Sync with Linux
> dt-bindings: reset: jh7110: Sync with Linux
> clk: starfive: jh7110: Sync clock definitions with Linux
> riscv: dts: jh7110: Sync clock and reset definitions with Linux
>
> .../dts/jh7110-starfive-visionfive-2.dtsi | 6 +-
> arch/riscv/dts/jh7110-u-boot.dtsi | 2 +-
> arch/riscv/dts/jh7110.dtsi | 28 +--
> drivers/clk/starfive/clk-jh7110-pll.c | 6 +-
> drivers/clk/starfive/clk-jh7110.c | 44 ++---
> .../dt-bindings/clock/starfive,jh7110-crg.h | 180 +++++++++++-------
> .../dt-bindings/reset/starfive,jh7110-crg.h | 144 ++++++++------
> 7 files changed, 243 insertions(+), 167 deletions(-)
>
>
> base-commit: ea722aa5eb33740ae77e8816aeb72b385e621cd0
> --
> 2.43.2
>
^ permalink raw reply [flat|nested] 10+ messages in thread* RE: [PATCH v1 0/4] Sync StarFive JH7110 clock and reset dt-bindings with Linux
2024-06-03 20:32 ` [PATCH v1 0/4] Sync StarFive JH7110 clock and reset dt-bindings " E Shattow
@ 2024-06-05 1:56 ` Hal Feng
2024-06-05 14:35 ` Tom Rini
0 siblings, 1 reply; 10+ messages in thread
From: Hal Feng @ 2024-06-05 1:56 UTC (permalink / raw)
To: E Shattow
Cc: Leo Yu-Chi Liang, Tom Rini, Lukasz Majewski, Sean Anderson,
Rick Chen, Heinrich Schuchardt, Nam Cao, Bo Gan, Yanhong Wang,
Emil Renner Berthing, Minda Chen, u-boot@lists.denx.de
> On 04.06.24 04:32, E Shattow wrote:
> Hi Hal,
>
> Instead of manual dt-bindings sync can we please adopt OF_UPSTREAM for
> JH7110 ?
Yeah, I will try to do it recently, although I am not sure whether the U-Boot
drivers and Linux drivers are compatible so that they can use the same DT.
Best regards,
Hal
>
>
> On Mon, Jun 3, 2024 at 6:57 AM Hal Feng <hal.feng@starfivetech.com> wrote:
> >
> > There are differences in clock / reset dt-bindings between U-Boot and
> > Linux. Sync them, so it is feasible to use OF_UPSTREAM for StarFive
> > JH7110 SoC.
> >
> > Hal Feng (4):
> > dt-bindings: clock: jh7110: Sync with Linux
> > dt-bindings: reset: jh7110: Sync with Linux
> > clk: starfive: jh7110: Sync clock definitions with Linux
> > riscv: dts: jh7110: Sync clock and reset definitions with Linux
> >
> > .../dts/jh7110-starfive-visionfive-2.dtsi | 6 +-
> > arch/riscv/dts/jh7110-u-boot.dtsi | 2 +-
> > arch/riscv/dts/jh7110.dtsi | 28 +--
> > drivers/clk/starfive/clk-jh7110-pll.c | 6 +-
> > drivers/clk/starfive/clk-jh7110.c | 44 ++---
> > .../dt-bindings/clock/starfive,jh7110-crg.h | 180 +++++++++++-------
> > .../dt-bindings/reset/starfive,jh7110-crg.h | 144 ++++++++------
> > 7 files changed, 243 insertions(+), 167 deletions(-)
> >
> >
> > base-commit: ea722aa5eb33740ae77e8816aeb72b385e621cd0
> > --
> > 2.43.2
> >
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 0/4] Sync StarFive JH7110 clock and reset dt-bindings with Linux
2024-06-05 1:56 ` Hal Feng
@ 2024-06-05 14:35 ` Tom Rini
2024-06-05 15:37 ` Conor Dooley
0 siblings, 1 reply; 10+ messages in thread
From: Tom Rini @ 2024-06-05 14:35 UTC (permalink / raw)
To: Hal Feng
Cc: E Shattow, Leo Yu-Chi Liang, Lukasz Majewski, Sean Anderson,
Rick Chen, Heinrich Schuchardt, Nam Cao, Bo Gan, Yanhong Wang,
Emil Renner Berthing, Minda Chen, u-boot@lists.denx.de
[-- Attachment #1: Type: text/plain, Size: 489 bytes --]
On Wed, Jun 05, 2024 at 01:56:13AM +0000, Hal Feng wrote:
> > On 04.06.24 04:32, E Shattow wrote:
> > Hi Hal,
> >
> > Instead of manual dt-bindings sync can we please adopt OF_UPSTREAM for
> > JH7110 ?
>
> Yeah, I will try to do it recently, although I am not sure whether the U-Boot
> drivers and Linux drivers are compatible so that they can use the same DT.
They must be compatible so that they can use the same DT, U-Boot needs
updating if it doesn't match.
--
Tom
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 0/4] Sync StarFive JH7110 clock and reset dt-bindings with Linux
2024-06-05 14:35 ` Tom Rini
@ 2024-06-05 15:37 ` Conor Dooley
2024-07-04 9:31 ` Hal Feng
0 siblings, 1 reply; 10+ messages in thread
From: Conor Dooley @ 2024-06-05 15:37 UTC (permalink / raw)
To: Tom Rini
Cc: Hal Feng, E Shattow, Leo Yu-Chi Liang, Lukasz Majewski,
Sean Anderson, Rick Chen, Heinrich Schuchardt, Nam Cao, Bo Gan,
Yanhong Wang, Emil Renner Berthing, Minda Chen,
u-boot@lists.denx.de
[-- Attachment #1: Type: text/plain, Size: 814 bytes --]
On Wed, Jun 05, 2024 at 08:35:15AM -0600, Tom Rini wrote:
> On Wed, Jun 05, 2024 at 01:56:13AM +0000, Hal Feng wrote:
> > > On 04.06.24 04:32, E Shattow wrote:
> > > Hi Hal,
> > >
> > > Instead of manual dt-bindings sync can we please adopt OF_UPSTREAM for
> > > JH7110 ?
> >
> > Yeah, I will try to do it recently, although I am not sure whether the U-Boot
> > drivers and Linux drivers are compatible so that they can use the same DT.
>
> They must be compatible so that they can use the same DT, U-Boot needs
> updating if it doesn't match.
Other than the naming, I think they are compatible. IIRC there were some
issues where U-Boot originally used different numbers to linux, but this
was fixed in commit 9a12e304dd ("dt-bindings: clock: jh7110: Modify clock
id to be same with Linux").
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^ permalink raw reply [flat|nested] 10+ messages in thread* RE: [PATCH v1 0/4] Sync StarFive JH7110 clock and reset dt-bindings with Linux
2024-06-05 15:37 ` Conor Dooley
@ 2024-07-04 9:31 ` Hal Feng
0 siblings, 0 replies; 10+ messages in thread
From: Hal Feng @ 2024-07-04 9:31 UTC (permalink / raw)
To: Conor Dooley, Tom Rini
Cc: E Shattow, Leo Yu-Chi Liang, Lukasz Majewski, Sean Anderson,
Rick Chen, Heinrich Schuchardt, Nam Cao, Bo Gan, Yanhong Wang,
Emil Renner Berthing, Minda Chen, u-boot@lists.denx.de
> On 05.06.24 23:38, Conor Dooley wrote:
> On Wed, Jun 05, 2024 at 08:35:15AM -0600, Tom Rini wrote:
> > On Wed, Jun 05, 2024 at 01:56:13AM +0000, Hal Feng wrote:
> > > > On 04.06.24 04:32, E Shattow wrote:
> > > > Hi Hal,
> > > >
> > > > Instead of manual dt-bindings sync can we please adopt OF_UPSTREAM
> > > > for
> > > > JH7110 ?
> > >
> > > Yeah, I will try to do it recently, although I am not sure whether
> > > the U-Boot drivers and Linux drivers are compatible so that they can use the
> same DT.
> >
> > They must be compatible so that they can use the same DT, U-Boot needs
> > updating if it doesn't match.
>
> Other than the naming, I think they are compatible. IIRC there were some issues
> where U-Boot originally used different numbers to linux, but this was fixed in
> commit 9a12e304dd ("dt-bindings: clock: jh7110: Modify clock id to be same
> with Linux").
I found the Linux DT of VisionFive 2 can not be applied to U-Boot directly. Some issues
need to be fixed such as making drivers compatible with Linux DT, unifying DT names.
I am preparing a new patchset. When I finish coding and testing, I will send it out.
Best regards,
Hal
^ permalink raw reply [flat|nested] 10+ messages in thread