* [PATCH v3] mem/cxl_type3: support 3, 6, 12 and 16 interleave ways
@ 2024-05-08 0:53 Yao Xingtao via
2024-05-24 9:31 ` Xingtao Yao (Fujitsu) via
0 siblings, 1 reply; 5+ messages in thread
From: Yao Xingtao via @ 2024-05-08 0:53 UTC (permalink / raw)
To: jonathan.cameron, fan.ni; +Cc: qemu-devel, Yao Xingtao
Since the kernel does not check the interleave capability, a
3-way, 6-way, 12-way or 16-way region can be create normally.
Applications can access the memory of 16-way region normally because
qemu can convert hpa to dpa correctly for the power of 2 interleave
ways, after kernel implementing the check, this kind of region will
not be created any more.
For non power of 2 interleave ways, applications could not access the
memory normally and may occur some unexpected behaviors, such as
segmentation fault.
So implements this feature is needed.
Link: https://lore.kernel.org/linux-cxl/3e84b919-7631-d1db-3e1d-33000f3f3868@fujitsu.com/
Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
---
hw/cxl/cxl-component-utils.c | 9 +++++++--
hw/mem/cxl_type3.c | 15 +++++++++++----
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index cd116c0401..473895948b 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -243,8 +243,13 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 1);
ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
POISON_ON_ERR_CAP, 0);
- ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY, 0);
- ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 16_WAY, 0);
+ if (type == CXL2_TYPE3_DEVICE) {
+ ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY, 1);
+ ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 16_WAY, 1);
+ } else {
+ ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY, 0);
+ ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 16_WAY, 0);
+ }
ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, UIO, 0);
ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
UIO_DECODER_COUNT, 0);
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 3e42490b6c..b755318838 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -804,10 +804,17 @@ static bool cxl_type3_dpa(CXLType3Dev *ct3d, hwaddr host_addr, uint64_t *dpa)
continue;
}
- *dpa = dpa_base +
- ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) |
- ((MAKE_64BIT_MASK(8 + ig + iw, 64 - 8 - ig - iw) & hpa_offset)
- >> iw));
+ if (iw < 8) {
+ *dpa = dpa_base +
+ ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) |
+ ((MAKE_64BIT_MASK(8 + ig + iw, 64 - 8 - ig - iw) & hpa_offset)
+ >> iw));
+ } else {
+ *dpa = dpa_base +
+ ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) |
+ ((((MAKE_64BIT_MASK(ig + iw, 64 - ig - iw) & hpa_offset)
+ >> (ig + iw)) / 3) << (ig + 8)));
+ }
return true;
}
--
2.37.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* RE: [PATCH v3] mem/cxl_type3: support 3, 6, 12 and 16 interleave ways
2024-05-08 0:53 [PATCH v3] mem/cxl_type3: support 3, 6, 12 and 16 interleave ways Yao Xingtao via
@ 2024-05-24 9:31 ` Xingtao Yao (Fujitsu) via
2024-06-06 8:07 ` Xingtao Yao (Fujitsu) via
0 siblings, 1 reply; 5+ messages in thread
From: Xingtao Yao (Fujitsu) via @ 2024-05-24 9:31 UTC (permalink / raw)
To: Xingtao Yao (Fujitsu), jonathan.cameron@huawei.com,
fan.ni@samsung.com
Cc: qemu-devel@nongnu.org
ping.
> -----Original Message-----
> From: Yao Xingtao <yaoxt.fnst@fujitsu.com>
> Sent: Wednesday, May 8, 2024 8:53 AM
> To: jonathan.cameron@huawei.com; fan.ni@samsung.com
> Cc: qemu-devel@nongnu.org; Yao, Xingtao/姚 幸涛 <yaoxt.fnst@fujitsu.com>
> Subject: [PATCH v3] mem/cxl_type3: support 3, 6, 12 and 16 interleave ways
>
> Since the kernel does not check the interleave capability, a
> 3-way, 6-way, 12-way or 16-way region can be create normally.
>
> Applications can access the memory of 16-way region normally because
> qemu can convert hpa to dpa correctly for the power of 2 interleave
> ways, after kernel implementing the check, this kind of region will
> not be created any more.
>
> For non power of 2 interleave ways, applications could not access the
> memory normally and may occur some unexpected behaviors, such as
> segmentation fault.
>
> So implements this feature is needed.
>
> Link:
> https://lore.kernel.org/linux-cxl/3e84b919-7631-d1db-3e1d-33000f3f3868@fujits
> u.com/
> Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
> ---
> hw/cxl/cxl-component-utils.c | 9 +++++++--
> hw/mem/cxl_type3.c | 15 +++++++++++----
> 2 files changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
> index cd116c0401..473895948b 100644
> --- a/hw/cxl/cxl-component-utils.c
> +++ b/hw/cxl/cxl-component-utils.c
> @@ -243,8 +243,13 @@ static void hdm_init_common(uint32_t *reg_state,
> uint32_t *write_msk,
> ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> INTERLEAVE_4K, 1);
> ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> POISON_ON_ERR_CAP, 0);
> - ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> 3_6_12_WAY, 0);
> - ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 16_WAY,
> 0);
> + if (type == CXL2_TYPE3_DEVICE) {
> + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> 3_6_12_WAY, 1);
> + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> 16_WAY, 1);
> + } else {
> + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> 3_6_12_WAY, 0);
> + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> 16_WAY, 0);
> + }
> ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, UIO, 0);
> ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> UIO_DECODER_COUNT, 0);
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index 3e42490b6c..b755318838 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -804,10 +804,17 @@ static bool cxl_type3_dpa(CXLType3Dev *ct3d, hwaddr
> host_addr, uint64_t *dpa)
> continue;
> }
>
> - *dpa = dpa_base +
> - ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) |
> - ((MAKE_64BIT_MASK(8 + ig + iw, 64 - 8 - ig - iw) & hpa_offset)
> - >> iw));
> + if (iw < 8) {
> + *dpa = dpa_base +
> + ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) |
> + ((MAKE_64BIT_MASK(8 + ig + iw, 64 - 8 - ig - iw) & hpa_offset)
> + >> iw));
> + } else {
> + *dpa = dpa_base +
> + ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) |
> + ((((MAKE_64BIT_MASK(ig + iw, 64 - ig - iw) & hpa_offset)
> + >> (ig + iw)) / 3) << (ig + 8)));
> + }
>
> return true;
> }
> --
> 2.37.3
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH v3] mem/cxl_type3: support 3, 6, 12 and 16 interleave ways
2024-05-24 9:31 ` Xingtao Yao (Fujitsu) via
@ 2024-06-06 8:07 ` Xingtao Yao (Fujitsu) via
2024-06-21 15:01 ` Jonathan Cameron via
0 siblings, 1 reply; 5+ messages in thread
From: Xingtao Yao (Fujitsu) via @ 2024-06-06 8:07 UTC (permalink / raw)
To: jonathan.cameron@huawei.com, fan.ni@samsung.com; +Cc: qemu-devel@nongnu.org
ping again.
> -----Original Message-----
> From: Yao, Xingtao/姚 幸涛 <yaoxt.fnst@fujitsu.com>
> Sent: Friday, May 24, 2024 5:31 PM
> To: Yao, Xingtao/姚 幸涛 <yaoxt.fnst@fujitsu.com>;
> jonathan.cameron@huawei.com; fan.ni@samsung.com
> Cc: qemu-devel@nongnu.org
> Subject: RE: [PATCH v3] mem/cxl_type3: support 3, 6, 12 and 16 interleave ways
>
> ping.
>
> > -----Original Message-----
> > From: Yao Xingtao <yaoxt.fnst@fujitsu.com>
> > Sent: Wednesday, May 8, 2024 8:53 AM
> > To: jonathan.cameron@huawei.com; fan.ni@samsung.com
> > Cc: qemu-devel@nongnu.org; Yao, Xingtao/姚 幸涛 <yaoxt.fnst@fujitsu.com>
> > Subject: [PATCH v3] mem/cxl_type3: support 3, 6, 12 and 16 interleave ways
> >
> > Since the kernel does not check the interleave capability, a
> > 3-way, 6-way, 12-way or 16-way region can be create normally.
> >
> > Applications can access the memory of 16-way region normally because
> > qemu can convert hpa to dpa correctly for the power of 2 interleave
> > ways, after kernel implementing the check, this kind of region will
> > not be created any more.
> >
> > For non power of 2 interleave ways, applications could not access the
> > memory normally and may occur some unexpected behaviors, such as
> > segmentation fault.
> >
> > So implements this feature is needed.
> >
> > Link:
> >
> https://lore.kernel.org/linux-cxl/3e84b919-7631-d1db-3e1d-33000f3f3868@fujits
> > u.com/
> > Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
> > ---
> > hw/cxl/cxl-component-utils.c | 9 +++++++--
> > hw/mem/cxl_type3.c | 15 +++++++++++----
> > 2 files changed, 18 insertions(+), 6 deletions(-)
> >
> > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
> > index cd116c0401..473895948b 100644
> > --- a/hw/cxl/cxl-component-utils.c
> > +++ b/hw/cxl/cxl-component-utils.c
> > @@ -243,8 +243,13 @@ static void hdm_init_common(uint32_t *reg_state,
> > uint32_t *write_msk,
> > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > INTERLEAVE_4K, 1);
> > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > POISON_ON_ERR_CAP, 0);
> > - ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > 3_6_12_WAY, 0);
> > - ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> 16_WAY,
> > 0);
> > + if (type == CXL2_TYPE3_DEVICE) {
> > + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > 3_6_12_WAY, 1);
> > + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > 16_WAY, 1);
> > + } else {
> > + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > 3_6_12_WAY, 0);
> > + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > 16_WAY, 0);
> > + }
> > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, UIO,
> 0);
> > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > UIO_DECODER_COUNT, 0);
> > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> > index 3e42490b6c..b755318838 100644
> > --- a/hw/mem/cxl_type3.c
> > +++ b/hw/mem/cxl_type3.c
> > @@ -804,10 +804,17 @@ static bool cxl_type3_dpa(CXLType3Dev *ct3d, hwaddr
> > host_addr, uint64_t *dpa)
> > continue;
> > }
> >
> > - *dpa = dpa_base +
> > - ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) |
> > - ((MAKE_64BIT_MASK(8 + ig + iw, 64 - 8 - ig - iw) & hpa_offset)
> > - >> iw));
> > + if (iw < 8) {
> > + *dpa = dpa_base +
> > + ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) |
> > + ((MAKE_64BIT_MASK(8 + ig + iw, 64 - 8 - ig - iw) &
> hpa_offset)
> > + >> iw));
> > + } else {
> > + *dpa = dpa_base +
> > + ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) |
> > + ((((MAKE_64BIT_MASK(ig + iw, 64 - ig - iw) & hpa_offset)
> > + >> (ig + iw)) / 3) << (ig + 8)));
> > + }
> >
> > return true;
> > }
> > --
> > 2.37.3
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3] mem/cxl_type3: support 3, 6, 12 and 16 interleave ways
2024-06-06 8:07 ` Xingtao Yao (Fujitsu) via
@ 2024-06-21 15:01 ` Jonathan Cameron via
2024-06-24 0:03 ` Xingtao Yao (Fujitsu) via
0 siblings, 1 reply; 5+ messages in thread
From: Jonathan Cameron via @ 2024-06-21 15:01 UTC (permalink / raw)
To: Xingtao Yao (Fujitsu); +Cc: fan.ni@samsung.com, qemu-devel@nongnu.org
On Thu, 6 Jun 2024 08:07:27 +0000
"Xingtao Yao (Fujitsu)" <yaoxt.fnst@fujitsu.com> wrote:
> ping again.
Sorry for delay - I was waiting for some of the tree I'm carrying
to get picked up before applying anything new.
I haven't yet tested this as fully as I'd like for upstreaming, but
with that in mind applied to my cxl staging tree.
Thanks,
Jonathan
>
> > -----Original Message-----
> > From: Yao, Xingtao/姚 幸涛 <yaoxt.fnst@fujitsu.com>
> > Sent: Friday, May 24, 2024 5:31 PM
> > To: Yao, Xingtao/姚 幸涛 <yaoxt.fnst@fujitsu.com>;
> > jonathan.cameron@huawei.com; fan.ni@samsung.com
> > Cc: qemu-devel@nongnu.org
> > Subject: RE: [PATCH v3] mem/cxl_type3: support 3, 6, 12 and 16 interleave ways
> >
> > ping.
> >
> > > -----Original Message-----
> > > From: Yao Xingtao <yaoxt.fnst@fujitsu.com>
> > > Sent: Wednesday, May 8, 2024 8:53 AM
> > > To: jonathan.cameron@huawei.com; fan.ni@samsung.com
> > > Cc: qemu-devel@nongnu.org; Yao, Xingtao/姚 幸涛 <yaoxt.fnst@fujitsu.com>
> > > Subject: [PATCH v3] mem/cxl_type3: support 3, 6, 12 and 16 interleave ways
> > >
> > > Since the kernel does not check the interleave capability, a
> > > 3-way, 6-way, 12-way or 16-way region can be create normally.
> > >
> > > Applications can access the memory of 16-way region normally because
> > > qemu can convert hpa to dpa correctly for the power of 2 interleave
> > > ways, after kernel implementing the check, this kind of region will
> > > not be created any more.
> > >
> > > For non power of 2 interleave ways, applications could not access the
> > > memory normally and may occur some unexpected behaviors, such as
> > > segmentation fault.
> > >
> > > So implements this feature is needed.
> > >
> > > Link:
> > >
> > https://lore.kernel.org/linux-cxl/3e84b919-7631-d1db-3e1d-33000f3f3868@fujits
> > > u.com/
> > > Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
> > > ---
> > > hw/cxl/cxl-component-utils.c | 9 +++++++--
> > > hw/mem/cxl_type3.c | 15 +++++++++++----
> > > 2 files changed, 18 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
> > > index cd116c0401..473895948b 100644
> > > --- a/hw/cxl/cxl-component-utils.c
> > > +++ b/hw/cxl/cxl-component-utils.c
> > > @@ -243,8 +243,13 @@ static void hdm_init_common(uint32_t *reg_state,
> > > uint32_t *write_msk,
> > > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > > INTERLEAVE_4K, 1);
> > > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > > POISON_ON_ERR_CAP, 0);
> > > - ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > > 3_6_12_WAY, 0);
> > > - ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > 16_WAY,
> > > 0);
> > > + if (type == CXL2_TYPE3_DEVICE) {
> > > + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > > 3_6_12_WAY, 1);
> > > + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > > 16_WAY, 1);
> > > + } else {
> > > + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > > 3_6_12_WAY, 0);
> > > + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > > 16_WAY, 0);
> > > + }
> > > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, UIO,
> > 0);
> > > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > > UIO_DECODER_COUNT, 0);
> > > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> > > index 3e42490b6c..b755318838 100644
> > > --- a/hw/mem/cxl_type3.c
> > > +++ b/hw/mem/cxl_type3.c
> > > @@ -804,10 +804,17 @@ static bool cxl_type3_dpa(CXLType3Dev *ct3d, hwaddr
> > > host_addr, uint64_t *dpa)
> > > continue;
> > > }
> > >
> > > - *dpa = dpa_base +
> > > - ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) |
> > > - ((MAKE_64BIT_MASK(8 + ig + iw, 64 - 8 - ig - iw) & hpa_offset)
> > > - >> iw));
> > > + if (iw < 8) {
> > > + *dpa = dpa_base +
> > > + ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) |
> > > + ((MAKE_64BIT_MASK(8 + ig + iw, 64 - 8 - ig - iw) &
> > hpa_offset)
> > > + >> iw));
> > > + } else {
> > > + *dpa = dpa_base +
> > > + ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) |
> > > + ((((MAKE_64BIT_MASK(ig + iw, 64 - ig - iw) & hpa_offset)
> > > + >> (ig + iw)) / 3) << (ig + 8)));
> > > + }
> > >
> > > return true;
> > > }
> > > --
> > > 2.37.3
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH v3] mem/cxl_type3: support 3, 6, 12 and 16 interleave ways
2024-06-21 15:01 ` Jonathan Cameron via
@ 2024-06-24 0:03 ` Xingtao Yao (Fujitsu) via
0 siblings, 0 replies; 5+ messages in thread
From: Xingtao Yao (Fujitsu) via @ 2024-06-24 0:03 UTC (permalink / raw)
To: Jonathan Cameron; +Cc: fan.ni@samsung.com, qemu-devel@nongnu.org
> -----Original Message-----
> From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
> Sent: Friday, June 21, 2024 11:02 PM
> To: Yao, Xingtao/姚 幸涛 <yaoxt.fnst@fujitsu.com>
> Cc: fan.ni@samsung.com; qemu-devel@nongnu.org
> Subject: Re: [PATCH v3] mem/cxl_type3: support 3, 6, 12 and 16 interleave ways
>
> On Thu, 6 Jun 2024 08:07:27 +0000
> "Xingtao Yao (Fujitsu)" <yaoxt.fnst@fujitsu.com> wrote:
>
> > ping again.
>
> Sorry for delay - I was waiting for some of the tree I'm carrying
> to get picked up before applying anything new.
>
> I haven't yet tested this as fully as I'd like for upstreaming, but
> with that in mind applied to my cxl staging tree.
many thanks, I can do some test if you need.
>
> Thanks,
>
> Jonathan
>
> >
> > > -----Original Message-----
> > > From: Yao, Xingtao/姚 幸涛 <yaoxt.fnst@fujitsu.com>
> > > Sent: Friday, May 24, 2024 5:31 PM
> > > To: Yao, Xingtao/姚 幸涛 <yaoxt.fnst@fujitsu.com>;
> > > jonathan.cameron@huawei.com; fan.ni@samsung.com
> > > Cc: qemu-devel@nongnu.org
> > > Subject: RE: [PATCH v3] mem/cxl_type3: support 3, 6, 12 and 16 interleave
> ways
> > >
> > > ping.
> > >
> > > > -----Original Message-----
> > > > From: Yao Xingtao <yaoxt.fnst@fujitsu.com>
> > > > Sent: Wednesday, May 8, 2024 8:53 AM
> > > > To: jonathan.cameron@huawei.com; fan.ni@samsung.com
> > > > Cc: qemu-devel@nongnu.org; Yao, Xingtao/姚 幸涛
> <yaoxt.fnst@fujitsu.com>
> > > > Subject: [PATCH v3] mem/cxl_type3: support 3, 6, 12 and 16 interleave ways
> > > >
> > > > Since the kernel does not check the interleave capability, a
> > > > 3-way, 6-way, 12-way or 16-way region can be create normally.
> > > >
> > > > Applications can access the memory of 16-way region normally because
> > > > qemu can convert hpa to dpa correctly for the power of 2 interleave
> > > > ways, after kernel implementing the check, this kind of region will
> > > > not be created any more.
> > > >
> > > > For non power of 2 interleave ways, applications could not access the
> > > > memory normally and may occur some unexpected behaviors, such as
> > > > segmentation fault.
> > > >
> > > > So implements this feature is needed.
> > > >
> > > > Link:
> > > >
> > >
> https://lore.kernel.org/linux-cxl/3e84b919-7631-d1db-3e1d-33000f3f3868@fujits
> > > > u.com/
> > > > Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
> > > > ---
> > > > hw/cxl/cxl-component-utils.c | 9 +++++++--
> > > > hw/mem/cxl_type3.c | 15 +++++++++++----
> > > > 2 files changed, 18 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
> > > > index cd116c0401..473895948b 100644
> > > > --- a/hw/cxl/cxl-component-utils.c
> > > > +++ b/hw/cxl/cxl-component-utils.c
> > > > @@ -243,8 +243,13 @@ static void hdm_init_common(uint32_t *reg_state,
> > > > uint32_t *write_msk,
> > > > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > > > INTERLEAVE_4K, 1);
> > > > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > > > POISON_ON_ERR_CAP, 0);
> > > > - ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > > > 3_6_12_WAY, 0);
> > > > - ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > > 16_WAY,
> > > > 0);
> > > > + if (type == CXL2_TYPE3_DEVICE) {
> > > > + ARRAY_FIELD_DP32(reg_state,
> CXL_HDM_DECODER_CAPABILITY,
> > > > 3_6_12_WAY, 1);
> > > > + ARRAY_FIELD_DP32(reg_state,
> CXL_HDM_DECODER_CAPABILITY,
> > > > 16_WAY, 1);
> > > > + } else {
> > > > + ARRAY_FIELD_DP32(reg_state,
> CXL_HDM_DECODER_CAPABILITY,
> > > > 3_6_12_WAY, 0);
> > > > + ARRAY_FIELD_DP32(reg_state,
> CXL_HDM_DECODER_CAPABILITY,
> > > > 16_WAY, 0);
> > > > + }
> > > > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> UIO,
> > > 0);
> > > > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > > > UIO_DECODER_COUNT, 0);
> > > > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> > > > index 3e42490b6c..b755318838 100644
> > > > --- a/hw/mem/cxl_type3.c
> > > > +++ b/hw/mem/cxl_type3.c
> > > > @@ -804,10 +804,17 @@ static bool cxl_type3_dpa(CXLType3Dev *ct3d,
> hwaddr
> > > > host_addr, uint64_t *dpa)
> > > > continue;
> > > > }
> > > >
> > > > - *dpa = dpa_base +
> > > > - ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) |
> > > > - ((MAKE_64BIT_MASK(8 + ig + iw, 64 - 8 - ig - iw) &
> hpa_offset)
> > > > - >> iw));
> > > > + if (iw < 8) {
> > > > + *dpa = dpa_base +
> > > > + ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) |
> > > > + ((MAKE_64BIT_MASK(8 + ig + iw, 64 - 8 - ig - iw) &
> > > hpa_offset)
> > > > + >> iw));
> > > > + } else {
> > > > + *dpa = dpa_base +
> > > > + ((MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) |
> > > > + ((((MAKE_64BIT_MASK(ig + iw, 64 - ig - iw) &
> hpa_offset)
> > > > + >> (ig + iw)) / 3) << (ig + 8)));
> > > > + }
> > > >
> > > > return true;
> > > > }
> > > > --
> > > > 2.37.3
> >
> >
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2024-06-24 0:04 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-05-08 0:53 [PATCH v3] mem/cxl_type3: support 3, 6, 12 and 16 interleave ways Yao Xingtao via
2024-05-24 9:31 ` Xingtao Yao (Fujitsu) via
2024-06-06 8:07 ` Xingtao Yao (Fujitsu) via
2024-06-21 15:01 ` Jonathan Cameron via
2024-06-24 0:03 ` Xingtao Yao (Fujitsu) via
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