All of lore.kernel.org
 help / color / mirror / Atom feed
From: Conor Dooley <conor@kernel.org>
To: daire.mcnamara@microchip.com
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	conor.dooley@microchip.com, lpieralisi@kernel.org, kw@linux.com,
	robh@kernel.org, bhelgaas@google.com,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	krzk+dt@kernel.org, conor+dt@kernel.org,
	ilpo.jarvinen@linux.intel.com
Subject: Re: [PATCH v5 1/3] PCI: microchip: Fix outbound address translation tables
Date: Tue, 25 Jun 2024 17:26:12 +0100	[thread overview]
Message-ID: <20240625-length-user-c6c36e36bbeb@spud> (raw)
In-Reply-To: <20240625123845.3747764-2-daire.mcnamara@microchip.com>

[-- Attachment #1: Type: text/plain, Size: 1120 bytes --]

On Tue, Jun 25, 2024 at 01:38:43PM +0100, daire.mcnamara@microchip.com wrote:
> From: Daire McNamara <daire.mcnamara@microchip.com>
> 
> On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of
> three general-purpose Fabric Interface Controller (FIC) buses that
> encapsulate an AXI-M interface. That FIC is responsible for managing
> the translations of the upper 32-bits of the AXI-M address. On MPFS,
> the Root Port driver needs to take account of that outbound address
> translation done by the parent FIC bus before setting up its own
> outbound address translation tables.  In all cases on MPFS,
> the remaining outbound address translation tables are 32-bit only.
> 
> Limit the outbound address translation tables to 32-bit only.
> 
> This necessitates changing a size_t in mc_pcie_setup_window
> to a resource_size_t to avoid a compile error on 32-bit platforms.
> 
> Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver")
> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: daire.mcnamara@microchip.com
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	conor.dooley@microchip.com, lpieralisi@kernel.org, kw@linux.com,
	robh@kernel.org, bhelgaas@google.com,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	krzk+dt@kernel.org, conor+dt@kernel.org,
	ilpo.jarvinen@linux.intel.com
Subject: Re: [PATCH v5 1/3] PCI: microchip: Fix outbound address translation tables
Date: Tue, 25 Jun 2024 17:26:12 +0100	[thread overview]
Message-ID: <20240625-length-user-c6c36e36bbeb@spud> (raw)
In-Reply-To: <20240625123845.3747764-2-daire.mcnamara@microchip.com>


[-- Attachment #1.1: Type: text/plain, Size: 1120 bytes --]

On Tue, Jun 25, 2024 at 01:38:43PM +0100, daire.mcnamara@microchip.com wrote:
> From: Daire McNamara <daire.mcnamara@microchip.com>
> 
> On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of
> three general-purpose Fabric Interface Controller (FIC) buses that
> encapsulate an AXI-M interface. That FIC is responsible for managing
> the translations of the upper 32-bits of the AXI-M address. On MPFS,
> the Root Port driver needs to take account of that outbound address
> translation done by the parent FIC bus before setting up its own
> outbound address translation tables.  In all cases on MPFS,
> the remaining outbound address translation tables are 32-bit only.
> 
> Limit the outbound address translation tables to 32-bit only.
> 
> This necessitates changing a size_t in mc_pcie_setup_window
> to a resource_size_t to avoid a compile error on 32-bit platforms.
> 
> Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver")
> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2024-06-25 16:26 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-25 12:38 [PATCH v5 0/3] Fix address translations on MPFS PCIe controller daire.mcnamara
2024-06-25 12:38 ` daire.mcnamara
2024-06-25 12:38 ` [PATCH v5 1/3] PCI: microchip: Fix outbound address translation tables daire.mcnamara
2024-06-25 12:38   ` daire.mcnamara
2024-06-25 16:26   ` Conor Dooley [this message]
2024-06-25 16:26     ` Conor Dooley
2024-06-25 12:38 ` [PATCH v5 2/3] PCI: microchip: Fix inbound " daire.mcnamara
2024-06-25 12:38   ` daire.mcnamara
2024-06-25 16:26   ` Conor Dooley
2024-06-25 16:26     ` Conor Dooley
2024-06-25 12:38 ` [PATCH v5 3/3] dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent daire.mcnamara
2024-06-25 12:38   ` daire.mcnamara

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240625-length-user-c6c36e36bbeb@spud \
    --to=conor@kernel.org \
    --cc=bhelgaas@google.com \
    --cc=conor+dt@kernel.org \
    --cc=conor.dooley@microchip.com \
    --cc=daire.mcnamara@microchip.com \
    --cc=devicetree@vger.kernel.org \
    --cc=ilpo.jarvinen@linux.intel.com \
    --cc=krzk+dt@kernel.org \
    --cc=kw@linux.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=lpieralisi@kernel.org \
    --cc=robh@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.