From: Simon Horman <horms@kernel.org>
To: Karol Kolacinski <karol.kolacinski@intel.com>
Cc: netdev@vger.kernel.org,
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
anthony.l.nguyen@intel.com, Yochai Hagvi <yochai.hagvi@intel.com>,
przemyslaw.kitszel@intel.com, intel-wired-lan@lists.osuosl.org
Subject: Re: [Intel-wired-lan] [PATCH v2 iwl-next 6/7] ice: Read SDP section from NVM for pin definitions
Date: Wed, 3 Jul 2024 19:21:01 +0100 [thread overview]
Message-ID: <20240703182101.GO598357@kernel.org> (raw)
In-Reply-To: <20240702134448.132374-15-karol.kolacinski@intel.com>
On Tue, Jul 02, 2024 at 03:41:35PM +0200, Karol Kolacinski wrote:
> From: Yochai Hagvi <yochai.hagvi@intel.com>
>
> PTP pins assignment and their related SDPs (Software Definable Pins) are
> currently hardcoded.
> Fix that by reading NVM section instead on products supporting this,
> which are E810 products.
> If SDP section is not defined in NVM, the driver continues to use the
> hardcoded table.
>
> Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
> Signed-off-by: Yochai Hagvi <yochai.hagvi@intel.com>
> Co-developed-by: Karol Kolacinski <karol.kolacinski@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Reviewed-by: Simon Horman <horms@kernel.org>
WARNING: multiple messages have this Message-ID (diff)
From: Simon Horman <horms@kernel.org>
To: Karol Kolacinski <karol.kolacinski@intel.com>
Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org,
anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com,
Yochai Hagvi <yochai.hagvi@intel.com>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Subject: Re: [PATCH v2 iwl-next 6/7] ice: Read SDP section from NVM for pin definitions
Date: Wed, 3 Jul 2024 19:21:01 +0100 [thread overview]
Message-ID: <20240703182101.GO598357@kernel.org> (raw)
In-Reply-To: <20240702134448.132374-15-karol.kolacinski@intel.com>
On Tue, Jul 02, 2024 at 03:41:35PM +0200, Karol Kolacinski wrote:
> From: Yochai Hagvi <yochai.hagvi@intel.com>
>
> PTP pins assignment and their related SDPs (Software Definable Pins) are
> currently hardcoded.
> Fix that by reading NVM section instead on products supporting this,
> which are E810 products.
> If SDP section is not defined in NVM, the driver continues to use the
> hardcoded table.
>
> Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
> Signed-off-by: Yochai Hagvi <yochai.hagvi@intel.com>
> Co-developed-by: Karol Kolacinski <karol.kolacinski@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Reviewed-by: Simon Horman <horms@kernel.org>
next prev parent reply other threads:[~2024-07-03 18:21 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-02 13:41 [Intel-wired-lan] [PATCH v2 iwl-next 0/7] ice: Cleanup and refactor PTP pin handling Karol Kolacinski
2024-07-02 13:41 ` Karol Kolacinski
2024-07-02 13:41 ` [Intel-wired-lan] [PATCH v2 iwl-next 1/7] ice: Implement ice_ptp_pin_desc Karol Kolacinski
2024-07-02 13:41 ` Karol Kolacinski
2024-07-03 18:19 ` [Intel-wired-lan] " Simon Horman
2024-07-03 18:19 ` Simon Horman
2024-08-19 3:58 ` [Intel-wired-lan] " Pucha, HimasekharX Reddy
2024-08-19 3:58 ` Pucha, HimasekharX Reddy
2024-07-02 13:41 ` [Intel-wired-lan] [PATCH v2 iwl-next 2/7] ice: Add SDPs support for E825C Karol Kolacinski
2024-07-02 13:41 ` Karol Kolacinski
2024-07-03 18:20 ` [Intel-wired-lan] " Simon Horman
2024-07-03 18:20 ` Simon Horman
2024-08-19 3:58 ` [Intel-wired-lan] " Pucha, HimasekharX Reddy
2024-08-19 3:58 ` Pucha, HimasekharX Reddy
2024-07-02 13:41 ` [Intel-wired-lan] [PATCH v2 iwl-next 3/7] ice: Align E810T GPIO to other products Karol Kolacinski
2024-07-02 13:41 ` Karol Kolacinski
2024-07-03 18:19 ` [Intel-wired-lan] " Simon Horman
2024-07-03 18:19 ` Simon Horman
2024-08-19 3:58 ` [Intel-wired-lan] " Pucha, HimasekharX Reddy
2024-08-19 3:58 ` Pucha, HimasekharX Reddy
2024-07-02 13:41 ` [Intel-wired-lan] [PATCH v2 iwl-next 4/7] ice: Cache perout/extts requests and check flags Karol Kolacinski
2024-07-02 13:41 ` Karol Kolacinski
2024-07-03 18:20 ` [Intel-wired-lan] " Simon Horman
2024-07-03 18:20 ` Simon Horman
2024-08-19 3:58 ` [Intel-wired-lan] " Pucha, HimasekharX Reddy
2024-08-19 3:58 ` Pucha, HimasekharX Reddy
2024-07-02 13:41 ` [Intel-wired-lan] [PATCH v2 iwl-next 5/7] ice: Disable shared pin on E810 on setfunc Karol Kolacinski
2024-07-02 13:41 ` Karol Kolacinski
2024-07-03 18:20 ` [Intel-wired-lan] " Simon Horman
2024-07-03 18:20 ` Simon Horman
2024-08-19 3:58 ` [Intel-wired-lan] " Pucha, HimasekharX Reddy
2024-08-19 3:58 ` Pucha, HimasekharX Reddy
2024-07-02 13:41 ` [Intel-wired-lan] [PATCH v2 iwl-next 6/7] ice: Read SDP section from NVM for pin definitions Karol Kolacinski
2024-07-02 13:41 ` Karol Kolacinski
2024-07-03 18:21 ` Simon Horman [this message]
2024-07-03 18:21 ` Simon Horman
2024-08-19 3:58 ` [Intel-wired-lan] " Pucha, HimasekharX Reddy
2024-08-19 3:58 ` Pucha, HimasekharX Reddy
2024-07-02 13:41 ` [Intel-wired-lan] [PATCH v2 iwl-next 7/7] ice: Enable 1PPS out from CGU for E825C products Karol Kolacinski
2024-07-02 13:41 ` Karol Kolacinski
2024-07-03 18:21 ` [Intel-wired-lan] " Simon Horman
2024-07-03 18:21 ` Simon Horman
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240703182101.GO598357@kernel.org \
--to=horms@kernel.org \
--cc=anthony.l.nguyen@intel.com \
--cc=arkadiusz.kubalewski@intel.com \
--cc=intel-wired-lan@lists.osuosl.org \
--cc=karol.kolacinski@intel.com \
--cc=netdev@vger.kernel.org \
--cc=przemyslaw.kitszel@intel.com \
--cc=yochai.hagvi@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.