From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2] riscv: define ILLEGAL_POINTER_VALUE for 64bit
Date: Sat, 6 Jul 2024 01:02:10 +0800 [thread overview]
Message-ID: <20240705170210.3236-1-jszhang@kernel.org> (raw)
This is used in poison.h for poison pointer offset. Based on current
SV39, SV48 and SV57 vm layout, 0xdead000000000000 is a proper value
that is not mappable, this can avoid potentially turning an oops to
an expolit.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
Since v1:
- fix typo:s/SV59/SV57
arch/riscv/Kconfig | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index c51b32a8ddff..c992eabbd002 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -313,6 +313,11 @@ config GENERIC_HWEIGHT
config FIX_EARLYCON_MEM
def_bool MMU
+config ILLEGAL_POINTER_VALUE
+ hex
+ default 0 if 32BIT
+ default 0xdead000000000000 if 64BIT
+
config PGTABLE_LEVELS
int
default 5 if 64BIT
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2] riscv: define ILLEGAL_POINTER_VALUE for 64bit
Date: Sat, 6 Jul 2024 01:02:10 +0800 [thread overview]
Message-ID: <20240705170210.3236-1-jszhang@kernel.org> (raw)
This is used in poison.h for poison pointer offset. Based on current
SV39, SV48 and SV57 vm layout, 0xdead000000000000 is a proper value
that is not mappable, this can avoid potentially turning an oops to
an expolit.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
Since v1:
- fix typo:s/SV59/SV57
arch/riscv/Kconfig | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index c51b32a8ddff..c992eabbd002 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -313,6 +313,11 @@ config GENERIC_HWEIGHT
config FIX_EARLYCON_MEM
def_bool MMU
+config ILLEGAL_POINTER_VALUE
+ hex
+ default 0 if 32BIT
+ default 0xdead000000000000 if 64BIT
+
config PGTABLE_LEVELS
int
default 5 if 64BIT
--
2.43.0
next reply other threads:[~2024-07-05 17:16 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-05 17:02 Jisheng Zhang [this message]
2024-07-05 17:02 ` [PATCH v2] riscv: define ILLEGAL_POINTER_VALUE for 64bit Jisheng Zhang
2024-07-06 0:50 ` Jisheng Zhang
2024-07-06 0:50 ` Jisheng Zhang
2024-09-15 6:55 ` Palmer Dabbelt
2024-09-15 6:55 ` Palmer Dabbelt
2024-09-17 13:00 ` patchwork-bot+linux-riscv
2024-09-17 13:00 ` patchwork-bot+linux-riscv
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240705170210.3236-1-jszhang@kernel.org \
--to=jszhang@kernel.org \
--cc=aou@eecs.berkeley.edu \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.