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From: Sunil V L <sunilvl@ventanamicro.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
	"Michael S . Tsirkin" <mst@redhat.com>,
	Igor Mammedov <imammedo@redhat.com>,
	Ani Sinha <anisinha@redhat.com>,
	Sunil V L <sunilvl@ventanamicro.com>
Subject: [PATCH v2 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
Date: Mon,  8 Jul 2024 17:17:33 +0530	[thread overview]
Message-ID: <20240708114741.3499585-2-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20240708114741.3499585-1-sunilvl@ventanamicro.com>

PLIC and APLIC should be in namespace as well. So, add them using the
defined HID.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt-acpi-build.c | 47 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 0925528160..87fe882af0 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -141,6 +141,52 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
     }
 }
 
+static void acpi_dsdt_add_plic_aplic(Aml *scope, RISCVVirtState *s)
+{
+    MachineState *ms = MACHINE(s);
+    uint64_t plic_aplic_addr;
+    uint32_t gsi_base;
+    uint8_t  socket;
+
+    if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+        /* PLICs */
+        for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+            plic_aplic_addr = s->memmap[VIRT_PLIC].base +
+                         s->memmap[VIRT_PLIC].size * socket;
+            gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+            Aml *dev = aml_device("IC%.02X", socket);
+            aml_append(dev, aml_name_decl("_HID", aml_string("RSCV0001")));
+            aml_append(dev, aml_name_decl("_UID", aml_int(socket)));
+            aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base)));
+
+            Aml *crs = aml_resource_template();
+            aml_append(crs, aml_memory32_fixed(plic_aplic_addr,
+                                               s->memmap[VIRT_PLIC].size,
+                                               AML_READ_WRITE));
+            aml_append(dev, aml_name_decl("_CRS", crs));
+            aml_append(scope, dev);
+        }
+    } else {
+        /* APLICs */
+        for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+            plic_aplic_addr = s->memmap[VIRT_APLIC_S].base +
+                             s->memmap[VIRT_APLIC_S].size * socket;
+            gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+            Aml *dev = aml_device("IC%.02X", socket);
+            aml_append(dev, aml_name_decl("_HID", aml_string("RSCV0002")));
+            aml_append(dev, aml_name_decl("_UID", aml_int(socket)));
+            aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base)));
+
+            Aml *crs = aml_resource_template();
+            aml_append(crs, aml_memory32_fixed(plic_aplic_addr,
+                                               s->memmap[VIRT_APLIC_S].size,
+                                               AML_READ_WRITE));
+            aml_append(dev, aml_name_decl("_CRS", crs));
+            aml_append(scope, dev);
+        }
+    }
+}
+
 static void
 acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
                     uint32_t uart_irq)
@@ -411,6 +457,7 @@ static void build_dsdt(GArray *table_data,
 
     socket_count = riscv_socket_count(ms);
 
+    acpi_dsdt_add_plic_aplic(scope, s);
     acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ);
 
     if (socket_count == 1) {
-- 
2.43.0



  reply	other threads:[~2024-07-08 11:48 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-08 11:47 [PATCH v2 0/9] RISC-V: ACPI: Namespace updates Sunil V L
2024-07-08 11:47 ` Sunil V L [this message]
2024-07-11 13:17   ` [PATCH v2 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC Igor Mammedov
2024-07-11 13:21   ` Igor Mammedov
2024-07-08 11:47 ` [PATCH v2 2/9] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART Sunil V L
2024-07-11 13:25   ` Igor Mammedov
2024-07-11 14:41     ` Michael S. Tsirkin
2024-07-12  5:07       ` Sunil V L
2024-07-08 11:47 ` [PATCH v2 3/9] tests/acpi: Allow DSDT acpi table changes for aarch64 Sunil V L
2024-07-11 13:53   ` Igor Mammedov
2024-07-08 11:47 ` [PATCH v2 4/9] acpi/gpex: Create PCI link devices outside PCI root bridge Sunil V L
2024-07-11 13:43   ` Igor Mammedov
2024-07-08 11:47 ` [PATCH v2 5/9] tests/acpi: update expected DSDT blob for aarch64 and microvm Sunil V L
2024-07-08 11:47 ` [PATCH v2 6/9] tests/qtest/bios-tables-test.c: Remove the fall back path Sunil V L
2024-07-10  0:54   ` Alistair Francis
2024-07-11 13:53   ` Igor Mammedov
2024-07-08 11:47 ` [PATCH v2 7/9] tests/acpi: Add empty ACPI data files for RISC-V Sunil V L
2024-07-08 11:47 ` [PATCH v2 8/9] tests/qtest/bios-tables-test.c: Enable basic testing " Sunil V L
2024-07-08 11:47 ` [PATCH v2 9/9] tests/acpi: Add expected ACPI AML files " Sunil V L
2024-07-12 12:43 ` [PATCH v2 0/9] RISC-V: ACPI: Namespace updates Igor Mammedov
2024-07-12 12:51   ` Daniel P. Berrangé
2024-07-12 13:50     ` Igor Mammedov
2024-07-14  7:46       ` Michael S. Tsirkin
2024-07-15 12:43         ` Igor Mammedov
2024-07-16 12:26           ` Sunil V L
2024-07-16 14:28             ` Igor Mammedov
2024-07-16 14:33               ` Igor Mammedov

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