* [PATCH 0/3] Add fixups for two-plane serial NAND flash
@ 2024-07-10 1:15 ` Cheng Ming Lin
0 siblings, 0 replies; 12+ messages in thread
From: Cheng Ming Lin @ 2024-07-10 1:15 UTC (permalink / raw)
To: miquel.raynal, vigneshr, linux-mtd, linux-kernel
Cc: richard, alvinzhou, leoyu, Cheng Ming Lin
From: Cheng Ming Lin <chengminglin@mxic.com.tw>
Macronix serial NAND flash with a two-plane structure
requires insertion of Plane Select bit into the column
address during the write_to_cache operation.
Additionally, for MX35{U,F}2G14AC, insertion of Plane
Select bit into the column address is required during
the read_from_cache operation.
In spinand.h, add struct spi_nand_fixups as SPI NAND
fixup hooks.
In macronix.c, add fixup functions and update ID table.
In core.c, add an if statement to determine whether to
insert the Plane Select bit for the column address.
These flashes have been validated on Xilinx zynq-picozed
board which included Macronix SPI Host.
Cheng Ming Lin (3):
include/linux/mtd/spinand.h: Add fixups for spinand
mtd: spinand: macronix: Fixups for PLANE_SELECT_BIT
mtd: spinand: Insert Plane Select bit for the column address
drivers/mtd/nand/spi/core.c | 7 +++++
drivers/mtd/nand/spi/macronix.c | 51 +++++++++++++++++++++++++++++----
include/linux/mtd/spinand.h | 17 +++++++++++
3 files changed, 69 insertions(+), 6 deletions(-)
--
2.25.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 0/3] Add fixups for two-plane serial NAND flash @ 2024-07-10 1:15 ` Cheng Ming Lin 0 siblings, 0 replies; 12+ messages in thread From: Cheng Ming Lin @ 2024-07-10 1:15 UTC (permalink / raw) To: miquel.raynal, vigneshr, linux-mtd, linux-kernel Cc: richard, alvinzhou, leoyu, Cheng Ming Lin From: Cheng Ming Lin <chengminglin@mxic.com.tw> Macronix serial NAND flash with a two-plane structure requires insertion of Plane Select bit into the column address during the write_to_cache operation. Additionally, for MX35{U,F}2G14AC, insertion of Plane Select bit into the column address is required during the read_from_cache operation. In spinand.h, add struct spi_nand_fixups as SPI NAND fixup hooks. In macronix.c, add fixup functions and update ID table. In core.c, add an if statement to determine whether to insert the Plane Select bit for the column address. These flashes have been validated on Xilinx zynq-picozed board which included Macronix SPI Host. Cheng Ming Lin (3): include/linux/mtd/spinand.h: Add fixups for spinand mtd: spinand: macronix: Fixups for PLANE_SELECT_BIT mtd: spinand: Insert Plane Select bit for the column address drivers/mtd/nand/spi/core.c | 7 +++++ drivers/mtd/nand/spi/macronix.c | 51 +++++++++++++++++++++++++++++---- include/linux/mtd/spinand.h | 17 +++++++++++ 3 files changed, 69 insertions(+), 6 deletions(-) -- 2.25.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/3] include/linux/mtd/spinand.h: Add fixups for spinand 2024-07-10 1:15 ` Cheng Ming Lin @ 2024-07-10 1:15 ` Cheng Ming Lin -1 siblings, 0 replies; 12+ messages in thread From: Cheng Ming Lin @ 2024-07-10 1:15 UTC (permalink / raw) To: miquel.raynal, vigneshr, linux-mtd, linux-kernel Cc: richard, alvinzhou, leoyu, Cheng Ming Lin From: Cheng Ming Lin <chengminglin@mxic.com.tw> Add struct spi_nand_fixups as SPI NAND fixup hooks. To determine whether the Plane Select bit should be inserted into the column address in core.c, add the member struct spinand_info to struct spinand_device to ascertain whether the device has fixups. Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw> --- include/linux/mtd/spinand.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 5c19ead60499..c079c6ac1541 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -354,6 +354,7 @@ struct spinand_info { } op_variants; int (*select_target)(struct spinand_device *spinand, unsigned int target); + const struct spi_nand_fixups *fixups; }; #define SPINAND_ID(__method, ...) \ @@ -379,6 +380,9 @@ struct spinand_info { #define SPINAND_SELECT_TARGET(__func) \ .select_target = __func, +#define SPINAND_PLANE_SELECT_BIT(__func) \ + .fixups = __func, + #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \ __flags, ...) \ { \ @@ -398,6 +402,18 @@ struct spinand_dirmap { struct spi_mem_dirmap_desc *rdesc_ecc; }; +/** + * struct spi_nand_fixups - SPI NAND fixup hooks + * @write_to_cache: program load requires Plane Select bit in CADD. + * @read_from_cache: read from cache requires Plane Select bit in CADD. + */ +struct spi_nand_fixups { + unsigned int (*write_to_cache)(struct spinand_device *spinand, + const struct nand_page_io_req *req, unsigned int column); + u16 (*read_from_cache)(struct spinand_device *spinand, + const struct nand_page_io_req *req, u16 column); +}; + /** * struct spinand_device - SPI NAND device instance * @base: NAND device instance @@ -449,6 +465,7 @@ struct spinand_device { u8 *databuf; u8 *oobbuf; u8 *scratchbuf; + const struct spinand_info *info; const struct spinand_manufacturer *manufacturer; void *priv; }; -- 2.25.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 1/3] include/linux/mtd/spinand.h: Add fixups for spinand @ 2024-07-10 1:15 ` Cheng Ming Lin 0 siblings, 0 replies; 12+ messages in thread From: Cheng Ming Lin @ 2024-07-10 1:15 UTC (permalink / raw) To: miquel.raynal, vigneshr, linux-mtd, linux-kernel Cc: richard, alvinzhou, leoyu, Cheng Ming Lin From: Cheng Ming Lin <chengminglin@mxic.com.tw> Add struct spi_nand_fixups as SPI NAND fixup hooks. To determine whether the Plane Select bit should be inserted into the column address in core.c, add the member struct spinand_info to struct spinand_device to ascertain whether the device has fixups. Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw> --- include/linux/mtd/spinand.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 5c19ead60499..c079c6ac1541 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -354,6 +354,7 @@ struct spinand_info { } op_variants; int (*select_target)(struct spinand_device *spinand, unsigned int target); + const struct spi_nand_fixups *fixups; }; #define SPINAND_ID(__method, ...) \ @@ -379,6 +380,9 @@ struct spinand_info { #define SPINAND_SELECT_TARGET(__func) \ .select_target = __func, +#define SPINAND_PLANE_SELECT_BIT(__func) \ + .fixups = __func, + #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \ __flags, ...) \ { \ @@ -398,6 +402,18 @@ struct spinand_dirmap { struct spi_mem_dirmap_desc *rdesc_ecc; }; +/** + * struct spi_nand_fixups - SPI NAND fixup hooks + * @write_to_cache: program load requires Plane Select bit in CADD. + * @read_from_cache: read from cache requires Plane Select bit in CADD. + */ +struct spi_nand_fixups { + unsigned int (*write_to_cache)(struct spinand_device *spinand, + const struct nand_page_io_req *req, unsigned int column); + u16 (*read_from_cache)(struct spinand_device *spinand, + const struct nand_page_io_req *req, u16 column); +}; + /** * struct spinand_device - SPI NAND device instance * @base: NAND device instance @@ -449,6 +465,7 @@ struct spinand_device { u8 *databuf; u8 *oobbuf; u8 *scratchbuf; + const struct spinand_info *info; const struct spinand_manufacturer *manufacturer; void *priv; }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/3] mtd: spinand: macronix: Fixups for PLANE_SELECT_BIT 2024-07-10 1:15 ` Cheng Ming Lin @ 2024-07-10 1:15 ` Cheng Ming Lin -1 siblings, 0 replies; 12+ messages in thread From: Cheng Ming Lin @ 2024-07-10 1:15 UTC (permalink / raw) To: miquel.raynal, vigneshr, linux-mtd, linux-kernel Cc: richard, alvinzhou, leoyu, Cheng Ming Lin From: Cheng Ming Lin <chengminglin@mxic.com.tw> Macronix serial NAND flash with a two-plane structure requires insertion of Plane Select bit into the column address during the write_to_cache operation. Additionally, for MX35{U,F}2G14AC, insertion of Plane Select bit into the column address is required during the read_from_cache operation. Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw> --- drivers/mtd/nand/spi/macronix.c | 51 +++++++++++++++++++++++++++++---- 1 file changed, 45 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c index 3f9e9c572854..c61f1ba31f0c 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -100,6 +100,39 @@ static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand, return -EINVAL; } +/** + * Macronix serial NAND flash with a two-plane structure + * should insert Plane Select bit into the column address + * during the write_to_cache operation. + * Additionally, MX35{U,F}2G14AC also need to insert Plane + * Select bit into the column address during the read_from_cache + * operation. + */ +static unsigned int write_Plane_Select_bit_in_cadd(struct spinand_device *spinand, + const struct nand_page_io_req *req, unsigned int column) +{ + struct nand_device *nand = spinand_to_nand(spinand); + + return column | (req->pos.plane << fls(nanddev_page_size(nand))); +} + +static u16 read_Plane_Select_bit_in_cadd(struct spinand_device *spinand, + const struct nand_page_io_req *req, u16 column) +{ + struct nand_device *nand = spinand_to_nand(spinand); + + return column | (req->pos.plane << fls(nanddev_page_size(nand))); +} + +static const struct spi_nand_fixups write_fixups = { + .write_to_cache = write_Plane_Select_bit_in_cadd, +}; + +static const struct spi_nand_fixups read_and_write_fixups = { + .write_to_cache = write_Plane_Select_bit_in_cadd, + .read_from_cache = read_Plane_Select_bit_in_cadd, +}; + static const struct spinand_info macronix_spinand_table[] = { SPINAND_INFO("MX35LF1GE4AB", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12), @@ -157,7 +190,8 @@ static const struct spinand_info macronix_spinand_table[] = { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35LF2G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x64, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), @@ -175,7 +209,8 @@ static const struct spinand_info macronix_spinand_table[] = { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35LF4G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x75, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), @@ -215,7 +250,8 @@ static const struct spinand_info macronix_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&read_and_write_fixups)), SPINAND_INFO("MX35UF4G24AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1), @@ -225,7 +261,8 @@ static const struct spinand_info macronix_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35UF4G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xf5, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), @@ -255,7 +292,8 @@ static const struct spinand_info macronix_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&read_and_write_fixups)), SPINAND_INFO("MX35UF2G24AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), @@ -265,7 +303,8 @@ static const struct spinand_info macronix_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35UF2G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe4, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), -- 2.25.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/3] mtd: spinand: macronix: Fixups for PLANE_SELECT_BIT @ 2024-07-10 1:15 ` Cheng Ming Lin 0 siblings, 0 replies; 12+ messages in thread From: Cheng Ming Lin @ 2024-07-10 1:15 UTC (permalink / raw) To: miquel.raynal, vigneshr, linux-mtd, linux-kernel Cc: richard, alvinzhou, leoyu, Cheng Ming Lin From: Cheng Ming Lin <chengminglin@mxic.com.tw> Macronix serial NAND flash with a two-plane structure requires insertion of Plane Select bit into the column address during the write_to_cache operation. Additionally, for MX35{U,F}2G14AC, insertion of Plane Select bit into the column address is required during the read_from_cache operation. Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw> --- drivers/mtd/nand/spi/macronix.c | 51 +++++++++++++++++++++++++++++---- 1 file changed, 45 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c index 3f9e9c572854..c61f1ba31f0c 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -100,6 +100,39 @@ static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand, return -EINVAL; } +/** + * Macronix serial NAND flash with a two-plane structure + * should insert Plane Select bit into the column address + * during the write_to_cache operation. + * Additionally, MX35{U,F}2G14AC also need to insert Plane + * Select bit into the column address during the read_from_cache + * operation. + */ +static unsigned int write_Plane_Select_bit_in_cadd(struct spinand_device *spinand, + const struct nand_page_io_req *req, unsigned int column) +{ + struct nand_device *nand = spinand_to_nand(spinand); + + return column | (req->pos.plane << fls(nanddev_page_size(nand))); +} + +static u16 read_Plane_Select_bit_in_cadd(struct spinand_device *spinand, + const struct nand_page_io_req *req, u16 column) +{ + struct nand_device *nand = spinand_to_nand(spinand); + + return column | (req->pos.plane << fls(nanddev_page_size(nand))); +} + +static const struct spi_nand_fixups write_fixups = { + .write_to_cache = write_Plane_Select_bit_in_cadd, +}; + +static const struct spi_nand_fixups read_and_write_fixups = { + .write_to_cache = write_Plane_Select_bit_in_cadd, + .read_from_cache = read_Plane_Select_bit_in_cadd, +}; + static const struct spinand_info macronix_spinand_table[] = { SPINAND_INFO("MX35LF1GE4AB", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12), @@ -157,7 +190,8 @@ static const struct spinand_info macronix_spinand_table[] = { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35LF2G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x64, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), @@ -175,7 +209,8 @@ static const struct spinand_info macronix_spinand_table[] = { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35LF4G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x75, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), @@ -215,7 +250,8 @@ static const struct spinand_info macronix_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&read_and_write_fixups)), SPINAND_INFO("MX35UF4G24AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1), @@ -225,7 +261,8 @@ static const struct spinand_info macronix_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35UF4G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xf5, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), @@ -255,7 +292,8 @@ static const struct spinand_info macronix_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&read_and_write_fixups)), SPINAND_INFO("MX35UF2G24AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), @@ -265,7 +303,8 @@ static const struct spinand_info macronix_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35UF2G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe4, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), -- 2.25.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 2/3] mtd: spinand: macronix: Fixups for PLANE_SELECT_BIT 2024-07-10 1:15 ` Cheng Ming Lin @ 2024-07-10 22:09 ` kernel test robot -1 siblings, 0 replies; 12+ messages in thread From: kernel test robot @ 2024-07-10 22:09 UTC (permalink / raw) To: Cheng Ming Lin, miquel.raynal, vigneshr, linux-mtd, linux-kernel Cc: llvm, oe-kbuild-all, richard, alvinzhou, leoyu, Cheng Ming Lin Hi Cheng, kernel test robot noticed the following build warnings: [auto build test WARNING on mtd/nand/next] [also build test WARNING on next-20240710] [cannot apply to linus/master v6.10-rc7] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Cheng-Ming-Lin/include-linux-mtd-spinand-h-Add-fixups-for-spinand/20240710-184654 base: https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next patch link: https://lore.kernel.org/r/20240710011541.342682-3-linchengming884%40gmail.com patch subject: [PATCH 2/3] mtd: spinand: macronix: Fixups for PLANE_SELECT_BIT config: i386-randconfig-014-20240711 (https://download.01.org/0day-ci/archive/20240711/202407110520.pbPnrOlM-lkp@intel.com/config) compiler: clang version 18.1.5 (https://github.com/llvm/llvm-project 617a15a9eac96088ae5e9134248d8236e34b91b1) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240711/202407110520.pbPnrOlM-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202407110520.pbPnrOlM-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/mtd/nand/spi/macronix.c:113: warning: Function parameter or struct member 'spinand' not described in 'write_Plane_Select_bit_in_cadd' >> drivers/mtd/nand/spi/macronix.c:113: warning: Function parameter or struct member 'req' not described in 'write_Plane_Select_bit_in_cadd' >> drivers/mtd/nand/spi/macronix.c:113: warning: Function parameter or struct member 'column' not described in 'write_Plane_Select_bit_in_cadd' >> drivers/mtd/nand/spi/macronix.c:113: warning: expecting prototype for Macronix serial NAND flash with a two(). Prototype was for write_Plane_Select_bit_in_cadd() instead vim +113 drivers/mtd/nand/spi/macronix.c 102 103 /** 104 * Macronix serial NAND flash with a two-plane structure 105 * should insert Plane Select bit into the column address 106 * during the write_to_cache operation. 107 * Additionally, MX35{U,F}2G14AC also need to insert Plane 108 * Select bit into the column address during the read_from_cache 109 * operation. 110 */ 111 static unsigned int write_Plane_Select_bit_in_cadd(struct spinand_device *spinand, 112 const struct nand_page_io_req *req, unsigned int column) > 113 { 114 struct nand_device *nand = spinand_to_nand(spinand); 115 116 return column | (req->pos.plane << fls(nanddev_page_size(nand))); 117 } 118 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/3] mtd: spinand: macronix: Fixups for PLANE_SELECT_BIT @ 2024-07-10 22:09 ` kernel test robot 0 siblings, 0 replies; 12+ messages in thread From: kernel test robot @ 2024-07-10 22:09 UTC (permalink / raw) To: Cheng Ming Lin, miquel.raynal, vigneshr, linux-mtd, linux-kernel Cc: llvm, oe-kbuild-all, richard, alvinzhou, leoyu, Cheng Ming Lin Hi Cheng, kernel test robot noticed the following build warnings: [auto build test WARNING on mtd/nand/next] [also build test WARNING on next-20240710] [cannot apply to linus/master v6.10-rc7] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Cheng-Ming-Lin/include-linux-mtd-spinand-h-Add-fixups-for-spinand/20240710-184654 base: https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next patch link: https://lore.kernel.org/r/20240710011541.342682-3-linchengming884%40gmail.com patch subject: [PATCH 2/3] mtd: spinand: macronix: Fixups for PLANE_SELECT_BIT config: i386-randconfig-014-20240711 (https://download.01.org/0day-ci/archive/20240711/202407110520.pbPnrOlM-lkp@intel.com/config) compiler: clang version 18.1.5 (https://github.com/llvm/llvm-project 617a15a9eac96088ae5e9134248d8236e34b91b1) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240711/202407110520.pbPnrOlM-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202407110520.pbPnrOlM-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/mtd/nand/spi/macronix.c:113: warning: Function parameter or struct member 'spinand' not described in 'write_Plane_Select_bit_in_cadd' >> drivers/mtd/nand/spi/macronix.c:113: warning: Function parameter or struct member 'req' not described in 'write_Plane_Select_bit_in_cadd' >> drivers/mtd/nand/spi/macronix.c:113: warning: Function parameter or struct member 'column' not described in 'write_Plane_Select_bit_in_cadd' >> drivers/mtd/nand/spi/macronix.c:113: warning: expecting prototype for Macronix serial NAND flash with a two(). Prototype was for write_Plane_Select_bit_in_cadd() instead vim +113 drivers/mtd/nand/spi/macronix.c 102 103 /** 104 * Macronix serial NAND flash with a two-plane structure 105 * should insert Plane Select bit into the column address 106 * during the write_to_cache operation. 107 * Additionally, MX35{U,F}2G14AC also need to insert Plane 108 * Select bit into the column address during the read_from_cache 109 * operation. 110 */ 111 static unsigned int write_Plane_Select_bit_in_cadd(struct spinand_device *spinand, 112 const struct nand_page_io_req *req, unsigned int column) > 113 { 114 struct nand_device *nand = spinand_to_nand(spinand); 115 116 return column | (req->pos.plane << fls(nanddev_page_size(nand))); 117 } 118 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/3] mtd: spinand: Insert Plane Select bit for the column address 2024-07-10 1:15 ` Cheng Ming Lin @ 2024-07-10 1:15 ` Cheng Ming Lin -1 siblings, 0 replies; 12+ messages in thread From: Cheng Ming Lin @ 2024-07-10 1:15 UTC (permalink / raw) To: miquel.raynal, vigneshr, linux-mtd, linux-kernel Cc: richard, alvinzhou, leoyu, Cheng Ming Lin From: Cheng Ming Lin <chengminglin@mxic.com.tw> In the function spinand_read_from_cache_op and spinand_write_to_cache_op, add an if statement to determine whether the device has fixups and their corresponding functions. If so, give the Plane Select bit to the column address. In the function spinand_match_and_init, add spinand_info in spinand_device for determining whether Plane Select bit should be inserted. Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw> --- drivers/mtd/nand/spi/core.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index e0b6715e5dfe..d6d6f3832f9d 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -386,6 +386,9 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand, else rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc; + if (spinand->info->fixups && spinand->info->fixups->read_from_cache) + column = spinand->info->fixups->read_from_cache(spinand, req, column); + while (nbytes) { ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf); if (ret < 0) @@ -460,6 +463,9 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand, else wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc; + if (spinand->info->fixups && spinand->info->fixups->write_to_cache) + column = spinand->info->fixups->write_to_cache(spinand, req, column); + while (nbytes) { ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf); if (ret < 0) @@ -1095,6 +1101,7 @@ int spinand_match_and_init(struct spinand_device *spinand, spinand->flags = table[i].flags; spinand->id.len = 1 + table[i].devid.len; spinand->select_target = table[i].select_target; + spinand->info = info; op = spinand_select_op_variant(spinand, info->op_variants.read_cache); -- 2.25.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/3] mtd: spinand: Insert Plane Select bit for the column address @ 2024-07-10 1:15 ` Cheng Ming Lin 0 siblings, 0 replies; 12+ messages in thread From: Cheng Ming Lin @ 2024-07-10 1:15 UTC (permalink / raw) To: miquel.raynal, vigneshr, linux-mtd, linux-kernel Cc: richard, alvinzhou, leoyu, Cheng Ming Lin From: Cheng Ming Lin <chengminglin@mxic.com.tw> In the function spinand_read_from_cache_op and spinand_write_to_cache_op, add an if statement to determine whether the device has fixups and their corresponding functions. If so, give the Plane Select bit to the column address. In the function spinand_match_and_init, add spinand_info in spinand_device for determining whether Plane Select bit should be inserted. Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw> --- drivers/mtd/nand/spi/core.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index e0b6715e5dfe..d6d6f3832f9d 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -386,6 +386,9 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand, else rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc; + if (spinand->info->fixups && spinand->info->fixups->read_from_cache) + column = spinand->info->fixups->read_from_cache(spinand, req, column); + while (nbytes) { ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf); if (ret < 0) @@ -460,6 +463,9 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand, else wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc; + if (spinand->info->fixups && spinand->info->fixups->write_to_cache) + column = spinand->info->fixups->write_to_cache(spinand, req, column); + while (nbytes) { ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf); if (ret < 0) @@ -1095,6 +1101,7 @@ int spinand_match_and_init(struct spinand_device *spinand, spinand->flags = table[i].flags; spinand->id.len = 1 + table[i].devid.len; spinand->select_target = table[i].select_target; + spinand->info = info; op = spinand_select_op_variant(spinand, info->op_variants.read_cache); -- 2.25.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 0/3] Add fixups for two-plane serial NAND flash 2024-07-10 1:15 ` Cheng Ming Lin @ 2024-07-17 8:16 ` Miquel Raynal -1 siblings, 0 replies; 12+ messages in thread From: Miquel Raynal @ 2024-07-17 8:16 UTC (permalink / raw) To: Cheng Ming Lin Cc: vigneshr, linux-mtd, linux-kernel, richard, alvinzhou, leoyu, Cheng Ming Lin Hi Cheng, linchengming884@gmail.com wrote on Wed, 10 Jul 2024 09:15:38 +0800: > From: Cheng Ming Lin <chengminglin@mxic.com.tw> > > Macronix serial NAND flash with a two-plane structure > requires insertion of Plane Select bit into the column > address during the write_to_cache operation. > > Additionally, for MX35{U,F}2G14AC, insertion of Plane > Select bit into the column address is required during > the read_from_cache operation. > > In spinand.h, add struct spi_nand_fixups as SPI NAND > fixup hooks. > > In macronix.c, add fixup functions and update ID table. > > In core.c, add an if statement to determine whether to > insert the Plane Select bit for the column address. > > These flashes have been validated on Xilinx zynq-picozed > board which included Macronix SPI Host. > > Cheng Ming Lin (3): > include/linux/mtd/spinand.h: Add fixups for spinand > mtd: spinand: macronix: Fixups for PLANE_SELECT_BIT > mtd: spinand: Insert Plane Select bit for the column address I believe patches 1 and 3 should be squashed and come before patch 2. In general in your code, please avoid camelCase. Finally, I am not convinced yet by this implementation, I don't know what to propose yet, but I am not particularly in favor of adding such hooks. Can you point to a datasheet (url and page) where I could get more information? > > drivers/mtd/nand/spi/core.c | 7 +++++ > drivers/mtd/nand/spi/macronix.c | 51 +++++++++++++++++++++++++++++---- > include/linux/mtd/spinand.h | 17 +++++++++++ > 3 files changed, 69 insertions(+), 6 deletions(-) > Thanks, Miquèl ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/3] Add fixups for two-plane serial NAND flash @ 2024-07-17 8:16 ` Miquel Raynal 0 siblings, 0 replies; 12+ messages in thread From: Miquel Raynal @ 2024-07-17 8:16 UTC (permalink / raw) To: Cheng Ming Lin Cc: vigneshr, linux-mtd, linux-kernel, richard, alvinzhou, leoyu, Cheng Ming Lin Hi Cheng, linchengming884@gmail.com wrote on Wed, 10 Jul 2024 09:15:38 +0800: > From: Cheng Ming Lin <chengminglin@mxic.com.tw> > > Macronix serial NAND flash with a two-plane structure > requires insertion of Plane Select bit into the column > address during the write_to_cache operation. > > Additionally, for MX35{U,F}2G14AC, insertion of Plane > Select bit into the column address is required during > the read_from_cache operation. > > In spinand.h, add struct spi_nand_fixups as SPI NAND > fixup hooks. > > In macronix.c, add fixup functions and update ID table. > > In core.c, add an if statement to determine whether to > insert the Plane Select bit for the column address. > > These flashes have been validated on Xilinx zynq-picozed > board which included Macronix SPI Host. > > Cheng Ming Lin (3): > include/linux/mtd/spinand.h: Add fixups for spinand > mtd: spinand: macronix: Fixups for PLANE_SELECT_BIT > mtd: spinand: Insert Plane Select bit for the column address I believe patches 1 and 3 should be squashed and come before patch 2. In general in your code, please avoid camelCase. Finally, I am not convinced yet by this implementation, I don't know what to propose yet, but I am not particularly in favor of adding such hooks. Can you point to a datasheet (url and page) where I could get more information? > > drivers/mtd/nand/spi/core.c | 7 +++++ > drivers/mtd/nand/spi/macronix.c | 51 +++++++++++++++++++++++++++++---- > include/linux/mtd/spinand.h | 17 +++++++++++ > 3 files changed, 69 insertions(+), 6 deletions(-) > Thanks, Miquèl ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2024-07-17 8:16 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-07-10 1:15 [PATCH 0/3] Add fixups for two-plane serial NAND flash Cheng Ming Lin 2024-07-10 1:15 ` Cheng Ming Lin 2024-07-10 1:15 ` [PATCH 1/3] include/linux/mtd/spinand.h: Add fixups for spinand Cheng Ming Lin 2024-07-10 1:15 ` Cheng Ming Lin 2024-07-10 1:15 ` [PATCH 2/3] mtd: spinand: macronix: Fixups for PLANE_SELECT_BIT Cheng Ming Lin 2024-07-10 1:15 ` Cheng Ming Lin 2024-07-10 22:09 ` kernel test robot 2024-07-10 22:09 ` kernel test robot 2024-07-10 1:15 ` [PATCH 3/3] mtd: spinand: Insert Plane Select bit for the column address Cheng Ming Lin 2024-07-10 1:15 ` Cheng Ming Lin 2024-07-17 8:16 ` [PATCH 0/3] Add fixups for two-plane serial NAND flash Miquel Raynal 2024-07-17 8:16 ` Miquel Raynal
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