Re: [RFC] iommu_ops->domain_alloc_paging() enhancement to support AMD IOMMU driver

[Jason Gunthorpe <jgg@ziepe.ca>]

On Fri, Jul 12, 2024 at 02:40:37PM +0100, Robin Murphy wrote:
> > > BTW. SVA domain shall not be attached to RID I suppose. This should
> > > be a common restriction across vendors. Do you think it is valuable
> > > to let iommu core block such an attempt?
> > 
> > Yeah, maybe.
> 
> There's no functional reason to disallow it for Arm SMMUs, at least, so it's
> something that could potentially want relaxing back to per-driver in
> future.

I think everyone can technically do SVA as everyone should be able to
do PRI on the RID. We want PRI on RID anyhow for unpinned guest KVM
support someday.

My specific "maybe" was because SVA is troublesome for MSI, on ARM we
won't have an ITS page mapped for instance.

> I've heard murmurings over the years about potential use-cases for SVA with
> platform and/or non-PASID PCI devices, but never anything concrete for
> existing hardware. I imagine we can expect to see more SVA-interested
> on-chip accelerators in future, but whether they'll all be nice and support
> Substreams (i.e. "platform PASIDs") is the question...

So I guess they don't send MSI down those special stream ids? It makes
sense as a use case to me.

Thanks,
Jason