Re: [PATCH v6 4/4] hw/cxl/cxl-mailbox-utils: Add device DDR5 ECS control feature

[Jonathan Cameron <Jonathan.Cameron@Huawei.com>]

On Fri, 5 Jul 2024 13:30:38 +0100
Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote:

> From: Shiju Jose <shiju.jose@huawei.com>
> 
> CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS)
> control feature.

Hi Michael / all,

Silly stray white space issue inline that checkpatch will catch.

> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index dda35f2528..222db7032d 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -829,6 +829,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
>      uint8_t *pci_conf = pci_dev->config;
>      unsigned short msix_num = 6;
>      int i, rc;
> +    uint16_t count;
>  
>      QTAILQ_INIT(&ct3d->error_list);
>  
> @@ -901,6 +902,19 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
>                             CXL_MEMDEV_PS_CUR_SCRUB_CYCLE_DEFAULT |
>                             (CXL_MEMDEV_PS_MIN_SCRUB_CYCLE_DEFAULT << 8);
>      ct3d->patrol_scrub_attrs.scrub_flags = CXL_MEMDEV_PS_ENABLE_DEFAULT;
> +    

Sorry - stray whitespace here.  I'll not send a new version for just this though.


> +    /* Set default value for DDR5 ECS read attributes */
> +    for (count = 0; count < CXL_ECS_NUM_MEDIA_FRUS; count++) {
> +        ct3d->ecs_attrs[count].ecs_log_cap =
> +                            CXL_ECS_LOG_ENTRY_TYPE_DEFAULT;
> +        ct3d->ecs_attrs[count].ecs_cap =
> +                            CXL_ECS_REALTIME_REPORT_CAP_DEFAULT;
> +        ct3d->ecs_attrs[count].ecs_config =
> +                            CXL_ECS_THRESHOLD_COUNT_DEFAULT |
> +                            (CXL_ECS_MODE_DEFAULT << 3);
> +        /* Reserved */
> +        ct3d->ecs_attrs[count].ecs_flags = 0;
> +    }
>  
>      return;
>