* [linux dev-6.6 v1 1/3] arm64: dts: nuvoton: npcm8xx: add reference 25m clock property
@ 2024-07-14 15:26 Tomer Maimon
2024-07-14 15:26 ` [linux dev-6.6 v1 2/3] arm64: dts: nuvoton: npcm8xx: add pin and gpio controller nodes Tomer Maimon
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Tomer Maimon @ 2024-07-14 15:26 UTC (permalink / raw)
To: openbmc; +Cc: Joel Stanley, Tomer Maimon
The NPCM8XX clock driver uses a 25Mhz external clock, therefore adding
clock property.
The new required clock property does not break the NPCM8XX clock ABI
since the NPCM8XX clock driver hasn't merged yet to the Linux vanilla.
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 9 +++++----
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 7 +++++++
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
index 91c1b5c4d635..9bd22f7d43f4 100644
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
@@ -58,6 +58,7 @@ clk: clock-controller@f0801000 {
compatible = "nuvoton,npcm845-clk";
#clock-cells = <1>;
reg = <0x0 0xf0801000 0x0 0x1000>;
+ clocks = <&refclk>;
};
apb {
@@ -81,7 +82,7 @@ timer0: timer@8000 {
compatible = "nuvoton,npcm845-timer";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x8000 0x1C>;
- clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ clocks = <&refclk>;
clock-names = "refclk";
};
@@ -153,7 +154,7 @@ watchdog0: watchdog@801c {
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x801c 0x4>;
status = "disabled";
- clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ clocks = <&refclk>;
syscon = <&gcr>;
};
@@ -162,7 +163,7 @@ watchdog1: watchdog@901c {
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x901c 0x4>;
status = "disabled";
- clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ clocks = <&refclk>;
syscon = <&gcr>;
};
@@ -171,7 +172,7 @@ watchdog2: watchdog@a01c {
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xa01c 0x4>;
status = "disabled";
- clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ clocks = <&refclk>;
syscon = <&gcr>;
};
};
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
index a5ab2bc0f835..83c2f4e138e5 100644
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
@@ -19,6 +19,13 @@ chosen {
memory {
reg = <0x0 0x0 0x0 0x40000000>;
};
+
+ refclk: refclk-25mhz {
+ compatible = "fixed-clock";
+ clock-output-names = "ref";
+ clock-frequency = <25000000>;
+ #clock-cells = <0>;
+ };
};
&serial0 {
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [linux dev-6.6 v1 2/3] arm64: dts: nuvoton: npcm8xx: add pin and gpio controller nodes
2024-07-14 15:26 [linux dev-6.6 v1 1/3] arm64: dts: nuvoton: npcm8xx: add reference 25m clock property Tomer Maimon
@ 2024-07-14 15:26 ` Tomer Maimon
2024-07-14 15:26 ` [linux dev-6.6 v1 3/3] arm64: dts: nuvoton: npcm8xx: add modules node Tomer Maimon
2024-07-15 6:04 ` [linux dev-6.6 v1 1/3] arm64: dts: nuvoton: npcm8xx: add reference 25m clock property Andrew Jeffery
2 siblings, 0 replies; 8+ messages in thread
From: Tomer Maimon @ 2024-07-14 15:26 UTC (permalink / raw)
To: openbmc; +Cc: Joel Stanley, Tomer Maimon
Add BMC Nuvoton NPCM8XX pin and GPIO controller nodes.
The Pin controller node includes eight GPIO controller nodes, each GPIO
node control 32 GPIO.
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
.../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 699 ++++++++++++++++++
1 file changed, 699 insertions(+)
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
index 9bd22f7d43f4..8aef313a6ff6 100644
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/clock/nuvoton,npcm845-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <2>;
@@ -177,4 +178,702 @@ watchdog2: watchdog@a01c {
};
};
};
+
+ pinctrl: pinctrl@f0010000 {
+ compatible = "nuvoton,npcm845-pinctrl";
+ ranges = <0x0 0x0 0xf0010000 0x8000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nuvoton,sysgcr = <&gcr>;
+
+ gpio0: gpio@f0010000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0xB0>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ };
+ gpio1: gpio@f0011000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x1000 0xB0>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ };
+ gpio2: gpio@f0012000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x2000 0xB0>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ };
+ gpio3: gpio@f0013000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x3000 0xB0>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ };
+ gpio4: gpio@f0014000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x4000 0xB0>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ };
+ gpio5: gpio@f0015000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x5000 0xB0>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 160 32>;
+ };
+ gpio6: gpio@f0016000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x6000 0xB0>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 192 32>;
+ };
+ gpio7: gpio@f0017000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x7000 0xB0>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 224 32>;
+ };
+
+ iox1_pins: iox1-mux {
+ groups = "iox1";
+ function = "iox1";
+ };
+ iox2_pins: iox2-mux {
+ groups = "iox2";
+ function = "iox2";
+ };
+ smb1d_pins: smb1d-mux {
+ groups = "smb1d";
+ function = "smb1d";
+ };
+ smb2d_pins: smb2d-mux {
+ groups = "smb2d";
+ function = "smb2d";
+ };
+ lkgpo1_pins: lkgpo1-mux {
+ groups = "lkgpo1";
+ function = "lkgpo1";
+ };
+ lkgpo2_pins: lkgpo2-mux {
+ groups = "lkgpo2";
+ function = "lkgpo2";
+ };
+ ioxh_pins: ioxh-mux {
+ groups = "ioxh";
+ function = "ioxh";
+ };
+ gspi_pins: gspi-mux {
+ groups = "gspi";
+ function = "gspi";
+ };
+ smb5b_pins: smb5b-mux {
+ groups = "smb5b";
+ function = "smb5b";
+ };
+ smb5c_pins: smb5c-mux {
+ groups = "smb5c";
+ function = "smb5c";
+ };
+ lkgpo0_pins: lkgpo0-mux {
+ groups = "lkgpo0";
+ function = "lkgpo0";
+ };
+ pspi_pins: pspi-mux {
+ groups = "pspi";
+ function = "pspi";
+ };
+ jm1_pins: jm1-mux {
+ groups = "jm1";
+ function = "jm1";
+ };
+ jm2_pins: jm2-mux {
+ groups = "jm2";
+ function = "jm2";
+ };
+ smb4b_pins: smb4b-mux {
+ groups = "smb4b";
+ function = "smb4b";
+ };
+ smb4c_pins: smb4c-mux {
+ groups = "smb4c";
+ function = "smb4c";
+ };
+ smb15_pins: smb15-mux {
+ groups = "smb15";
+ function = "smb15";
+ };
+ smb16_pins: smb16-mux {
+ groups = "smb16";
+ function = "smb16";
+ };
+ smb17_pins: smb17-mux {
+ groups = "smb17";
+ function = "smb17";
+ };
+ smb18_pins: smb18-mux {
+ groups = "smb18";
+ function = "smb18";
+ };
+ smb19_pins: smb19-mux {
+ groups = "smb19";
+ function = "smb19";
+ };
+ smb20_pins: smb20-mux {
+ groups = "smb20";
+ function = "smb20";
+ };
+ smb21_pins: smb21-mux {
+ groups = "smb21";
+ function = "smb21";
+ };
+ smb22_pins: smb22-mux {
+ groups = "smb22";
+ function = "smb22";
+ };
+ smb23_pins: smb23-mux {
+ groups = "smb23";
+ function = "smb23";
+ };
+ smb4d_pins: smb4d-mux {
+ groups = "smb4d";
+ function = "smb4d";
+ };
+ smb14_pins: smb14-mux {
+ groups = "smb14";
+ function = "smb14";
+ };
+ smb5_pins: smb5-mux {
+ groups = "smb5";
+ function = "smb5";
+ };
+ smb4_pins: smb4-mux {
+ groups = "smb4";
+ function = "smb4";
+ };
+ smb3_pins: smb3-mux {
+ groups = "smb3";
+ function = "smb3";
+ };
+ spi0cs1_pins: spi0cs1-mux {
+ groups = "spi0cs1";
+ function = "spi0cs1";
+ };
+ spi0cs2_pins: spi0cs2-mux {
+ groups = "spi0cs2";
+ function = "spi0cs2";
+ };
+ spi0cs3_pins: spi0cs3-mux {
+ groups = "spi0cs3";
+ function = "spi0cs3";
+ };
+ smb3c_pins: smb3c-mux {
+ groups = "smb3c";
+ function = "smb3c";
+ };
+ smb3b_pins: smb3b-mux {
+ groups = "smb3b";
+ function = "smb3b";
+ };
+ bmcuart0a_pins: bmcuart0a-mux {
+ groups = "bmcuart0a";
+ function = "bmcuart0a";
+ };
+ uart1_pins: uart1-mux {
+ groups = "uart1";
+ function = "uart1";
+ };
+ jtag2_pins: jtag2-mux {
+ groups = "jtag2";
+ function = "jtag2";
+ };
+ bmcuart1_pins: bmcuart1-mux {
+ groups = "bmcuart1";
+ function = "bmcuart1";
+ };
+ uart2_pins: uart2-mux {
+ groups = "uart2";
+ function = "uart2";
+ };
+ bmcuart0b_pins: bmcuart0b-mux {
+ groups = "bmcuart0b";
+ function = "bmcuart0b";
+ };
+ r1err_pins: r1err-mux {
+ groups = "r1err";
+ function = "r1err";
+ };
+ r1md_pins: r1md-mux {
+ groups = "r1md";
+ function = "r1md";
+ };
+ r1oen_pins: r1oen-mux {
+ groups = "r1oen";
+ function = "r1oen";
+ };
+ r2oen_pins: r2oen-mux {
+ groups = "r2oen";
+ function = "r2oen";
+ };
+ rmii3_pins: rmii3-mux {
+ groups = "rmii3";
+ function = "rmii3";
+ };
+ r3oen_pins: r3oen-mux {
+ groups = "r3oen";
+ function = "r3oen";
+ };
+ smb3d_pins: smb3d-mux {
+ groups = "smb3d";
+ function = "smb3d";
+ };
+ fanin0_pins: fanin0-mux {
+ groups = "fanin0";
+ function = "fanin0";
+ };
+ fanin1_pins: fanin1-mux {
+ groups = "fanin1";
+ function = "fanin1";
+ };
+ fanin2_pins: fanin2-mux {
+ groups = "fanin2";
+ function = "fanin2";
+ };
+ fanin3_pins: fanin3-mux {
+ groups = "fanin3";
+ function = "fanin3";
+ };
+ fanin4_pins: fanin4-mux {
+ groups = "fanin4";
+ function = "fanin4";
+ };
+ fanin5_pins: fanin5-mux {
+ groups = "fanin5";
+ function = "fanin5";
+ };
+ fanin6_pins: fanin6-mux {
+ groups = "fanin6";
+ function = "fanin6";
+ };
+ fanin7_pins: fanin7-mux {
+ groups = "fanin7";
+ function = "fanin7";
+ };
+ fanin8_pins: fanin8-mux {
+ groups = "fanin8";
+ function = "fanin8";
+ };
+ fanin9_pins: fanin9-mux {
+ groups = "fanin9";
+ function = "fanin9";
+ };
+ fanin10_pins: fanin10-mux {
+ groups = "fanin10";
+ function = "fanin10";
+ };
+ fanin11_pins: fanin11-mux {
+ groups = "fanin11";
+ function = "fanin11";
+ };
+ fanin12_pins: fanin12-mux {
+ groups = "fanin12";
+ function = "fanin12";
+ };
+ fanin13_pins: fanin13-mux {
+ groups = "fanin13";
+ function = "fanin13";
+ };
+ fanin14_pins: fanin14-mux {
+ groups = "fanin14";
+ function = "fanin14";
+ };
+ fanin15_pins: fanin15-mux {
+ groups = "fanin15";
+ function = "fanin15";
+ };
+ pwm0_pins: pwm0-mux {
+ groups = "pwm0";
+ function = "pwm0";
+ };
+ pwm1_pins: pwm1-mux {
+ groups = "pwm1";
+ function = "pwm1";
+ };
+ pwm2_pins: pwm2-mux {
+ groups = "pwm2";
+ function = "pwm2";
+ };
+ pwm3_pins: pwm3-mux {
+ groups = "pwm3";
+ function = "pwm3";
+ };
+ r2_pins: r2-mux {
+ groups = "r2";
+ function = "r2";
+ };
+ r2err_pins: r2err-mux {
+ groups = "r2err";
+ function = "r2err";
+ };
+ r2md_pins: r2md-mux {
+ groups = "r2md";
+ function = "r2md";
+ };
+ r3rxer_pins: r3rxer-mux {
+ groups = "r3rxer";
+ function = "r3rxer";
+ };
+ ga20kbc_pins: ga20kbc-mux {
+ groups = "ga20kbc";
+ function = "ga20kbc";
+ };
+ smb5d_pins: smb5d-mux {
+ groups = "smb5d";
+ function = "smb5d";
+ };
+ lpc_pins: lpc-mux {
+ groups = "lpc";
+ function = "lpc";
+ };
+ espi_pins: espi-mux {
+ groups = "espi";
+ function = "espi";
+ };
+ sg1mdio_pins: sg1mdio-mux {
+ groups = "sg1mdio";
+ function = "sg1mdio";
+ };
+ rg2_pins: rg2-mux {
+ groups = "rg2";
+ function = "rg2";
+ };
+ ddr_pins: ddr-mux {
+ groups = "ddr";
+ function = "ddr";
+ };
+ i3c0_pins: i3c0-mux {
+ groups = "i3c0";
+ function = "i3c0";
+ };
+ i3c1_pins: i3c1-mux {
+ groups = "i3c1";
+ function = "i3c1";
+ };
+ i3c2_pins: i3c2-mux {
+ groups = "i3c2";
+ function = "i3c2";
+ };
+ i3c3_pins: i3c3-mux {
+ groups = "i3c3";
+ function = "i3c3";
+ };
+ i3c4_pins: i3c4-mux {
+ groups = "i3c4";
+ function = "i3c4";
+ };
+ i3c5_pins: i3c5-mux {
+ groups = "i3c5";
+ function = "i3c5";
+ };
+ smb0_pins: smb0-mux {
+ groups = "smb0";
+ function = "smb0";
+ };
+ smb1_pins: smb1-mux {
+ groups = "smb1";
+ function = "smb1";
+ };
+ smb2_pins: smb2-mux {
+ groups = "smb2";
+ function = "smb2";
+ };
+ smb2c_pins: smb2c-mux {
+ groups = "smb2c";
+ function = "smb2c";
+ };
+ smb2b_pins: smb2b-mux {
+ groups = "smb2b";
+ function = "smb2b";
+ };
+ smb1c_pins: smb1c-mux {
+ groups = "smb1c";
+ function = "smb1c";
+ };
+ smb1b_pins: smb1b-mux {
+ groups = "smb1b";
+ function = "smb1b";
+ };
+ smb8_pins: smb8-mux {
+ groups = "smb8";
+ function = "smb8";
+ };
+ smb9_pins: smb9-mux {
+ groups = "smb9";
+ function = "smb9";
+ };
+ smb10_pins: smb10-mux {
+ groups = "smb10";
+ function = "smb10";
+ };
+ smb11_pins: smb11-mux {
+ groups = "smb11";
+ function = "smb11";
+ };
+ sd1_pins: sd1-mux {
+ groups = "sd1";
+ function = "sd1";
+ };
+ sd1pwr_pins: sd1pwr-mux {
+ groups = "sd1pwr";
+ function = "sd1pwr";
+ };
+ pwm4_pins: pwm4-mux {
+ groups = "pwm4";
+ function = "pwm4";
+ };
+ pwm5_pins: pwm5-mux {
+ groups = "pwm5";
+ function = "pwm5";
+ };
+ pwm6_pins: pwm6-mux {
+ groups = "pwm6";
+ function = "pwm6";
+ };
+ pwm7_pins: pwm7-mux {
+ groups = "pwm7";
+ function = "pwm7";
+ };
+ pwm8_pins: pwm8-mux {
+ groups = "pwm8";
+ function = "pwm8";
+ };
+ pwm9_pins: pwm9-mux {
+ groups = "pwm9";
+ function = "pwm9";
+ };
+ pwm10_pins: pwm10-mux {
+ groups = "pwm10";
+ function = "pwm10";
+ };
+ pwm11_pins: pwm11-mux {
+ groups = "pwm11";
+ function = "pwm11";
+ };
+ mmc8_pins: mmc8-mux {
+ groups = "mmc8";
+ function = "mmc8";
+ };
+ mmc_pins: mmc-mux {
+ groups = "mmc";
+ function = "mmc";
+ };
+ mmcwp_pins: mmcwp-mux {
+ groups = "mmcwp";
+ function = "mmcwp";
+ };
+ mmccd_pins: mmccd-mux {
+ groups = "mmccd";
+ function = "mmccd";
+ };
+ mmcrst_pins: mmcrst-mux {
+ groups = "mmcrst";
+ function = "mmcrst";
+ };
+ clkout_pins: clkout-mux {
+ groups = "clkout";
+ function = "clkout";
+ };
+ serirq_pins: serirq-mux {
+ groups = "serirq";
+ function = "serirq";
+ };
+ scipme_pins: scipme-mux {
+ groups = "scipme";
+ function = "scipme";
+ };
+ smb6_pins: smb6-mux {
+ groups = "smb6";
+ function = "smb6";
+ };
+ smb6b_pins: smb6b-mux {
+ groups = "smb6b";
+ function = "smb6b";
+ };
+ smb6c_pins: smb6c-mux {
+ groups = "smb6c";
+ function = "smb6c";
+ };
+ smb6d_pins: smb6d-mux {
+ groups = "smb6d";
+ function = "smb6d";
+ };
+ smb7_pins: smb7-mux {
+ groups = "smb7";
+ function = "smb7";
+ };
+ smb7b_pins: smb7b-mux {
+ groups = "smb7b";
+ function = "smb7b";
+ };
+ smb7c_pins: smb7c-mux {
+ groups = "smb7c";
+ function = "smb7c";
+ };
+ smb7d_pins: smb7d-mux {
+ groups = "smb7d";
+ function = "smb7d";
+ };
+ spi1_pins: spi1-mux {
+ groups = "spi1";
+ function = "spi1";
+ };
+ faninx_pins: faninx-mux {
+ groups = "faninx";
+ function = "faninx";
+ };
+ r1_pins: r1-mux {
+ groups = "r1";
+ function = "r1";
+ };
+ spi3_pins: spi3-mux {
+ groups = "spi3";
+ function = "spi3";
+ };
+ spi3cs1_pins: spi3cs1-mux {
+ groups = "spi3cs1";
+ function = "spi3cs1";
+ };
+ spi3quad_pins: spi3quad-mux {
+ groups = "spi3quad";
+ function = "spi3quad";
+ };
+ spi3cs2_pins: spi3cs2-mux {
+ groups = "spi3cs2";
+ function = "spi3cs2";
+ };
+ spi3cs3_pins: spi3cs3-mux {
+ groups = "spi3cs3";
+ function = "spi3cs3";
+ };
+ nprd_smi_pins: nprd-smi-mux {
+ groups = "nprd_smi";
+ function = "nprd_smi";
+ };
+ smb0b_pins: smb0b-mux {
+ groups = "smb0b";
+ function = "smb0b";
+ };
+ smb0c_pins: smb0c-mux {
+ groups = "smb0c";
+ function = "smb0c";
+ };
+ smb0den_pins: smb0den-mux {
+ groups = "smb0den";
+ function = "smb0den";
+ };
+ smb0d_pins: smb0d-mux {
+ groups = "smb0d";
+ function = "smb0d";
+ };
+ ddc_pins: ddc-mux {
+ groups = "ddc";
+ function = "ddc";
+ };
+ rg2mdio_pins: rg2mdio-mux {
+ groups = "rg2mdio";
+ function = "rg2mdio";
+ };
+ wdog1_pins: wdog1-mux {
+ groups = "wdog1";
+ function = "wdog1";
+ };
+ wdog2_pins: wdog2-mux {
+ groups = "wdog2";
+ function = "wdog2";
+ };
+ smb12_pins: smb12-mux {
+ groups = "smb12";
+ function = "smb12";
+ };
+ smb13_pins: smb13-mux {
+ groups = "smb13";
+ function = "smb13";
+ };
+ spix_pins: spix-mux {
+ groups = "spix";
+ function = "spix";
+ };
+ spixcs1_pins: spixcs1-mux {
+ groups = "spixcs1";
+ function = "spixcs1";
+ };
+ clkreq_pins: clkreq-mux {
+ groups = "clkreq";
+ function = "clkreq";
+ };
+ hgpio0_pins: hgpio0-mux {
+ groups = "hgpio0";
+ function = "hgpio0";
+ };
+ hgpio1_pins: hgpio1-mux {
+ groups = "hgpio1";
+ function = "hgpio1";
+ };
+ hgpio2_pins: hgpio2-mux {
+ groups = "hgpio2";
+ function = "hgpio2";
+ };
+ hgpio3_pins: hgpio3-mux {
+ groups = "hgpio3";
+ function = "hgpio3";
+ };
+ hgpio4_pins: hgpio4-mux {
+ groups = "hgpio4";
+ function = "hgpio4";
+ };
+ hgpio5_pins: hgpio5-mux {
+ groups = "hgpio5";
+ function = "hgpio5";
+ };
+ hgpio6_pins: hgpio6-mux {
+ groups = "hgpio6";
+ function = "hgpio6";
+ };
+ hgpio7_pins: hgpio7-mux {
+ groups = "hgpio7";
+ function = "hgpio7";
+ };
+ bu4_pins: bu4-mux {
+ groups = "bu4";
+ function = "bu4";
+ };
+ bu4b_pins: bu4b-mux {
+ groups = "bu4b";
+ function = "bu4b";
+ };
+ bu5_pins: bu5-mux {
+ groups = "bu5";
+ function = "bu5";
+ };
+ bu5b_pins: bu5b-mux {
+ groups = "bu5b";
+ function = "bu5b";
+ };
+ bu6_pins: bu6-mux {
+ groups = "bu6";
+ function = "bu6";
+ };
+ gpo187_pins: gpo187-mux {
+ groups = "gpo187";
+ function = "gpo187";
+ };
+ };
};
\ No newline at end of file
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [linux dev-6.6 v1 3/3] arm64: dts: nuvoton: npcm8xx: add modules node
2024-07-14 15:26 [linux dev-6.6 v1 1/3] arm64: dts: nuvoton: npcm8xx: add reference 25m clock property Tomer Maimon
2024-07-14 15:26 ` [linux dev-6.6 v1 2/3] arm64: dts: nuvoton: npcm8xx: add pin and gpio controller nodes Tomer Maimon
@ 2024-07-14 15:26 ` Tomer Maimon
2024-07-15 8:27 ` Andrew Jeffery
2024-07-15 6:04 ` [linux dev-6.6 v1 1/3] arm64: dts: nuvoton: npcm8xx: add reference 25m clock property Andrew Jeffery
2 siblings, 1 reply; 8+ messages in thread
From: Tomer Maimon @ 2024-07-14 15:26 UTC (permalink / raw)
To: openbmc; +Cc: Joel Stanley, Tomer Maimon
Add the following modules nodes to Nuvoton NPCM8xx BMC device tree:
- GMAC.
- FIU.
- OHCI and EHCI.
- SDHCI.
- PCIe.
- VCD and ECE.
- KCS.
- BPC.
- eSPI.
- PECI.
- PSPI.
- JTAG master.
- RNG.
- ADC.
- SGPIO.
- PWM and FAN.
- I3C.
- I2C.
- GFXI.
- Thermal zone.
- UDC.
- OPTEE.
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
.../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 918 +++++++++++++++++-
.../boot/dts/nuvoton/nuvoton-npcm845.dtsi | 162 ++++
2 files changed, 1075 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
index 8aef313a6ff6..d733509cab90 100644
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
@@ -21,6 +21,23 @@ soc {
gcr: system-controller@f0800000 {
compatible = "nuvoton,npcm845-gcr", "syscon";
reg = <0x0 0xf0800000 0x0 0x1000>;
+ udc9_mux: mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x9C 0x3000>;
+ idle-states = <0x3000>;
+ };
+ };
+
+ rst: system-controller@f0801000 {
+ compatible = "nuvoton,npcm845-rst", "syscon";
+ reg = <0x0 0xf0801000 0x0 0xC4>;
+ };
+
+ fuse:fuse@f0189000 {
+ compatible = "nuvoton,npcm845-fuse", "syscon",
+ "simple-mfd";
+ reg = <0x0 0xf0189000 0x0 0x1000>;
};
gic: interrupt-controller@dfff9000 {
@@ -39,6 +56,12 @@ ppi_cluster0: interrupt-partition-0 {
};
};
};
+
+ spswc: spswc@f0800038 {
+ compatible = "nuvoton,npcm-sp-ctrl";
+ reg = <0x0 0xf0800038 0x0 0x4>;
+ };
+
};
ahb {
@@ -62,15 +85,276 @@ clk: clock-controller@f0801000 {
clocks = <&refclk>;
};
+ gmac0: eth@f0802000 {
+ device_type = "network";
+ compatible = "nuvoton,npcm-dwmac";
+ reg = <0x0 0xf0802000 0x0 0x2000>,
+ <0x0 0xf0780000 0x0 0x200>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clk NPCM8XX_CLK_AHB>;
+ clock-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sg1mdio_pins>;
+ status = "disabled";
+ };
+
+ gmac1: eth@f0804000 {
+ device_type = "network";
+ compatible = "snps,dwmac";
+ reg = <0x0 0xf0804000 0x0 0x2000>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clk NPCM8XX_CLK_AHB>;
+ clock-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rg2_pins
+ &rg2mdio_pins>;
+ status = "disabled";
+ };
+
+ gmac2: eth@f0806000 {
+ device_type = "network";
+ compatible = "snps,dwmac";
+ reg = <0x0 0xf0806000 0x0 0x2000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clk NPCM8XX_CLK_AHB>;
+ clock-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&r1_pins
+ &r1err_pins
+ &r1md_pins>;
+ status = "disabled";
+ };
+
+ gmac3: eth@f0808000 {
+ device_type = "network";
+ compatible = "snps,dwmac";
+ reg = <0x0 0xf0808000 0x0 0x2000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clk NPCM8XX_CLK_AHB>;
+ clock-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&r2_pins
+ &r2err_pins
+ &r2md_pins>;
+ status = "disabled";
+ };
+
+ ehci1: usb@f0828100 {
+ compatible = "nuvoton,npcm750-ehci";
+ reg = <0x0 0xf0828100 0x0 0x1000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ehci2: usb@f082a100 {
+ compatible = "nuvoton,npcm750-ehci";
+ reg = <0x0 0xf082a100 0x0 0x1000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ohci1: usb@f0829000 {
+ compatible = "nuvoton,npcm750-ohci", "generic-ohci";
+ reg = <0x0 0xf0829000 0x0 0x1000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ohci2: usb@f082b000 {
+ compatible = "nuvoton,npcm750-ohci", "generic-ohci";
+ reg = <0x0 0xf082b000 0x0 0x1000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sdhci: mmc@f0842000 {
+ compatible = "nuvoton,npcm845-sdhci";
+ reg = <0x0 0xf0842000 0x0 0x100>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM8XX_CLK_AHB>;
+ clock-names = "clk_mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc8_pins
+ &mmc_pins>;
+ status = "disabled";
+ };
+
+ pcie: pcie@e1000000 {
+ compatible = "nuvoton,npcm845-pcie";
+ device_type = "pci";
+ reg = <0x0 0xE1000000 0x0 0x1000>,
+ <0x0 0xE8000000 0x0 0x1000>;
+ bus-range = <0x0 0xF>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x01000000 0 0xe9000000 0x0 0xe9000000 0 0x01000000
+ 0x02000000 0 0xea000000 0x0 0xea000000 0 0x04000000>;
+ resets = <&rstc 0x34 15>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ nuvoton,sysgcr = <&gcr>;
+ };
+
+ fiu0: spi@fb000000 {
+ compatible = "nuvoton,npcm845-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0xfb000000 0x0 0x1000>,
+ <0x0 0x80000000 0x0 0x10000000>;
+ reg-names = "control", "memory";
+ clocks = <&clk NPCM8XX_CLK_SPI0>;
+ clock-names = "clk_ahb";
+ status = "disabled";
+ };
+
+ fiu1: spi@fb002000 {
+ compatible = "nuvoton,npcm845-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0xfb002000 0x0 0x1000>,
+ <0x0 0x90000000 0x0 0x4000000>;
+ reg-names = "control", "memory";
+ clocks = <&clk NPCM8XX_CLK_SPI1>;
+ clock-names = "clk_spi1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ status = "disabled";
+ };
+
+ fiu3: spi@c0000000 {
+ compatible = "nuvoton,npcm845-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0xc0000000 0x0 0x1000>,
+ <0x0 0xA0000000 0x0 0x20000000>;
+ reg-names = "control", "memory";
+ clocks = <&clk NPCM8XX_CLK_SPI3>;
+ clock-names = "clk_spi3";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3_pins>;
+ status = "disabled";
+ };
+
+ fiux: spi@fb001000 {
+ compatible = "nuvoton,npcm845-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0xfb001000 0x0 0x1000>,
+ <0x0 0xf8000000 0x0 0x2000000>;
+ reg-names = "control", "memory";
+ clocks = <&clk NPCM8XX_CLK_SPIX>;
+ clock-names = "clk_ahb";
+ status = "disabled";
+ };
+
+ pcimbox: pcimbox@f0848000 {
+ compatible = "nuvoton,npcm845-pci-mbox", "nuvoton,npcm750-pci-mbox",
+ "simple-mfd", "syscon";
+ reg = <0x0 0xf084C000 0x0 0x8
+ 0x0 0xf0848000 0x0 0x3F00>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ vcd: vcd@f0810000 {
+ compatible = "nuvoton,npcm845-vcd";
+ reg = <0x0 0xf0810000 0x0 0x10000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rstc 0x24 14>;
+ nuvoton,sysgcr = <&gcr>;
+ nuvoton,sysgfxi = <&gfxi>;
+ nuvoton,ece = <&ece>;
+ status = "disabled";
+ };
+
+ ece: video-codec@f0820000 {
+ compatible = "nuvoton,npcm845-ece";
+ reg = <0x0 0xf0820000 0x0 0x2000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rstc 0x24 13>;
+ status = "disabled";
+ };
+
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges = <0x0 0x0 0xf0000000 0x00300000>,
- <0xfff00000 0x0 0xfff00000 0x00016000>;
+ <0xfff00000 0x0 0xfff00000 0x00016000>,
+ <0xf0800000 0x0 0xf0800000 0x00060000>;
+
+ lpc_kcs: lpc_kcs@7000 {
+ compatible = "nuvoton,npcm845-lpc-kcs",
+ "simple-mfd", "syscon";
+ reg = <0x7000 0x40>;
+ reg-io-width = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x7000 0x40>;
+
+ kcs1: kcs1@0 {
+ compatible = "nuvoton,npcm845-kcs-bmc", "nuvoton,npcm750-kcs-bmc";
+ reg = <0x0 0x40>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ kcs_chan = <1>;
+ status = "disabled";
+ };
- peci: peci-controller@100000 {
+ kcs2: kcs2@0 {
+ compatible = "nuvoton,npcm845-kcs-bmc", "nuvoton,npcm750-kcs-bmc";
+ reg = <0x0 0x40>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ kcs_chan = <2>;
+ status = "disabled";
+ };
+
+ kcs3: kcs3@0 {
+ compatible = "nuvoton,npcm845-kcs-bmc", "nuvoton,npcm750-kcs-bmc";
+ reg = <0x0 0x40>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ kcs_chan = <3>;
+ status = "disabled";
+ };
+ };
+
+ lpc_host: lpc_host@7000 {
+ compatible = "nuvoton,npcm845-lpc-host",
+ "simple-mfd", "syscon";
+ reg = <0x7000 0x60>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x7000 0x60>;
+
+ lpc_bpc: lpc_bpc@40 {
+ compatible = "nuvoton,npcm845-lpc-bpc", "nuvoton,npcm750-lpc-bpc";
+ reg = <0x40 0x20>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ espi: espi@9f000 {
+ compatible = "nuvoton,npcm845-espi",
+ "simple-mfd", "syscon";
+ reg = <0x9f000 0x1000>;
+ vw_gpio: vw_gpio {
+ compatible = "nuvoton,npcm845-espi-vwgpio";
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ peci0: peci-controller@100000 {
compatible = "nuvoton,npcm845-peci";
reg = <0x100000 0x1000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
@@ -79,6 +363,48 @@ peci: peci-controller@100000 {
status = "disabled";
};
+ pspi: spi@201000 {
+ compatible = "nuvoton,npcm845-pspi";
+ reg = <0x201000 0x1000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pspi_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM8XX_CLK_APB5>;
+ clock-names = "clk_apb5";
+ resets = <&rstc 0x24 23>;
+ status = "disabled";
+ };
+
+ jtm1: jtm@208000 {
+ compatible = "nuvoton,npcm845-jtm";
+ reg = <0x208000 0x1000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&jm1_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM8XX_CLK_APB5>;
+ clock-names = "clk_apb5";
+ resets = <&rstc 0x74 29>;
+ status = "disabled";
+ };
+
+ jtm2: jtm@209000 {
+ compatible = "nuvoton,npcm845-jtm";
+ reg = <0x209000 0x1000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&jm2_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM8XX_CLK_APB5>;
+ clock-names = "clk_apb5";
+ resets = <&rstc 0x74 30>;
+ status = "disabled";
+ };
+
timer0: timer@8000 {
compatible = "nuvoton,npcm845-timer";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
@@ -126,27 +452,50 @@ serial3: serial@3000 {
serial4: serial@4000 {
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
reg = <0x4000 0x1000>;
- clocks = <&clk NPCM8XX_CLK_UART>;
+ clocks = <&clk NPCM8XX_CLK_UART2>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bu4_pins>;
status = "disabled";
};
serial5: serial@5000 {
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
reg = <0x5000 0x1000>;
- clocks = <&clk NPCM8XX_CLK_UART>;
+ clocks = <&clk NPCM8XX_CLK_UART2>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bu5_pins>;
status = "disabled";
};
serial6: serial@6000 {
compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
reg = <0x6000 0x1000>;
- clocks = <&clk NPCM8XX_CLK_UART>;
+ clocks = <&clk NPCM8XX_CLK_UART2>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bu6_pins>;
+ status = "disabled";
+ };
+
+ rng: rng@b000 {
+ compatible = "nuvoton,npcm845-rng";
+ reg = <0xb000 0x8>;
+ clocks = <&clk NPCM8XX_CLK_APB1>;
+ status = "disabled";
+ };
+
+ adc: adc@c000 {
+ compatible = "nuvoton,npcm845-adc";
+ reg = <0xC000 0x8>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM8XX_CLK_ADC>;
+ resets = <&rstc 0x20 27>;
+ syscon = <&fuse>;
status = "disabled";
};
@@ -176,6 +525,565 @@ watchdog2: watchdog@a01c {
clocks = <&refclk>;
syscon = <&gcr>;
};
+
+ tmps: tmps@188000 {
+ compatible = "nuvoton,npcm845-thermal";
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM8XX_CLK_APB4>;
+ reg = <0x188000 0x5C>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ sgpio1: sgpio@101000 {
+ compatible = "nuvoton,npcm845-sgpio";
+ reg = <0x101000 0x200>;
+ clocks = <&clk NPCM8XX_CLK_APB3>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&iox1_pins>;
+ nuvoton,input-ngpios = <64>;
+ nuvoton,output-ngpios = <64>;
+ status = "disabled";
+ };
+
+ sgpio2: sgpio@102000 {
+ compatible = "nuvoton,npcm845-sgpio";
+ reg = <0x102000 0x200>;
+ clocks = <&clk NPCM8XX_CLK_APB3>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&iox2_pins>;
+ nuvoton,input-ngpios = <64>;
+ nuvoton,output-ngpios = <64>;
+ status = "disabled";
+ };
+
+ pwm_fan:pwm-fan-controller@103000 {
+ compatible = "nuvoton,npcm845-pwm-fan";
+ reg = <0x103000 0x3000>,
+ <0x180000 0x8000>;
+ reg-names = "pwm", "fan";
+ clocks = <&clk NPCM8XX_CLK_APB3>,
+ <&clk NPCM8XX_CLK_APB4>;
+ clock-names = "pwm","fan";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins &pwm1_pins
+ &pwm2_pins &pwm3_pins
+ &pwm4_pins &pwm5_pins
+ &pwm6_pins &pwm7_pins
+ &pwm8_pins &pwm9_pins
+ &pwm10_pins &pwm11_pins
+ &fanin0_pins &fanin1_pins
+ &fanin2_pins &fanin3_pins
+ &fanin4_pins &fanin5_pins
+ &fanin6_pins &fanin7_pins
+ &fanin8_pins &fanin9_pins
+ &fanin10_pins &fanin11_pins
+ &fanin12_pins &fanin13_pins
+ &fanin14_pins &fanin15_pins>;
+ status = "disabled";
+ };
+
+ i3c0: i3c@fff10000 {
+ compatible = "silvaco,i3c-master";
+ reg = <0xfff10000 0x1000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i3c0_pins>;
+ clocks = <&clk NPCM8XX_CLK_AHB>, <&clk NPCM8XX_CLK_RCP>;
+ clock-names = "pclk", "fast_clk";
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rstc 0x74 8>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c1: i3c@fff11000 {
+ compatible = "silvaco,i3c-master";
+ reg = <0xfff11000 0x1000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i3c1_pins>;
+ clocks = <&clk NPCM8XX_CLK_AHB>, <&clk NPCM8XX_CLK_RCP>;
+ clock-names = "pclk", "fast_clk";
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rstc 0x74 9>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c2: i3c@fff12000 {
+ compatible = "silvaco,i3c-master";
+ reg = <0xfff12000 0x1000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i3c2_pins>;
+ clocks = <&clk NPCM8XX_CLK_AHB>, <&clk NPCM8XX_CLK_RCP>;
+ clock-names = "pclk", "fast_clk";
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rstc 0x74 10>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c3: i3c@fff13000 {
+ compatible = "silvaco,i3c-master";
+ reg = <0xfff13000 0x1000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i3c3_pins>;
+ clocks = <&clk NPCM8XX_CLK_AHB>, <&clk NPCM8XX_CLK_RCP>;
+ clock-names = "pclk", "fast_clk";
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rstc 0x74 11>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c4: i3c@fff14000 {
+ compatible = "silvaco,i3c-master";
+ reg = <0xfff14000 0x1000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i3c4_pins>;
+ clocks = <&clk NPCM8XX_CLK_AHB>, <&clk NPCM8XX_CLK_RCP>;
+ clock-names = "pclk", "fast_clk";
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rstc 0x74 12>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c5: i3c@fff15000 {
+ compatible = "silvaco,i3c-master";
+ reg = <0xfff15000 0x1000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i3c5_pins>;
+ clocks = <&clk NPCM8XX_CLK_AHB>, <&clk NPCM8XX_CLK_RCP>;
+ clock-names = "pclk", "fast_clk";
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rstc 0x74 13>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@80000 {
+ reg = <0x80000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb0_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@81000 {
+ reg = <0x81000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb1_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@82000 {
+ reg = <0x82000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb2_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@83000 {
+ reg = <0x83000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb3_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@84000 {
+ reg = <0x84000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb4_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@85000 {
+ reg = <0x85000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb5_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@86000 {
+ reg = <0x86000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb6_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@87000 {
+ reg = <0x87000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb7_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@88000 {
+ reg = <0x88000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb8_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c9: i2c@89000 {
+ reg = <0x89000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb9_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c10: i2c@8a000 {
+ reg = <0x8a000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb10_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c11: i2c@8b000 {
+ reg = <0x8b000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb11_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c12: i2c@8c000 {
+ reg = <0x8c000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb12_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c13: i2c@8d000 {
+ reg = <0x8d000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb13_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c14: i2c@8e000 {
+ reg = <0x8e000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb14_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c15: i2c@8f000 {
+ reg = <0x8f000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb15_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c16: i2c@fff00000 {
+ reg = <0xfff00000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb16_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c17: i2c@fff01000 {
+ reg = <0xfff01000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb17_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c18: i2c@fff02000 {
+ reg = <0xfff02000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb18_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c19: i2c@fff03000 {
+ reg = <0xfff03000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb19_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c20: i2c@fff04000 {
+ reg = <0xfff04000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb20_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c21: i2c@fff05000 {
+ reg = <0xfff05000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb21_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c22: i2c@fff06000 {
+ reg = <0xfff06000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb22_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c23: i2c@fff07000 {
+ reg = <0xfff07000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb23_pins>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c24: i2c@fff08000 {
+ reg = <0xfff08000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c25: i2c@fff09000 {
+ reg = <0xfff09000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c26: i2c@fff0a000 {
+ reg = <0xfff0a000 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ nuvoton,sys-mgr = <&gcr>;
+ status = "disabled";
+ };
+
+ gfxi: gfxi@e000 {
+ compatible = "nuvoton,npcm845-gfxi", "syscon",
+ "simple-mfd";
+ reg = <0xe000 0x100>;
+ };
+ };
+ };
+
+ thermal-zones {
+ cpu0_thermal: cpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tmps 0>;
+ trips {
+ cpu0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+ };
+ cpu1_thermal: cpu1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tmps 1>;
+ trips {
+ cpu1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
};
};
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
index 65ff5be54a06..1afbd6db9fae 100644
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
@@ -75,4 +75,166 @@ timer {
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ udc0_phy: usb-phy {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ };
+
+ ahb {
+ mc: memory-controller@f0824000 {
+ compatible = "nuvoton,npcm845-memory-controller";
+ reg = <0x0 0xf0824000 0x0 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ udc0:udc@f0830000 {
+ compatible = "nuvoton,npcm845-udc";
+ reg = <0x0 0xf0830000 0x0 0x1000
+ 0x0 0xfffeb000 0x0 0x800>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM8XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+
+ phys = <&udc0_phy>;
+ phy_type = "utmi_wide";
+ dr_mode = "peripheral";
+ status = "disabled";
+ };
+
+ udc1:udc@f0831000 {
+ compatible = "nuvoton,npcm845-udc";
+ reg = <0x0 0xf0831000 0x0 0x1000
+ 0x0 0xfffeb800 0x0 0x800>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM8XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+
+ phys = <&udc0_phy>;
+ phy_type = "utmi_wide";
+ dr_mode = "peripheral";
+ status = "disabled";
+ };
+
+ udc2:udc@f0832000 {
+ compatible = "nuvoton,npcm845-udc";
+ reg = <0x0 0xf0832000 0x0 0x1000
+ 0x0 0xfffec000 0x0 0x800>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM8XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+
+ phys = <&udc0_phy>;
+ phy_type = "utmi_wide";
+ dr_mode = "peripheral";
+ status = "disabled";
+ };
+
+ udc3:udc@f0833000 {
+ compatible = "nuvoton,npcm845-udc";
+ reg = <0x0 0xf0833000 0x0 0x1000
+ 0x0 0xfffec800 0x0 0x800>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM8XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+
+ phys = <&udc0_phy>;
+ phy_type = "utmi_wide";
+ dr_mode = "peripheral";
+ status = "disabled";
+ };
+
+ udc4:udc@f0834000 {
+ compatible = "nuvoton,npcm845-udc";
+ reg = <0x0 0xf0834000 0x0 0x1000
+ 0x0 0xfffed000 0x0 0x800>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM8XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+
+ phys = <&udc0_phy>;
+ phy_type = "utmi_wide";
+ dr_mode = "peripheral";
+ status = "disabled";
+ };
+
+ udc5:udc@f0835000 {
+ compatible = "nuvoton,npcm845-udc";
+ reg = <0x0 0xf0835000 0x0 0x1000
+ 0x0 0xfffed800 0x0 0x800>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM8XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+
+ phys = <&udc0_phy>;
+ phy_type = "utmi_wide";
+ dr_mode = "peripheral";
+ status = "disabled";
+ };
+
+ udc6:udc@f0836000 {
+ compatible = "nuvoton,npcm845-udc";
+ reg = <0x0 0xf0836000 0x0 0x1000
+ 0x0 0xfffee000 0x0 0x800>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM8XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+
+ phys = <&udc0_phy>;
+ phy_type = "utmi_wide";
+ dr_mode = "peripheral";
+ status = "disabled";
+ };
+
+ udc7:udc@f0837000 {
+ compatible = "nuvoton,npcm845-udc";
+ reg = <0x0 0xf0837000 0x0 0x1000
+ 0x0 0xfffee800 0x0 0x800>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM8XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+
+ phys = <&udc0_phy>;
+ phy_type = "utmi_wide";
+ dr_mode = "peripheral";
+ status = "disabled";
+ };
+
+ udc8:udc@f0838000 {
+ compatible = "nuvoton,npcm845-udc";
+ reg = <0x0 0xf0838000 0x0 0x1000
+ 0x0 0xfffef000 0x0 0x800>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM8XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+
+ nuvoton,sysgcr = <&gcr 0x9C 0xC000 0xC000>;
+ phys = <&udc0_phy>;
+ phy_type = "utmi_wide";
+ dr_mode = "peripheral";
+ status = "disabled";
+ };
+
+ udc9:udc@f0839000 {
+ compatible = "nuvoton,npcm845-udc";
+ reg = <0x0 0xf0839000 0x0 0x1000
+ 0x0 0xfffef800 0x0 0x800>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM8XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+
+ nuvoton,sysgcr = <&gcr 0x9C 0x3000 0x3000>;
+ phys = <&udc0_phy>;
+ phy_type = "utmi_wide";
+ dr_mode = "peripheral";
+ status = "disabled";
+ };
+ };
};
\ No newline at end of file
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [linux dev-6.6 v1 1/3] arm64: dts: nuvoton: npcm8xx: add reference 25m clock property
2024-07-14 15:26 [linux dev-6.6 v1 1/3] arm64: dts: nuvoton: npcm8xx: add reference 25m clock property Tomer Maimon
2024-07-14 15:26 ` [linux dev-6.6 v1 2/3] arm64: dts: nuvoton: npcm8xx: add pin and gpio controller nodes Tomer Maimon
2024-07-14 15:26 ` [linux dev-6.6 v1 3/3] arm64: dts: nuvoton: npcm8xx: add modules node Tomer Maimon
@ 2024-07-15 6:04 ` Andrew Jeffery
2024-07-15 9:16 ` Tomer Maimon
2 siblings, 1 reply; 8+ messages in thread
From: Andrew Jeffery @ 2024-07-15 6:04 UTC (permalink / raw)
To: Tomer Maimon, openbmc; +Cc: Joel Stanley
Hi Tomer,
In the future, can you please send your series with a cover letter with
the patches threaded under it?
If you're not already using it, b4 is a helpful tool for sending
patches:
https://b4.docs.kernel.org/en/latest/
I ask because it's not clear to me what the relationship of this series
is with respect to what's going on upstream. A cover letter is a great
place to explain whether the patches are:
1. A backport of those under review upstream
2. A backport of patches already merged upstream
3. Specific to the openbmc/linux tree and have no upstream equivalent
In the case of 1 and 2 (which are the ideal cases), I really prefer you
include a link to the upstream equivalents. The link makes it easier
for me to gauge how mature the patches are.
Regarding the patch content (rather than process), while the patches
all touch the NPCM8XX devicetree, they don't seem to have a coherent
feel otherwise :(
On Sun, 2024-07-14 at 18:26 +0300, Tomer Maimon wrote:
> The NPCM8XX clock driver uses a 25Mhz external clock, therefore adding
> clock property.
>
> The new required clock property does not break the NPCM8XX clock ABI
> since the NPCM8XX clock driver hasn't merged yet to the Linux vanilla.
This is a statement with respect to upstream, but it seems we've
already applied some of the patches here, and so there's possibly a
concern?
>
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
> arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 9 +++++----
> arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 7 +++++++
> 2 files changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> index 91c1b5c4d635..9bd22f7d43f4 100644
> --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> @@ -58,6 +58,7 @@ clk: clock-controller@f0801000 {
> compatible = "nuvoton,npcm845-clk";
> #clock-cells = <1>;
> reg = <0x0 0xf0801000 0x0 0x1000>;
> + clocks = <&refclk>;
> };
>
> apb {
> @@ -81,7 +82,7 @@ timer0: timer@8000 {
> compatible = "nuvoton,npcm845-timer";
> interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0x8000 0x1C>;
> - clocks = <&clk NPCM8XX_CLK_REFCLK>;
> + clocks = <&refclk>;
> clock-names = "refclk";
> };
>
> @@ -153,7 +154,7 @@ watchdog0: watchdog@801c {
> interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0x801c 0x4>;
> status = "disabled";
> - clocks = <&clk NPCM8XX_CLK_REFCLK>;
> + clocks = <&refclk>;
> syscon = <&gcr>;
> };
>
> @@ -162,7 +163,7 @@ watchdog1: watchdog@901c {
> interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0x901c 0x4>;
> status = "disabled";
> - clocks = <&clk NPCM8XX_CLK_REFCLK>;
> + clocks = <&refclk>;
> syscon = <&gcr>;
> };
>
> @@ -171,7 +172,7 @@ watchdog2: watchdog@a01c {
> interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0xa01c 0x4>;
> status = "disabled";
> - clocks = <&clk NPCM8XX_CLK_REFCLK>;
> + clocks = <&refclk>;
> syscon = <&gcr>;
> };
> };
> diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> index a5ab2bc0f835..83c2f4e138e5 100644
> --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> @@ -19,6 +19,13 @@ chosen {
> memory {
> reg = <0x0 0x0 0x0 0x40000000>;
> };
> +
> + refclk: refclk-25mhz {
The node name should probably just be 'clock' according to the generic
node names recommendation?
> + compatible = "fixed-clock";
> + clock-output-names = "ref";
> + clock-frequency = <25000000>;
> + #clock-cells = <0>;
> + };
Defining this in the .dts but referencing the label inside the .dtsi
feels a bit off to me (as the .dtsi is no-longer self-contained). How
about we define the node in the .dtsi but override it in the .dts?
Andrew
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [linux dev-6.6 v1 3/3] arm64: dts: nuvoton: npcm8xx: add modules node
2024-07-14 15:26 ` [linux dev-6.6 v1 3/3] arm64: dts: nuvoton: npcm8xx: add modules node Tomer Maimon
@ 2024-07-15 8:27 ` Andrew Jeffery
2024-07-15 9:35 ` Tomer Maimon
0 siblings, 1 reply; 8+ messages in thread
From: Andrew Jeffery @ 2024-07-15 8:27 UTC (permalink / raw)
To: Tomer Maimon, openbmc; +Cc: Joel Stanley
On Sun, 2024-07-14 at 18:26 +0300, Tomer Maimon wrote:
> Add the following modules nodes to Nuvoton NPCM8xx BMC device tree:
So we seem to be missing bindings for the following nodes:
> - GMAC.
> - OHCI
> - PCIe.
> - KCS.
> - eSPI.
> - JTAG master.
Can you chop these out of the patch, or send the bindings for these
nodes as part of the series, along with links to the corresponding
upstream patch series?
Also:
> - BPC.
What's BPC? I failed to map it to a node below, but possibly I didn't
look closely enough.
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
> .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 918 +++++++++++++++++-
> .../boot/dts/nuvoton/nuvoton-npcm845.dtsi | 162 ++++
> 2 files changed, 1075 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> index 8aef313a6ff6..d733509cab90 100644
> --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> @@ -21,6 +21,23 @@ soc {
> gcr: system-controller@f0800000 {
> compatible = "nuvoton,npcm845-gcr", "syscon";
> reg = <0x0 0xf0800000 0x0 0x1000>;
> + udc9_mux: mux-controller {
> + compatible = "mmio-mux";
> + #mux-control-cells = <1>;
> + mux-reg-masks = <0x9C 0x3000>;
> + idle-states = <0x3000>;
> + };
> + };
> +
> + rst: system-controller@f0801000 {
> + compatible = "nuvoton,npcm845-rst", "syscon";
> + reg = <0x0 0xf0801000 0x0 0xC4>;
> + };
> +
> + fuse:fuse@f0189000 {
> + compatible = "nuvoton,npcm845-fuse", "syscon",
> + "simple-mfd";
> + reg = <0x0 0xf0189000 0x0 0x1000>;
> };
>
> gic: interrupt-controller@dfff9000 {
> @@ -39,6 +56,12 @@ ppi_cluster0: interrupt-partition-0 {
> };
> };
> };
> +
> + spswc: spswc@f0800038 {
> + compatible = "nuvoton,npcm-sp-ctrl";
> + reg = <0x0 0xf0800038 0x0 0x4>;
> + };
> +
> };
>
> ahb {
> @@ -62,15 +85,276 @@ clk: clock-controller@f0801000 {
> clocks = <&refclk>;
> };
>
> + gmac0: eth@f0802000 {
> + device_type = "network";
> + compatible = "nuvoton,npcm-dwmac";
> + reg = <0x0 0xf0802000 0x0 0x2000>,
> + <0x0 0xf0780000 0x0 0x200>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + clocks = <&clk NPCM8XX_CLK_AHB>;
> + clock-names = "stmmaceth";
> + pinctrl-names = "default";
> + pinctrl-0 = <&sg1mdio_pins>;
> + status = "disabled";
> + };
> +
> + gmac1: eth@f0804000 {
> + device_type = "network";
> + compatible = "snps,dwmac";
> + reg = <0x0 0xf0804000 0x0 0x2000>;
> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + clocks = <&clk NPCM8XX_CLK_AHB>;
> + clock-names = "stmmaceth";
> + pinctrl-names = "default";
> + pinctrl-0 = <&rg2_pins
> + &rg2mdio_pins>;
> + status = "disabled";
> + };
> +
> + gmac2: eth@f0806000 {
> + device_type = "network";
> + compatible = "snps,dwmac";
> + reg = <0x0 0xf0806000 0x0 0x2000>;
> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + clocks = <&clk NPCM8XX_CLK_AHB>;
> + clock-names = "stmmaceth";
> + pinctrl-names = "default";
> + pinctrl-0 = <&r1_pins
> + &r1err_pins
> + &r1md_pins>;
> + status = "disabled";
> + };
> +
> + gmac3: eth@f0808000 {
> + device_type = "network";
> + compatible = "snps,dwmac";
> + reg = <0x0 0xf0808000 0x0 0x2000>;
> + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + clocks = <&clk NPCM8XX_CLK_AHB>;
> + clock-names = "stmmaceth";
> + pinctrl-names = "default";
> + pinctrl-0 = <&r2_pins
> + &r2err_pins
> + &r2md_pins>;
> + status = "disabled";
> + };
> +
> + ehci1: usb@f0828100 {
> + compatible = "nuvoton,npcm750-ehci";
> + reg = <0x0 0xf0828100 0x0 0x1000>;
> + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + ehci2: usb@f082a100 {
> + compatible = "nuvoton,npcm750-ehci";
> + reg = <0x0 0xf082a100 0x0 0x1000>;
> + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + ohci1: usb@f0829000 {
> + compatible = "nuvoton,npcm750-ohci", "generic-ohci";
> + reg = <0x0 0xf0829000 0x0 0x1000>;
> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + ohci2: usb@f082b000 {
> + compatible = "nuvoton,npcm750-ohci", "generic-ohci";
> + reg = <0x0 0xf082b000 0x0 0x1000>;
> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + sdhci: mmc@f0842000 {
> + compatible = "nuvoton,npcm845-sdhci";
> + reg = <0x0 0xf0842000 0x0 0x100>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk NPCM8XX_CLK_AHB>;
> + clock-names = "clk_mmc";
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc8_pins
> + &mmc_pins>;
> + status = "disabled";
> + };
> +
> + pcie: pcie@e1000000 {
> + compatible = "nuvoton,npcm845-pcie";
> + device_type = "pci";
> + reg = <0x0 0xE1000000 0x0 0x1000>,
> + <0x0 0xE8000000 0x0 0x1000>;
> + bus-range = <0x0 0xF>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + ranges = <0x01000000 0 0xe9000000 0x0 0xe9000000 0 0x01000000
> + 0x02000000 0 0xea000000 0x0 0xea000000 0 0x04000000>;
> + resets = <&rstc 0x34 15>;
> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
> + nuvoton,sysgcr = <&gcr>;
> + };
> +
> + fiu0: spi@fb000000 {
> + compatible = "nuvoton,npcm845-fiu";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0xfb000000 0x0 0x1000>,
> + <0x0 0x80000000 0x0 0x10000000>;
> + reg-names = "control", "memory";
> + clocks = <&clk NPCM8XX_CLK_SPI0>;
> + clock-names = "clk_ahb";
> + status = "disabled";
> + };
> +
> + fiu1: spi@fb002000 {
> + compatible = "nuvoton,npcm845-fiu";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0xfb002000 0x0 0x1000>,
> + <0x0 0x90000000 0x0 0x4000000>;
> + reg-names = "control", "memory";
> + clocks = <&clk NPCM8XX_CLK_SPI1>;
> + clock-names = "clk_spi1";
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi1_pins>;
> + status = "disabled";
> + };
> +
> + fiu3: spi@c0000000 {
> + compatible = "nuvoton,npcm845-fiu";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0xc0000000 0x0 0x1000>,
> + <0x0 0xA0000000 0x0 0x20000000>;
> + reg-names = "control", "memory";
> + clocks = <&clk NPCM8XX_CLK_SPI3>;
> + clock-names = "clk_spi3";
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi3_pins>;
> + status = "disabled";
> + };
> +
> + fiux: spi@fb001000 {
> + compatible = "nuvoton,npcm845-fiu";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0xfb001000 0x0 0x1000>,
> + <0x0 0xf8000000 0x0 0x2000000>;
> + reg-names = "control", "memory";
> + clocks = <&clk NPCM8XX_CLK_SPIX>;
> + clock-names = "clk_ahb";
> + status = "disabled";
> + };
> +
> + pcimbox: pcimbox@f0848000 {
> + compatible = "nuvoton,npcm845-pci-mbox", "nuvoton,npcm750-pci-mbox",
> + "simple-mfd", "syscon";
> + reg = <0x0 0xf084C000 0x0 0x8
> + 0x0 0xf0848000 0x0 0x3F00>;
> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + vcd: vcd@f0810000 {
> + compatible = "nuvoton,npcm845-vcd";
> + reg = <0x0 0xf0810000 0x0 0x10000>;
> + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&rstc 0x24 14>;
> + nuvoton,sysgcr = <&gcr>;
> + nuvoton,sysgfxi = <&gfxi>;
> + nuvoton,ece = <&ece>;
> + status = "disabled";
> + };
> +
> + ece: video-codec@f0820000 {
> + compatible = "nuvoton,npcm845-ece";
> + reg = <0x0 0xf0820000 0x0 0x2000>;
> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&rstc 0x24 13>;
> + status = "disabled";
> + };
> +
> apb {
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "simple-bus";
> interrupt-parent = <&gic>;
> ranges = <0x0 0x0 0xf0000000 0x00300000>,
> - <0xfff00000 0x0 0xfff00000 0x00016000>;
> + <0xfff00000 0x0 0xfff00000 0x00016000>,
> + <0xf0800000 0x0 0xf0800000 0x00060000>;
> +
> + lpc_kcs: lpc_kcs@7000 {
> + compatible = "nuvoton,npcm845-lpc-kcs",
> + "simple-mfd", "syscon";
> + reg = <0x7000 0x40>;
> + reg-io-width = <1>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x7000 0x40>;
> +
> + kcs1: kcs1@0 {
> + compatible = "nuvoton,npcm845-kcs-bmc", "nuvoton,npcm750-kcs-bmc";
> + reg = <0x0 0x40>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + kcs_chan = <1>;
> + status = "disabled";
> + };
>
> - peci: peci-controller@100000 {
No compatible? Did you test this with `make dtbs_check`?
> + kcs2: kcs2@0 {
> + compatible = "nuvoton,npcm845-kcs-bmc", "nuvoton,npcm750-kcs-bmc";
> + reg = <0x0 0x40>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + kcs_chan = <2>;
> + status = "disabled";
> + };
> +
> + kcs3: kcs3@0 {
> + compatible = "nuvoton,npcm845-kcs-bmc", "nuvoton,npcm750-kcs-bmc";
> + reg = <0x0 0x40>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + kcs_chan = <3>;
> + status = "disabled";
> + };
> + };
> +
> + lpc_host: lpc_host@7000 {
> + compatible = "nuvoton,npcm845-lpc-host",
> + "simple-mfd", "syscon";
> + reg = <0x7000 0x60>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x7000 0x60>;
> +
> + lpc_bpc: lpc_bpc@40 {
> + compatible = "nuvoton,npcm845-lpc-bpc", "nuvoton,npcm750-lpc-bpc";
> + reg = <0x40 0x20>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> + };
> +
> + espi: espi@9f000 {
> + compatible = "nuvoton,npcm845-espi",
> + "simple-mfd", "syscon";
> + reg = <0x9f000 0x1000>;
> + vw_gpio: vw_gpio {
> + compatible = "nuvoton,npcm845-espi-vwgpio";
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> + };
> +
> + peci0: peci-controller@100000 {
Didn't we define this one above? Should they be merged?
> compatible = "nuvoton,npcm845-peci";
> reg = <0x100000 0x1000>;
> interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> @@ -79,6 +363,48 @@ peci: peci-controller@100000 {
> status = "disabled";
> };
>
> + pspi: spi@201000 {
> + compatible = "nuvoton,npcm845-pspi";
> + reg = <0x201000 0x1000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pspi_pins>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk NPCM8XX_CLK_APB5>;
> + clock-names = "clk_apb5";
> + resets = <&rstc 0x24 23>;
> + status = "disabled";
> + };
> +
> + jtm1: jtm@208000 {
> + compatible = "nuvoton,npcm845-jtm";
> + reg = <0x208000 0x1000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&jm1_pins>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk NPCM8XX_CLK_APB5>;
> + clock-names = "clk_apb5";
> + resets = <&rstc 0x74 29>;
> + status = "disabled";
> + };
> +
> + jtm2: jtm@209000 {
> + compatible = "nuvoton,npcm845-jtm";
> + reg = <0x209000 0x1000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&jm2_pins>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk NPCM8XX_CLK_APB5>;
> + clock-names = "clk_apb5";
> + resets = <&rstc 0x74 30>;
> + status = "disabled";
> + };
> +
> timer0: timer@8000 {
> compatible = "nuvoton,npcm845-timer";
> interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> @@ -126,27 +452,50 @@ serial3: serial@3000 {
> serial4: serial@4000 {
> compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
> reg = <0x4000 0x1000>;
> - clocks = <&clk NPCM8XX_CLK_UART>;
> + clocks = <&clk NPCM8XX_CLK_UART2>;
> interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
> reg-shift = <2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&bu4_pins>;
> status = "disabled";
> };
>
> serial5: serial@5000 {
> compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
> reg = <0x5000 0x1000>;
> - clocks = <&clk NPCM8XX_CLK_UART>;
> + clocks = <&clk NPCM8XX_CLK_UART2>;
> interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
> reg-shift = <2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&bu5_pins>;
> status = "disabled";
> };
>
> serial6: serial@6000 {
> compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
> reg = <0x6000 0x1000>;
> - clocks = <&clk NPCM8XX_CLK_UART>;
> + clocks = <&clk NPCM8XX_CLK_UART2>;
The UART clock changes seem somewhat unrelated and probably deserve
their own patch?
> interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
> reg-shift = <2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&bu6_pins>;
> + status = "disabled";
This too.
Andrew
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [linux dev-6.6 v1 1/3] arm64: dts: nuvoton: npcm8xx: add reference 25m clock property
2024-07-15 6:04 ` [linux dev-6.6 v1 1/3] arm64: dts: nuvoton: npcm8xx: add reference 25m clock property Andrew Jeffery
@ 2024-07-15 9:16 ` Tomer Maimon
2024-07-16 2:59 ` Andrew Jeffery
0 siblings, 1 reply; 8+ messages in thread
From: Tomer Maimon @ 2024-07-15 9:16 UTC (permalink / raw)
To: Andrew Jeffery; +Cc: openbmc, Joel Stanley
Hi Andrew,
Thanks for your comments.
On Mon, 15 Jul 2024 at 09:05, Andrew Jeffery
<andrew@codeconstruct.com.au> wrote:
>
> Hi Tomer,
>
> In the future, can you please send your series with a cover letter with
> the patches threaded under it?
Sure!
>
> If you're not already using it, b4 is a helpful tool for sending
> patches:
I wasn't aware to B$, I will try it, thanks :-)
>
> https://b4.docs.kernel.org/en/latest/
>
> I ask because it's not clear to me what the relationship of this series
> is with respect to what's going on upstream. A cover letter is a great
> place to explain whether the patches are:
>
> 1. A backport of those under review upstream
> 2. A backport of patches already merged upstream
> 3. Specific to the openbmc/linux tree and have no upstream equivalent
>
> In the case of 1 and 2 (which are the ideal cases), I really prefer you
> include a link to the upstream equivalents. The link makes it easier
> for me to gauge how mature the patches are.
If I am sending one patch only do you like me to add under --- in the
patch explanation as well?
>
> Regarding the patch content (rather than process), while the patches
> all touch the NPCM8XX devicetree, they don't seem to have a coherent
> feel otherwise :(
>
> On Sun, 2024-07-14 at 18:26 +0300, Tomer Maimon wrote:
> > The NPCM8XX clock driver uses a 25Mhz external clock, therefore adding
> > clock property.
> >
> > The new required clock property does not break the NPCM8XX clock ABI
> > since the NPCM8XX clock driver hasn't merged yet to the Linux vanilla.
>
> This is a statement with respect to upstream, but it seems we've
> already applied some of the patches here, and so there's possibly a
> concern?
Unfortunately, the NPCM8XX clock driver has been removed in dev-6.6,
so the OpenBMC Linux kernel is dev-6.6 is in the same state as the
Linux kernel vanilla.
BTW, I don't see any concern with the reference clock patch, but the
DT maintainers asked me to mention it not cause any ABI issue.
>
> >
> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> > ---
> > arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 9 +++++----
> > arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 7 +++++++
> > 2 files changed, 12 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> > index 91c1b5c4d635..9bd22f7d43f4 100644
> > --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> > +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> > @@ -58,6 +58,7 @@ clk: clock-controller@f0801000 {
> > compatible = "nuvoton,npcm845-clk";
> > #clock-cells = <1>;
> > reg = <0x0 0xf0801000 0x0 0x1000>;
> > + clocks = <&refclk>;
> > };
> >
> > apb {
> > @@ -81,7 +82,7 @@ timer0: timer@8000 {
> > compatible = "nuvoton,npcm845-timer";
> > interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> > reg = <0x8000 0x1C>;
> > - clocks = <&clk NPCM8XX_CLK_REFCLK>;
> > + clocks = <&refclk>;
> > clock-names = "refclk";
> > };
> >
> > @@ -153,7 +154,7 @@ watchdog0: watchdog@801c {
> > interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
> > reg = <0x801c 0x4>;
> > status = "disabled";
> > - clocks = <&clk NPCM8XX_CLK_REFCLK>;
> > + clocks = <&refclk>;
> > syscon = <&gcr>;
> > };
> >
> > @@ -162,7 +163,7 @@ watchdog1: watchdog@901c {
> > interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> > reg = <0x901c 0x4>;
> > status = "disabled";
> > - clocks = <&clk NPCM8XX_CLK_REFCLK>;
> > + clocks = <&refclk>;
> > syscon = <&gcr>;
> > };
> >
> > @@ -171,7 +172,7 @@ watchdog2: watchdog@a01c {
> > interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> > reg = <0xa01c 0x4>;
> > status = "disabled";
> > - clocks = <&clk NPCM8XX_CLK_REFCLK>;
> > + clocks = <&refclk>;
> > syscon = <&gcr>;
> > };
> > };
> > diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> > index a5ab2bc0f835..83c2f4e138e5 100644
> > --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> > +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> > @@ -19,6 +19,13 @@ chosen {
> > memory {
> > reg = <0x0 0x0 0x0 0x40000000>;
> > };
> > +
> > + refclk: refclk-25mhz {
>
> The node name should probably just be 'clock' according to the generic
> node names recommendation?
What do you mean? refclock? I am not sure, for example:
https://elixir.bootlin.com/linux/v6.10-rc7/source/arch/arm64/boot/dts/freescale/imx8mq-evk.dts#L24
>
> > + compatible = "fixed-clock";
> > + clock-output-names = "ref";
> > + clock-frequency = <25000000>;
> > + #clock-cells = <0>;
> > + };
>
> Defining this in the .dts but referencing the label inside the .dtsi
> feels a bit off to me (as the .dtsi is no-longer self-contained). How
> about we define the node in the .dtsi but override it in the .dts?
I had a dissection about it with Krzysztof :-) I was told that since
it is a reference clock on the board and not inside the SoC it should
be defined in the DTS.
>
> Andrew
Best regards,
Tomer
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [linux dev-6.6 v1 3/3] arm64: dts: nuvoton: npcm8xx: add modules node
2024-07-15 8:27 ` Andrew Jeffery
@ 2024-07-15 9:35 ` Tomer Maimon
0 siblings, 0 replies; 8+ messages in thread
From: Tomer Maimon @ 2024-07-15 9:35 UTC (permalink / raw)
To: Andrew Jeffery; +Cc: openbmc, Joel Stanley
Hi Andrew,
Thank for your comments
On Mon, 15 Jul 2024 at 11:27, Andrew Jeffery
<andrew@codeconstruct.com.au> wrote:
>
> On Sun, 2024-07-14 at 18:26 +0300, Tomer Maimon wrote:
> > Add the following modules nodes to Nuvoton NPCM8xx BMC device tree:
>
> So we seem to be missing bindings for the following nodes:
Sure.
>
> > - GMAC.
> > - OHCI
> > - PCIe.
> > - KCS.
> > - eSPI.
> > - JTAG master.
>
> Can you chop these out of the patch, or send the bindings for these
> nodes as part of the series, along with links to the corresponding
> upstream patch series?
>
> Also:
>
> > - BPC.
>
> What's BPC? I failed to map it to a node below, but possibly I didn't
> look closely enough.
BPC - BIOS Post Code, It was in dev-5.15 and removed I was sent the
BPC dev-6.6 a few months ago, and I will send it in a few days.
>
> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> > ---
> > .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 918 +++++++++++++++++-
> > .../boot/dts/nuvoton/nuvoton-npcm845.dtsi | 162 ++++
> > 2 files changed, 1075 insertions(+), 5 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> > index 8aef313a6ff6..d733509cab90 100644
> > --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> > +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> > @@ -21,6 +21,23 @@ soc {
> > gcr: system-controller@f0800000 {
> > compatible = "nuvoton,npcm845-gcr", "syscon";
> > reg = <0x0 0xf0800000 0x0 0x1000>;
> > + udc9_mux: mux-controller {
> > + compatible = "mmio-mux";
> > + #mux-control-cells = <1>;
> > + mux-reg-masks = <0x9C 0x3000>;
> > + idle-states = <0x3000>;
> > + };
> > + };
> > +
> > + rst: system-controller@f0801000 {
> > + compatible = "nuvoton,npcm845-rst", "syscon";
> > + reg = <0x0 0xf0801000 0x0 0xC4>;
> > + };
> > +
> > + fuse:fuse@f0189000 {
> > + compatible = "nuvoton,npcm845-fuse", "syscon",
> > + "simple-mfd";
> > + reg = <0x0 0xf0189000 0x0 0x1000>;
> > };
> >
> > gic: interrupt-controller@dfff9000 {
> > @@ -39,6 +56,12 @@ ppi_cluster0: interrupt-partition-0 {
> > };
> > };
> > };
> > +
> > + spswc: spswc@f0800038 {
> > + compatible = "nuvoton,npcm-sp-ctrl";
> > + reg = <0x0 0xf0800038 0x0 0x4>;
> > + };
> > +
> > };
> >
> > ahb {
> > @@ -62,15 +85,276 @@ clk: clock-controller@f0801000 {
> > clocks = <&refclk>;
> > };
> >
> > + gmac0: eth@f0802000 {
> > + device_type = "network";
> > + compatible = "nuvoton,npcm-dwmac";
> > + reg = <0x0 0xf0802000 0x0 0x2000>,
> > + <0x0 0xf0780000 0x0 0x200>;
> > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "macirq";
> > + clocks = <&clk NPCM8XX_CLK_AHB>;
> > + clock-names = "stmmaceth";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&sg1mdio_pins>;
> > + status = "disabled";
> > + };
> > +
> > + gmac1: eth@f0804000 {
> > + device_type = "network";
> > + compatible = "snps,dwmac";
> > + reg = <0x0 0xf0804000 0x0 0x2000>;
> > + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "macirq";
> > + clocks = <&clk NPCM8XX_CLK_AHB>;
> > + clock-names = "stmmaceth";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&rg2_pins
> > + &rg2mdio_pins>;
> > + status = "disabled";
> > + };
> > +
> > + gmac2: eth@f0806000 {
> > + device_type = "network";
> > + compatible = "snps,dwmac";
> > + reg = <0x0 0xf0806000 0x0 0x2000>;
> > + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "macirq";
> > + clocks = <&clk NPCM8XX_CLK_AHB>;
> > + clock-names = "stmmaceth";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&r1_pins
> > + &r1err_pins
> > + &r1md_pins>;
> > + status = "disabled";
> > + };
> > +
> > + gmac3: eth@f0808000 {
> > + device_type = "network";
> > + compatible = "snps,dwmac";
> > + reg = <0x0 0xf0808000 0x0 0x2000>;
> > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "macirq";
> > + clocks = <&clk NPCM8XX_CLK_AHB>;
> > + clock-names = "stmmaceth";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&r2_pins
> > + &r2err_pins
> > + &r2md_pins>;
> > + status = "disabled";
> > + };
> > +
> > + ehci1: usb@f0828100 {
> > + compatible = "nuvoton,npcm750-ehci";
> > + reg = <0x0 0xf0828100 0x0 0x1000>;
> > + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + ehci2: usb@f082a100 {
> > + compatible = "nuvoton,npcm750-ehci";
> > + reg = <0x0 0xf082a100 0x0 0x1000>;
> > + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + ohci1: usb@f0829000 {
> > + compatible = "nuvoton,npcm750-ohci", "generic-ohci";
> > + reg = <0x0 0xf0829000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + ohci2: usb@f082b000 {
> > + compatible = "nuvoton,npcm750-ohci", "generic-ohci";
> > + reg = <0x0 0xf082b000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + sdhci: mmc@f0842000 {
> > + compatible = "nuvoton,npcm845-sdhci";
> > + reg = <0x0 0xf0842000 0x0 0x100>;
> > + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk NPCM8XX_CLK_AHB>;
> > + clock-names = "clk_mmc";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&mmc8_pins
> > + &mmc_pins>;
> > + status = "disabled";
> > + };
> > +
> > + pcie: pcie@e1000000 {
> > + compatible = "nuvoton,npcm845-pcie";
> > + device_type = "pci";
> > + reg = <0x0 0xE1000000 0x0 0x1000>,
> > + <0x0 0xE8000000 0x0 0x1000>;
> > + bus-range = <0x0 0xF>;
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + #interrupt-cells = <1>;
> > + ranges = <0x01000000 0 0xe9000000 0x0 0xe9000000 0 0x01000000
> > + 0x02000000 0 0xea000000 0x0 0xea000000 0 0x04000000>;
> > + resets = <&rstc 0x34 15>;
> > + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0 0 0 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
> > + nuvoton,sysgcr = <&gcr>;
> > + };
> > +
> > + fiu0: spi@fb000000 {
> > + compatible = "nuvoton,npcm845-fiu";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0xfb000000 0x0 0x1000>,
> > + <0x0 0x80000000 0x0 0x10000000>;
> > + reg-names = "control", "memory";
> > + clocks = <&clk NPCM8XX_CLK_SPI0>;
> > + clock-names = "clk_ahb";
> > + status = "disabled";
> > + };
> > +
> > + fiu1: spi@fb002000 {
> > + compatible = "nuvoton,npcm845-fiu";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0xfb002000 0x0 0x1000>,
> > + <0x0 0x90000000 0x0 0x4000000>;
> > + reg-names = "control", "memory";
> > + clocks = <&clk NPCM8XX_CLK_SPI1>;
> > + clock-names = "clk_spi1";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&spi1_pins>;
> > + status = "disabled";
> > + };
> > +
> > + fiu3: spi@c0000000 {
> > + compatible = "nuvoton,npcm845-fiu";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0xc0000000 0x0 0x1000>,
> > + <0x0 0xA0000000 0x0 0x20000000>;
> > + reg-names = "control", "memory";
> > + clocks = <&clk NPCM8XX_CLK_SPI3>;
> > + clock-names = "clk_spi3";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&spi3_pins>;
> > + status = "disabled";
> > + };
> > +
> > + fiux: spi@fb001000 {
> > + compatible = "nuvoton,npcm845-fiu";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0xfb001000 0x0 0x1000>,
> > + <0x0 0xf8000000 0x0 0x2000000>;
> > + reg-names = "control", "memory";
> > + clocks = <&clk NPCM8XX_CLK_SPIX>;
> > + clock-names = "clk_ahb";
> > + status = "disabled";
> > + };
> > +
> > + pcimbox: pcimbox@f0848000 {
> > + compatible = "nuvoton,npcm845-pci-mbox", "nuvoton,npcm750-pci-mbox",
> > + "simple-mfd", "syscon";
> > + reg = <0x0 0xf084C000 0x0 0x8
> > + 0x0 0xf0848000 0x0 0x3F00>;
> > + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + vcd: vcd@f0810000 {
> > + compatible = "nuvoton,npcm845-vcd";
> > + reg = <0x0 0xf0810000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> > + resets = <&rstc 0x24 14>;
> > + nuvoton,sysgcr = <&gcr>;
> > + nuvoton,sysgfxi = <&gfxi>;
> > + nuvoton,ece = <&ece>;
> > + status = "disabled";
> > + };
> > +
> > + ece: video-codec@f0820000 {
> > + compatible = "nuvoton,npcm845-ece";
> > + reg = <0x0 0xf0820000 0x0 0x2000>;
> > + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> > + resets = <&rstc 0x24 13>;
> > + status = "disabled";
> > + };
> > +
> > apb {
> > #address-cells = <1>;
> > #size-cells = <1>;
> > compatible = "simple-bus";
> > interrupt-parent = <&gic>;
> > ranges = <0x0 0x0 0xf0000000 0x00300000>,
> > - <0xfff00000 0x0 0xfff00000 0x00016000>;
> > + <0xfff00000 0x0 0xfff00000 0x00016000>,
> > + <0xf0800000 0x0 0xf0800000 0x00060000>;
> > +
> > + lpc_kcs: lpc_kcs@7000 {
> > + compatible = "nuvoton,npcm845-lpc-kcs",
> > + "simple-mfd", "syscon";
> > + reg = <0x7000 0x40>;
> > + reg-io-width = <1>;
> > +
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0x0 0x7000 0x40>;
> > +
> > + kcs1: kcs1@0 {
> > + compatible = "nuvoton,npcm845-kcs-bmc", "nuvoton,npcm750-kcs-bmc";
> > + reg = <0x0 0x40>;
> > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > + kcs_chan = <1>;
> > + status = "disabled";
> > + };
> >
> > - peci: peci-controller@100000 {
>
> No compatible? Did you test this with `make dtbs_check`?
Will check it again
>
> > + kcs2: kcs2@0 {
> > + compatible = "nuvoton,npcm845-kcs-bmc", "nuvoton,npcm750-kcs-bmc";
> > + reg = <0x0 0x40>;
> > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > + kcs_chan = <2>;
> > + status = "disabled";
> > + };
> > +
> > + kcs3: kcs3@0 {
> > + compatible = "nuvoton,npcm845-kcs-bmc", "nuvoton,npcm750-kcs-bmc";
> > + reg = <0x0 0x40>;
> > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > + kcs_chan = <3>;
> > + status = "disabled";
> > + };
> > + };
> > +
> > + lpc_host: lpc_host@7000 {
> > + compatible = "nuvoton,npcm845-lpc-host",
> > + "simple-mfd", "syscon";
> > + reg = <0x7000 0x60>;
> > +
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0x0 0x7000 0x60>;
> > +
> > + lpc_bpc: lpc_bpc@40 {
> > + compatible = "nuvoton,npcm845-lpc-bpc", "nuvoton,npcm750-lpc-bpc";
> > + reg = <0x40 0x20>;
> > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > + };
> > +
> > + espi: espi@9f000 {
> > + compatible = "nuvoton,npcm845-espi",
> > + "simple-mfd", "syscon";
> > + reg = <0x9f000 0x1000>;
> > + vw_gpio: vw_gpio {
> > + compatible = "nuvoton,npcm845-espi-vwgpio";
> > + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + status = "disabled";
> > + };
> > + };
> > +
> > + peci0: peci-controller@100000 {
>
> Didn't we define this one above? Should they be merged?
Yes, my mistake will remove it.
>
> > compatible = "nuvoton,npcm845-peci";
> > reg = <0x100000 0x1000>;
> > interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> > @@ -79,6 +363,48 @@ peci: peci-controller@100000 {
> > status = "disabled";
> > };
> >
> > + pspi: spi@201000 {
> > + compatible = "nuvoton,npcm845-pspi";
> > + reg = <0x201000 0x1000>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pspi_pins>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk NPCM8XX_CLK_APB5>;
> > + clock-names = "clk_apb5";
> > + resets = <&rstc 0x24 23>;
> > + status = "disabled";
> > + };
> > +
> > + jtm1: jtm@208000 {
> > + compatible = "nuvoton,npcm845-jtm";
> > + reg = <0x208000 0x1000>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&jm1_pins>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk NPCM8XX_CLK_APB5>;
> > + clock-names = "clk_apb5";
> > + resets = <&rstc 0x74 29>;
> > + status = "disabled";
> > + };
> > +
> > + jtm2: jtm@209000 {
> > + compatible = "nuvoton,npcm845-jtm";
> > + reg = <0x209000 0x1000>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&jm2_pins>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk NPCM8XX_CLK_APB5>;
> > + clock-names = "clk_apb5";
> > + resets = <&rstc 0x74 30>;
> > + status = "disabled";
> > + };
> > +
> > timer0: timer@8000 {
> > compatible = "nuvoton,npcm845-timer";
> > interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> > @@ -126,27 +452,50 @@ serial3: serial@3000 {
> > serial4: serial@4000 {
> > compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
> > reg = <0x4000 0x1000>;
> > - clocks = <&clk NPCM8XX_CLK_UART>;
> > + clocks = <&clk NPCM8XX_CLK_UART2>;
> > interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
> > reg-shift = <2>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&bu4_pins>;
> > status = "disabled";
> > };
> >
> > serial5: serial@5000 {
> > compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
> > reg = <0x5000 0x1000>;
> > - clocks = <&clk NPCM8XX_CLK_UART>;
> > + clocks = <&clk NPCM8XX_CLK_UART2>;
> > interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
> > reg-shift = <2>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&bu5_pins>;
> > status = "disabled";
> > };
> >
> > serial6: serial@6000 {
> > compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
> > reg = <0x6000 0x1000>;
> > - clocks = <&clk NPCM8XX_CLK_UART>;
> > + clocks = <&clk NPCM8XX_CLK_UART2>;
>
> The UART clock changes seem somewhat unrelated and probably deserve
> their own patch?
O.K.
>
> > interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
> > reg-shift = <2>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&bu6_pins>;
> > + status = "disabled";
>
> This too.
O.K.
>
> Andrew
>
Thanks,
Tomer
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [linux dev-6.6 v1 1/3] arm64: dts: nuvoton: npcm8xx: add reference 25m clock property
2024-07-15 9:16 ` Tomer Maimon
@ 2024-07-16 2:59 ` Andrew Jeffery
0 siblings, 0 replies; 8+ messages in thread
From: Andrew Jeffery @ 2024-07-16 2:59 UTC (permalink / raw)
To: Tomer Maimon; +Cc: openbmc, Joel Stanley
On Mon, 2024-07-15 at 12:16 +0300, Tomer Maimon wrote:
> Hi Andrew,
>
> Thanks for your comments.
>
> On Mon, 15 Jul 2024 at 09:05, Andrew Jeffery
> <andrew@codeconstruct.com.au> wrote:
> >
> > Hi Tomer,
> >
> > In the future, can you please send your series with a cover letter with
> > the patches threaded under it?
> Sure!
> >
> > If you're not already using it, b4 is a helpful tool for sending
> > patches:
> I wasn't aware to B$, I will try it, thanks :-)
> >
> > https://b4.docs.kernel.org/en/latest/
> >
> > I ask because it's not clear to me what the relationship of this series
> > is with respect to what's going on upstream. A cover letter is a great
> > place to explain whether the patches are:
> >
> > 1. A backport of those under review upstream
> > 2. A backport of patches already merged upstream
> > 3. Specific to the openbmc/linux tree and have no upstream equivalent
> >
> > In the case of 1 and 2 (which are the ideal cases), I really prefer you
> > include a link to the upstream equivalents. The link makes it easier
> > for me to gauge how mature the patches are.
> If I am sending one patch only do you like me to add under --- in the
> patch explanation as well?
Yeah, that would be great, if you're just sending the one patch rather
than a series. Thanks.
> >
> > Regarding the patch content (rather than process), while the patches
> > all touch the NPCM8XX devicetree, they don't seem to have a coherent
> > feel otherwise :(
> >
> > On Sun, 2024-07-14 at 18:26 +0300, Tomer Maimon wrote:
> > > The NPCM8XX clock driver uses a 25Mhz external clock, therefore adding
> > > clock property.
> > >
> > > The new required clock property does not break the NPCM8XX clock ABI
> > > since the NPCM8XX clock driver hasn't merged yet to the Linux vanilla.
> >
> > This is a statement with respect to upstream, but it seems we've
> > already applied some of the patches here, and so there's possibly a
> > concern?
> Unfortunately, the NPCM8XX clock driver has been removed in dev-6.6,
> so the OpenBMC Linux kernel is dev-6.6 is in the same state as the
> Linux kernel vanilla.
> BTW, I don't see any concern with the reference clock patch, but the
> DT maintainers asked me to mention it not cause any ABI issue.
Okay. I guess I should have poked at the (absence) of the driver.
> >
> > >
> > > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> > > ---
> > > arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 9 +++++----
> > > arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 7 +++++++
> > > 2 files changed, 12 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> > > index 91c1b5c4d635..9bd22f7d43f4 100644
> > > --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> > > +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> > > @@ -58,6 +58,7 @@ clk: clock-controller@f0801000 {
> > > compatible = "nuvoton,npcm845-clk";
> > > #clock-cells = <1>;
> > > reg = <0x0 0xf0801000 0x0 0x1000>;
> > > + clocks = <&refclk>;
> > > };
> > >
> > > apb {
> > > @@ -81,7 +82,7 @@ timer0: timer@8000 {
> > > compatible = "nuvoton,npcm845-timer";
> > > interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> > > reg = <0x8000 0x1C>;
> > > - clocks = <&clk NPCM8XX_CLK_REFCLK>;
> > > + clocks = <&refclk>;
> > > clock-names = "refclk";
> > > };
> > >
> > > @@ -153,7 +154,7 @@ watchdog0: watchdog@801c {
> > > interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
> > > reg = <0x801c 0x4>;
> > > status = "disabled";
> > > - clocks = <&clk NPCM8XX_CLK_REFCLK>;
> > > + clocks = <&refclk>;
> > > syscon = <&gcr>;
> > > };
> > >
> > > @@ -162,7 +163,7 @@ watchdog1: watchdog@901c {
> > > interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> > > reg = <0x901c 0x4>;
> > > status = "disabled";
> > > - clocks = <&clk NPCM8XX_CLK_REFCLK>;
> > > + clocks = <&refclk>;
> > > syscon = <&gcr>;
> > > };
> > >
> > > @@ -171,7 +172,7 @@ watchdog2: watchdog@a01c {
> > > interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> > > reg = <0xa01c 0x4>;
> > > status = "disabled";
> > > - clocks = <&clk NPCM8XX_CLK_REFCLK>;
> > > + clocks = <&refclk>;
> > > syscon = <&gcr>;
> > > };
> > > };
> > > diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> > > index a5ab2bc0f835..83c2f4e138e5 100644
> > > --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> > > +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> > > @@ -19,6 +19,13 @@ chosen {
> > > memory {
> > > reg = <0x0 0x0 0x0 0x40000000>;
> > > };
> > > +
> > > + refclk: refclk-25mhz {
> >
> > The node name should probably just be 'clock' according to the generic
> > node names recommendation?
> What do you mean? refclock? I am not sure, for example:
> https://elixir.bootlin.com/linux/v6.10-rc7/source/arch/arm64/boot/dts/freescale/imx8mq-evk.dts#L24
I meant the node name (refclk-25mhz), not the label (refclk), but
plenty of other devicetrees call it random things, so don't worry about
it.
> >
> > > + compatible = "fixed-clock";
> > > + clock-output-names = "ref";
> > > + clock-frequency = <25000000>;
> > > + #clock-cells = <0>;
> > > + };
> >
> > Defining this in the .dts but referencing the label inside the .dtsi
> > feels a bit off to me (as the .dtsi is no-longer self-contained). How
> > about we define the node in the .dtsi but override it in the .dts?
> I had a dissection about it with Krzysztof :-) I was told that since
> it is a reference clock on the board and not inside the SoC it should
> be defined in the DTS.
Hah, okay, I guess do whatever Krysztof recommends. If that's what
you've got, then it is what it is.
Andrew
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-07-16 3:00 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-07-14 15:26 [linux dev-6.6 v1 1/3] arm64: dts: nuvoton: npcm8xx: add reference 25m clock property Tomer Maimon
2024-07-14 15:26 ` [linux dev-6.6 v1 2/3] arm64: dts: nuvoton: npcm8xx: add pin and gpio controller nodes Tomer Maimon
2024-07-14 15:26 ` [linux dev-6.6 v1 3/3] arm64: dts: nuvoton: npcm8xx: add modules node Tomer Maimon
2024-07-15 8:27 ` Andrew Jeffery
2024-07-15 9:35 ` Tomer Maimon
2024-07-15 6:04 ` [linux dev-6.6 v1 1/3] arm64: dts: nuvoton: npcm8xx: add reference 25m clock property Andrew Jeffery
2024-07-15 9:16 ` Tomer Maimon
2024-07-16 2:59 ` Andrew Jeffery
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