* [PATCH v3 0/8] Add Starfive JH7110 Cadence USB driver
@ 2024-07-19 1:38 Minda Chen
2024-07-19 1:38 ` [PATCH v3 1/8] usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode() Minda Chen
` (7 more replies)
0 siblings, 8 replies; 19+ messages in thread
From: Minda Chen @ 2024-07-19 1:38 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
Add Starfive JH7110 Cadence USB driver and related PHY driver.
So the codes can be used in visionfive2 and star64 7110 board.
The driver is almost the same with kernel driver.
Test with Star64 JH7110 board USB 3.0 + USB 2.0 host.
The code can work.
- Star64 using USB 3.0 and USB 2.0 host must add below board dts setting.
(Vbus bin setting. If usb host in Other JH7110 vbus pin is not GPIO, don't
require to set this)
1. usb pin setting
usb_pins: usb0-0 {
driver-vbus-pin {
pinmux = <GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
2. related dts node setting(USB 3.0 host)
&pcie0 {
status = "disabled";
};
&pciephy0 {
starfive,sys-syscon = <&sys_syscon 0x18>;
starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
status = "okay";
};
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb_pins>;
status = "okay";
};
&usb_cdns3 {
phys = <&usbphy0>, <&pciephy0>;
phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
dr_mode = "host";
status = "okay";
};
- If other board is USB 2.0 host, Just set dr mode is OKay.
&usb_cdns3 {
dr_mode = "host";
status = "okay";
};
- previous version
v1: https://patchwork.ozlabs.org/project/uboot/cover/20240504150358.19600-1-minda.chen@starfivetech.com/
v2: https://patchwork.ozlabs.org/project/uboot/cover/20240704055014.55117-1-minda.chen@starfivetech.com/
- patch description.
patch1: Add set phy mode function in cdns3 core driver
which is used by Starfive JH7110.
patch2-3: USB and PCIe 2.0 (usb 3.0) PHY drivier
patch4: Cadence USB wrapper driver.
patch5: Add JH7110 USB default overcurrent pin.
patch6-8 dts, config and maintainers update.
- change:
v3:
- patch 1 Move the added code to cdns3_drd_update_mode().
- patch 1-4 correct the code format.(follow Rogers's comments.)
- patch 3 using regmap_field.
v2:
- patch 1 Move the added code to cdns3_core_init_role(). Must
set PHY mode before calling cdns3 role start function.
- patch 1-4 correct the code format.(follow Marek's comments.)
- patch 2 Add set 125M clock in PHY init function.
- Add new patch5.
Minda Chen (8):
usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode()
phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver
phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver
usb: cdns: starfive: Add cdns USB driver
pinctrl: starfive: Setup USB default disable overcurrent pin
configs: starfive: Add visionfive2 cadence USB configuration
dts: starfive: Add JH7110 Cadence USB dts node
MAINTAINERS: Update Starfive visionfive2 maintain files.
.../dts/jh7110-starfive-visionfive-2.dtsi | 5 +
arch/riscv/dts/jh7110.dtsi | 52 ++++
board/starfive/visionfive2/MAINTAINERS | 2 +
configs/starfive_visionfive2_defconfig | 9 +
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/starfive/Kconfig | 21 ++
drivers/phy/starfive/Makefile | 7 +
drivers/phy/starfive/phy-jh7110-pcie.c | 237 ++++++++++++++++++
drivers/phy/starfive/phy-jh7110-usb2.c | 135 ++++++++++
drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 11 +-
drivers/usb/cdns3/Kconfig | 7 +
drivers/usb/cdns3/Makefile | 2 +
drivers/usb/cdns3/cdns3-starfive.c | 191 ++++++++++++++
drivers/usb/cdns3/drd.c | 14 ++
15 files changed, 693 insertions(+), 2 deletions(-)
create mode 100644 drivers/phy/starfive/Kconfig
create mode 100644 drivers/phy/starfive/Makefile
create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
create mode 100644 drivers/phy/starfive/phy-jh7110-usb2.c
create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
base-commit: fd46ea0e701920eb205c2bce9d527bf0dec10b59
--
2.17.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 1/8] usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode()
2024-07-19 1:38 [PATCH v3 0/8] Add Starfive JH7110 Cadence USB driver Minda Chen
@ 2024-07-19 1:38 ` Minda Chen
2024-07-26 8:39 ` Minda Chen
2024-07-19 1:38 ` [PATCH v3 2/8] phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver Minda Chen
` (6 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Minda Chen @ 2024-07-19 1:38 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
USB PHY maybe need to set PHY mode in different USB
dr mode. So translate USB PHY mode to generic PHY mode
and call generic_phy_set_mode().
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
drivers/usb/cdns3/drd.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/usb/cdns3/drd.c b/drivers/usb/cdns3/drd.c
index 47874fec29..cbb1334234 100644
--- a/drivers/usb/cdns3/drd.c
+++ b/drivers/usb/cdns3/drd.c
@@ -217,15 +217,19 @@ static int cdns3_init_otg_mode(struct cdns3 *cdns)
int cdns3_drd_update_mode(struct cdns3 *cdns)
{
int ret = 0;
+ int mode;
switch (cdns->dr_mode) {
case USB_DR_MODE_PERIPHERAL:
+ mode = PHY_MODE_USB_DEVICE;
ret = cdns3_set_mode(cdns, USB_DR_MODE_PERIPHERAL);
break;
case USB_DR_MODE_HOST:
+ mode = PHY_MODE_USB_HOST;
ret = cdns3_set_mode(cdns, USB_DR_MODE_HOST);
break;
case USB_DR_MODE_OTG:
+ mode = PHY_MODE_USB_OTG;
ret = cdns3_init_otg_mode(cdns);
break;
default:
@@ -234,6 +238,16 @@ int cdns3_drd_update_mode(struct cdns3 *cdns)
return -EINVAL;
}
+ ret = generic_phy_set_mode(&cdns->usb2_phy, mode, 0);
+ if (ret) {
+ dev_err(cdns->dev, "Set usb 2.0 PHY mode failed %d\n", ret);
+ return ret;
+ }
+
+ ret = generic_phy_set_mode(&cdns->usb3_phy, mode, 0);
+ if (ret)
+ dev_err(cdns->dev, "Set usb 3.0 PHY mode failed %d\n", ret);
+
return ret;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 2/8] phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver
2024-07-19 1:38 [PATCH v3 0/8] Add Starfive JH7110 Cadence USB driver Minda Chen
2024-07-19 1:38 ` [PATCH v3 1/8] usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode() Minda Chen
@ 2024-07-19 1:38 ` Minda Chen
2024-07-19 1:38 ` [PATCH v3 3/8] phy: starfive: Add Starfive JH7110 PCIe " Minda Chen
` (5 subsequent siblings)
7 siblings, 0 replies; 19+ messages in thread
From: Minda Chen @ 2024-07-19 1:38 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
Add Starfive JH7110 USB 2.0 PHY driver, which is generic
PHY driver.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
---
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/starfive/Kconfig | 14 +++
drivers/phy/starfive/Makefile | 6 ++
drivers/phy/starfive/phy-jh7110-usb2.c | 135 +++++++++++++++++++++++++
5 files changed, 157 insertions(+)
create mode 100644 drivers/phy/starfive/Kconfig
create mode 100644 drivers/phy/starfive/Makefile
create mode 100644 drivers/phy/starfive/phy-jh7110-usb2.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 8f767877e7..0c4d63a01f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -307,5 +307,6 @@ source "drivers/phy/cadence/Kconfig"
source "drivers/phy/ti/Kconfig"
source "drivers/phy/qcom/Kconfig"
source "drivers/phy/renesas/Kconfig"
+source "drivers/phy/starfive/Kconfig"
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 7a2b764492..6ac867350c 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -44,3 +44,4 @@ obj-y += cadence/
obj-y += ti/
obj-y += qcom/
obj-y += renesas/
+obj-y += starfive/
diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
new file mode 100644
index 0000000000..f28529d1f9
--- /dev/null
+++ b/drivers/phy/starfive/Kconfig
@@ -0,0 +1,14 @@
+#
+# PHY drivers for Starfive platforms
+#
+
+menu "Starfive PHY driver"
+
+config PHY_STARFIVE_JH7110_USB2
+ bool "Starfive JH7110 USB 2.0 PHY driver"
+ select PHY
+ help
+ Enable this to support the Starfive JH7110 USB 2.0 PHY.
+ Generic PHY driver JH7110 USB 2.0.
+
+endmenu
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
new file mode 100644
index 0000000000..a405a75e34
--- /dev/null
+++ b/drivers/phy/starfive/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Starfive
+#
+
+obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o
diff --git a/drivers/phy/starfive/phy-jh7110-usb2.c b/drivers/phy/starfive/phy-jh7110-usb2.c
new file mode 100644
index 0000000000..d48c9f8a74
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-usb2.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 USB 2.0 PHY driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Minda Chen <minda.chen@starfivetech.com>
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <soc.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+#define USB_LS_KEEPALIVE_OFF 0x4
+#define USB_LS_KEEPALIVE_ENABLE BIT(4)
+#define USB_PHY_CLK_RATE 125000000
+
+struct jh7110_usb2_phy {
+ struct phy *phy;
+ void __iomem *regs;
+ struct clk *usb_125m_clk;
+ struct clk *app_125m;
+ enum phy_mode mode;
+};
+
+static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool set)
+{
+ /* Host mode enable the LS speed keep-alive signal */
+ if (set)
+ clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
+ USB_LS_KEEPALIVE_ENABLE,
+ USB_LS_KEEPALIVE_ENABLE);
+ else
+ clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
+ USB_LS_KEEPALIVE_ENABLE, 0);
+}
+
+static int usb2_phy_set_mode(struct phy *_phy,
+ enum phy_mode mode, int submode)
+{
+ struct udevice *dev = _phy->dev;
+ struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+
+ if (mode == phy->mode)
+ return 0;
+
+ switch (mode) {
+ case PHY_MODE_USB_HOST:
+ case PHY_MODE_USB_DEVICE:
+ case PHY_MODE_USB_OTG:
+ dev_dbg(dev, "Changing phy to %d\n", mode);
+ phy->mode = mode;
+ usb2_set_ls_keepalive(phy, (mode != PHY_MODE_USB_DEVICE));
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int jh7110_usb2_phy_init(struct phy *_phy)
+{
+ struct udevice *dev = _phy->dev;
+ struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+ int ret;
+
+ ret = clk_set_rate(phy->usb_125m_clk, USB_PHY_CLK_RATE);
+ if (ret < 0) {
+ dev_err(dev, "Failed to set 125m clock\n");
+ return ret;
+ }
+
+ return clk_prepare_enable(phy->app_125m);
+}
+
+static int jh7110_usb2_phy_exit(struct phy *_phy)
+{
+ struct udevice *dev = _phy->dev;
+ struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+
+ clk_disable_unprepare(phy->app_125m);
+
+ return 0;
+}
+
+struct phy_ops jh7110_usb2_phy_ops = {
+ .init = jh7110_usb2_phy_init,
+ .exit = jh7110_usb2_phy_exit,
+ .set_mode = usb2_phy_set_mode,
+};
+
+int jh7110_usb2_phy_probe(struct udevice *dev)
+{
+ struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+
+ phy->regs = dev_read_addr_ptr(dev);
+ if (!phy->regs)
+ return -EINVAL;
+
+ phy->usb_125m_clk = devm_clk_get(dev, "125m");
+ if (IS_ERR(phy->usb_125m_clk)) {
+ dev_err(dev, "Failed to get 125m clock\n");
+ return PTR_ERR(phy->usb_125m_clk);
+ }
+
+ phy->app_125m = devm_clk_get(dev, "app_125m");
+ if (IS_ERR(phy->app_125m)) {
+ dev_err(dev, "Failed to get app 125m clock\n");
+ return PTR_ERR(phy->app_125m);
+ }
+
+ return 0;
+}
+
+static const struct udevice_id jh7110_usb2_phy[] = {
+ { .compatible = "starfive,jh7110-usb-phy"},
+ {},
+};
+
+U_BOOT_DRIVER(jh7110_usb2_phy) = {
+ .name = "jh7110_usb2_phy",
+ .id = UCLASS_PHY,
+ .of_match = jh7110_usb2_phy,
+ .probe = jh7110_usb2_phy_probe,
+ .ops = &jh7110_usb2_phy_ops,
+ .priv_auto = sizeof(struct jh7110_usb2_phy),
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 3/8] phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver
2024-07-19 1:38 [PATCH v3 0/8] Add Starfive JH7110 Cadence USB driver Minda Chen
2024-07-19 1:38 ` [PATCH v3 1/8] usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode() Minda Chen
2024-07-19 1:38 ` [PATCH v3 2/8] phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver Minda Chen
@ 2024-07-19 1:38 ` Minda Chen
2024-07-19 1:38 ` [PATCH v3 4/8] usb: cdns: starfive: Add cdns USB driver Minda Chen
` (4 subsequent siblings)
7 siblings, 0 replies; 19+ messages in thread
From: Minda Chen @ 2024-07-19 1:38 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
Add Starfive JH7110 PCIe 2.0 PHY driver, which is generic
PHY driver and can be used as USB 3.0 driver.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
drivers/phy/starfive/Kconfig | 7 +
drivers/phy/starfive/Makefile | 1 +
drivers/phy/starfive/phy-jh7110-pcie.c | 237 +++++++++++++++++++++++++
3 files changed, 245 insertions(+)
create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
index f28529d1f9..0843070b74 100644
--- a/drivers/phy/starfive/Kconfig
+++ b/drivers/phy/starfive/Kconfig
@@ -4,6 +4,13 @@
menu "Starfive PHY driver"
+config PHY_STARFIVE_JH7110_PCIE
+ bool "Starfive JH7110 PCIe 2.0 PHY driver"
+ select PHY
+ help
+ Enable this to support the Starfive JH7110 PCIE 2.0/USB 3.0 PHY.
+ Generic PHY driver JH7110 USB 3.0/ PCIe 2.0.
+
config PHY_STARFIVE_JH7110_USB2
bool "Starfive JH7110 USB 2.0 PHY driver"
select PHY
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
index a405a75e34..82f25aa21b 100644
--- a/drivers/phy/starfive/Makefile
+++ b/drivers/phy/starfive/Makefile
@@ -3,4 +3,5 @@
# Copyright (C) 2023 Starfive
#
+obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o
obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o
diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/phy-jh7110-pcie.c
new file mode 100644
index 0000000000..53bfc4839e
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-pcie.c
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 PCIe 2.0 PHY driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Minda Chen <minda.chen@starfivetech.com>
+ */
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <soc.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+#define PCIE_KVCO_LEVEL_OFF 0x28
+#define PCIE_USB3_PHY_PLL_CTL_OFF 0x7c
+#define PCIE_USB3_PHY_SS_MODE BIT(4)
+#define PCIE_KVCO_TUNE_SIGNAL_OFF 0x80
+#define PHY_KVCO_FINE_TUNE_LEVEL 0x91
+#define PHY_KVCO_FINE_TUNE_SIGNALS 0xc
+
+#define PCIE_USB3_PHY_MODE 0x1
+#define PCIE_BUS_WIDTH 0x2
+#define PCIE_USB3_PHY_ENABLE 0x1
+#define PCIE_USB3_PHY_SPLIT 0x1
+
+struct jh7110_pcie_phy {
+ struct phy *phy;
+ struct regmap *stg_syscon;
+ struct regmap *sys_syscon;
+ void __iomem *regs;
+ struct regmap_field *phy_mode;
+ struct regmap_field *bus_width;
+ struct regmap_field *usb3_phy_en;
+ struct regmap_field *usb_split;
+ enum phy_mode mode;
+};
+
+static int phy_pcie_mode_set(struct jh7110_pcie_phy *data, bool usb_mode)
+{
+ unsigned int phy_mode, width, usb3_phy, ss_mode, split;
+
+ /* default is PCIe mode */
+ if (!data->stg_syscon || !data->sys_syscon) {
+ if (usb_mode) {
+ dev_err(data->phy->dev, "doesn't support usb3 mode\n");
+ return -EINVAL;
+ }
+ return 0;
+ }
+
+ if (usb_mode) {
+ phy_mode = PCIE_USB3_PHY_MODE;
+ width = 0;
+ usb3_phy = PCIE_USB3_PHY_ENABLE;
+ ss_mode = PCIE_USB3_PHY_SS_MODE;
+ split = 0;
+ } else {
+ phy_mode = 0;
+ width = PCIE_BUS_WIDTH;
+ usb3_phy = 0;
+ ss_mode = 0;
+ split = PCIE_USB3_PHY_SPLIT;
+ }
+
+ regmap_field_write(data->phy_mode, phy_mode);
+ regmap_field_write(data->bus_width, width);
+ regmap_field_write(data->usb3_phy_en, usb3_phy);
+ clrsetbits_le32(data->regs + PCIE_USB3_PHY_PLL_CTL_OFF,
+ PCIE_USB3_PHY_SS_MODE, ss_mode);
+ regmap_field_write(data->usb_split, split);
+
+ return 0;
+}
+
+static void phy_kvco_gain_set(struct jh7110_pcie_phy *phy)
+{
+ /* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */
+ writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF);
+ writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF);
+}
+
+static int jh7110_pcie_phy_set_mode(struct phy *_phy,
+ enum phy_mode mode, int submode)
+{
+ struct udevice *dev = _phy->dev;
+ struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+ int ret;
+
+ if (mode == phy->mode)
+ return 0;
+
+ switch (mode) {
+ case PHY_MODE_USB_HOST:
+ case PHY_MODE_USB_DEVICE:
+ case PHY_MODE_USB_OTG:
+ ret = phy_pcie_mode_set(phy, 1);
+ if (ret)
+ return ret;
+ break;
+ case PHY_MODE_PCIE:
+ phy_pcie_mode_set(phy, 0);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ dev_dbg(_phy->dev, "Changing phy mode to %d\n", mode);
+ phy->mode = mode;
+
+ return 0;
+}
+
+static const struct phy_ops jh7110_pcie_phy_ops = {
+ .set_mode = jh7110_pcie_phy_set_mode,
+};
+
+static int phy_stg_regfield_init(struct udevice *dev, int mode, int usb3)
+{
+ struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+ struct reg_field phy_mode = REG_FIELD(mode, 20, 21);
+ struct reg_field bus_width = REG_FIELD(usb3, 2, 3);
+ struct reg_field usb3_phy_en = REG_FIELD(usb3, 4, 4);
+
+ phy->phy_mode = devm_regmap_field_alloc(dev, phy->stg_syscon, phy_mode);
+ if (IS_ERR(phy->phy_mode)) {
+ dev_err(dev, "PHY mode reg field init failed\n");
+ return PTR_ERR(phy->phy_mode);
+ }
+
+ phy->bus_width = devm_regmap_field_alloc(dev, phy->stg_syscon, bus_width);
+ if (IS_ERR(phy->bus_width)) {
+ dev_err(dev, "PHY bus width reg field init failed\n");
+ return PTR_ERR(phy->bus_width);
+ }
+
+ phy->usb3_phy_en = devm_regmap_field_alloc(dev, phy->stg_syscon, usb3_phy_en);
+ if (IS_ERR(phy->usb3_phy_en)) {
+ dev_err(dev, "USB3 PHY enable field init failed\n");
+ return PTR_ERR(phy->bus_width);
+ }
+
+ return 0;
+}
+
+static int phy_sys_regfield_init(struct udevice *dev, int split)
+{
+ struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+ struct reg_field usb_split = REG_FIELD(split, 17, 17);
+
+ phy->usb_split = devm_regmap_field_alloc(dev, phy->sys_syscon, usb_split);
+ if (IS_ERR(phy->usb_split)) {
+ dev_err(dev, "USB split field init failed\n");
+ return PTR_ERR(phy->usb_split);
+ }
+
+ return 0;
+}
+
+static int starfive_pcie_phy_get_syscon(struct udevice *dev)
+{
+ struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+ struct ofnode_phandle_args sys_phandle, stg_phandle;
+ int ret;
+
+ /* get corresponding syscon phandle */
+ ret = dev_read_phandle_with_args(dev, "starfive,sys-syscon", NULL, 1, 0,
+ &sys_phandle);
+
+ if (ret < 0) {
+ dev_err(dev, "Can't get sys cfg phandle: %d\n", ret);
+ return ret;
+ }
+
+ ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 2, 0,
+ &stg_phandle);
+
+ if (ret < 0) {
+ dev_err(dev, "Can't get stg cfg phandle: %d\n", ret);
+ return ret;
+ }
+
+ phy->sys_syscon = syscon_node_to_regmap(sys_phandle.node);
+ /* get syscon register offset */
+ if (!IS_ERR(phy->sys_syscon)) {
+ ret = phy_sys_regfield_init(dev, stg_phandle.args[0]);
+ if (ret)
+ return ret;
+ } else {
+ phy->sys_syscon = NULL;
+ }
+
+ phy->stg_syscon = syscon_node_to_regmap(stg_phandle.node);
+ if (!IS_ERR(phy->stg_syscon))
+ return phy_stg_regfield_init(dev, stg_phandle.args[0],
+ stg_phandle.args[1]);
+ else
+ phy->stg_syscon = NULL;
+
+ return 0;
+}
+
+int jh7110_pcie_phy_probe(struct udevice *dev)
+{
+ struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+ int rc;
+
+ phy->regs = dev_read_addr_ptr(dev);
+ if (!phy->regs)
+ return -EINVAL;
+
+ rc = starfive_pcie_phy_get_syscon(dev);
+ if (rc)
+ return rc;
+
+ phy_kvco_gain_set(phy);
+
+ return 0;
+}
+
+static const struct udevice_id jh7110_pcie_phy[] = {
+ { .compatible = "starfive,jh7110-pcie-phy"},
+ {},
+};
+
+U_BOOT_DRIVER(jh7110_pcie_phy) = {
+ .name = "jh7110_pcie_phy",
+ .id = UCLASS_PHY,
+ .of_match = jh7110_pcie_phy,
+ .probe = jh7110_pcie_phy_probe,
+ .ops = &jh7110_pcie_phy_ops,
+ .priv_auto = sizeof(struct jh7110_pcie_phy),
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 4/8] usb: cdns: starfive: Add cdns USB driver
2024-07-19 1:38 [PATCH v3 0/8] Add Starfive JH7110 Cadence USB driver Minda Chen
` (2 preceding siblings ...)
2024-07-19 1:38 ` [PATCH v3 3/8] phy: starfive: Add Starfive JH7110 PCIe " Minda Chen
@ 2024-07-19 1:38 ` Minda Chen
2024-07-19 1:38 ` [PATCH v3 5/8] pinctrl: starfive: Setup USB default disable overcurrent pin Minda Chen
` (3 subsequent siblings)
7 siblings, 0 replies; 19+ messages in thread
From: Minda Chen @ 2024-07-19 1:38 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
Add cdns USB3 wrapper driver.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
drivers/usb/cdns3/Kconfig | 7 ++
drivers/usb/cdns3/Makefile | 2 +
drivers/usb/cdns3/cdns3-starfive.c | 191 +++++++++++++++++++++++++++++
3 files changed, 200 insertions(+)
create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
index 35b61497d9..f8f363982b 100644
--- a/drivers/usb/cdns3/Kconfig
+++ b/drivers/usb/cdns3/Kconfig
@@ -55,4 +55,11 @@ config USB_CDNS3_TI
help
Say 'Y' here if you are building for Texas Instruments
platforms that contain Cadence USB3 controller core. E.g.: J721e.
+
+config USB_CDNS3_STARFIVE
+ tristate "Cadence USB3 support on Starfive platforms"
+ default USB_CDNS3
+ help
+ Say 'Y' here if you are building for Starfive platforms
+ that contain Cadence USB3 controller core. E.g.: JH7110.
endif
diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
index 18d7190755..03d1eadb2f 100644
--- a/drivers/usb/cdns3/Makefile
+++ b/drivers/usb/cdns3/Makefile
@@ -9,3 +9,5 @@ cdns3-$(CONFIG_$(SPL_)USB_CDNS3_GADGET) += gadget.o ep0.o
cdns3-$(CONFIG_$(SPL_)USB_CDNS3_HOST) += host.o
obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o
+
+obj-$(CONFIG_USB_CDNS3_STARFIVE) += cdns3-starfive.o
diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c
new file mode 100644
index 0000000000..839d72e4e1
--- /dev/null
+++ b/drivers/usb/cdns3/cdns3-starfive.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Minda Chen <minda.chen@starfivetech.com>
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/usb/otg.h>
+#include <reset.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <malloc.h>
+
+#include "core.h"
+
+#define USB_STRAP_HOST BIT(17)
+#define USB_STRAP_DEVICE BIT(18)
+#define USB_STRAP_MASK GENMASK(18, 16)
+
+#define USB_SUSPENDM_HOST BIT(19)
+#define USB_SUSPENDM_MASK BIT(19)
+
+#define USB_MISC_CFG_MASK GENMASK(23, 20)
+#define USB_SUSPENDM_BYPS BIT(20)
+#define USB_PLL_EN BIT(22)
+#define USB_REFCLK_MODE BIT(23)
+
+struct cdns_starfive {
+ struct udevice *dev;
+ struct regmap *stg_syscon;
+ struct reset_ctl_bulk resets;
+ struct clk_bulk clks;
+ u32 stg_usb_mode;
+ enum usb_dr_mode mode;
+};
+
+static void cdns_mode_init(struct cdns_starfive *data, enum usb_dr_mode mode)
+{
+ unsigned int strap, suspendm;
+
+ regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+ USB_MISC_CFG_MASK,
+ USB_SUSPENDM_BYPS | USB_PLL_EN | USB_REFCLK_MODE);
+
+ switch (mode) {
+ case USB_DR_MODE_HOST:
+ strap = USB_STRAP_HOST;
+ suspendm = USB_SUSPENDM_HOST;
+ break;
+
+ case USB_DR_MODE_PERIPHERAL:
+ strap = USB_STRAP_DEVICE;
+ suspendm = 0;
+ break;
+ default:
+ return;
+ }
+
+ regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+ USB_STRAP_MASK, strap);
+ regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+ USB_SUSPENDM_MASK, suspendm);
+}
+
+static void cdns_clk_rst_deinit(struct cdns_starfive *data)
+{
+ reset_assert_bulk(&data->resets);
+ clk_disable_bulk(&data->clks);
+}
+
+static int cdns_clk_rst_init(struct cdns_starfive *data)
+{
+ int ret;
+
+ ret = clk_get_bulk(data->dev, &data->clks);
+ if (ret)
+ return ret;
+
+ ret = reset_get_bulk(data->dev, &data->resets);
+ if (ret)
+ goto err_clk;
+
+ ret = clk_enable_bulk(&data->clks);
+ if (ret) {
+ dev_err(data->dev, "clk enable failed: %d\n", ret);
+ goto err_en_clk;
+ }
+
+ ret = reset_deassert_bulk(&data->resets);
+ if (ret) {
+ dev_err(data->dev, "reset deassert failed: %d\n", ret);
+ goto err_reset;
+ }
+
+ return 0;
+
+err_reset:
+ clk_disable_bulk(&data->clks);
+err_en_clk:
+ reset_release_bulk(&data->resets);
+err_clk:
+ clk_release_bulk(&data->clks);
+
+ return ret;
+}
+
+static int cdns_starfive_get_syscon(struct cdns_starfive *data)
+{
+ struct ofnode_phandle_args phandle;
+ int ret;
+
+ ret = dev_read_phandle_with_args(data->dev, "starfive,stg-syscon", NULL, 1, 0,
+ &phandle);
+ if (ret < 0) {
+ dev_err(data->dev, "Can't get stg cfg phandle: %d\n", ret);
+ return ret;
+ }
+
+ data->stg_syscon = syscon_node_to_regmap(phandle.node);
+ if (IS_ERR(data->stg_syscon)) {
+ dev_err(data->dev, "fail to get regmap: %d\n", (int)PTR_ERR(data->stg_syscon));
+ return PTR_ERR(data->stg_syscon);
+ }
+
+ data->stg_usb_mode = phandle.args[0];
+
+ return 0;
+}
+
+static int cdns_starfive_probe(struct udevice *dev)
+{
+ struct cdns_starfive *data = dev_get_plat(dev);
+ enum usb_dr_mode dr_mode;
+ ofnode node;
+ int ret;
+
+ data->dev = dev;
+
+ ret = cdns_starfive_get_syscon(data);
+ if (ret)
+ return ret;
+
+ node = ofnode_by_compatible(dev_ofnode(dev), "cdns,usb3");
+ if (!ofnode_valid(node)) {
+ dev_err(dev, "failed to get usb node\n");
+ return -ENODEV;
+ }
+
+ dr_mode = usb_get_dr_mode(node);
+
+ data->mode = dr_mode;
+ ret = cdns_clk_rst_init(data);
+ if (ret) {
+ dev_err(data->dev, "clk reset failed: %d\n", ret);
+ return ret;
+ }
+ cdns_mode_init(data, dr_mode);
+
+ return 0;
+}
+
+static int cdns_starfive_remove(struct udevice *dev)
+{
+ struct cdns_starfive *data = dev_get_plat(dev);
+
+ cdns_clk_rst_deinit(data);
+ return 0;
+}
+
+static const struct udevice_id cdns_starfive_of_match[] = {
+ { .compatible = "starfive,jh7110-usb", },
+ {},
+};
+
+U_BOOT_DRIVER(cdns_starfive) = {
+ .name = "cdns-starfive",
+ .id = UCLASS_NOP,
+ .of_match = cdns_starfive_of_match,
+ .bind = cdns3_bind,
+ .probe = cdns_starfive_probe,
+ .remove = cdns_starfive_remove,
+ .plat_auto = sizeof(struct cdns_starfive),
+ .flags = DM_FLAG_OS_PREPARE,
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 5/8] pinctrl: starfive: Setup USB default disable overcurrent pin
2024-07-19 1:38 [PATCH v3 0/8] Add Starfive JH7110 Cadence USB driver Minda Chen
` (3 preceding siblings ...)
2024-07-19 1:38 ` [PATCH v3 4/8] usb: cdns: starfive: Add cdns USB driver Minda Chen
@ 2024-07-19 1:38 ` Minda Chen
2024-07-26 8:35 ` Minda Chen
2024-07-19 1:38 ` [PATCH v3 6/8] configs: starfive: Add visionfive2 cadence USB configuration Minda Chen
` (2 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Minda Chen @ 2024-07-19 1:38 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
For some JH7110 boards, USB host overcurent pin is not reserved,
To make USB host work, overcurrent pin must be disabled. So set the
pin default disabled.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
index dafba65eae..1102985ab9 100644
--- a/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
+++ b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
@@ -378,8 +378,15 @@ static int jh7110_sys_pinctrl_probe(struct udevice *dev)
{
struct starfive_pinctrl_soc_info *info =
(struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev);
-
- return starfive_pinctrl_probe(dev, info);
+ struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = starfive_pinctrl_probe(dev, info);
+ /* Set default the usb controller overcurrent signal. */
+ if (!ret)
+ clrsetbits_le32(priv->base + JH7110_SYS_GPI,
+ GENMASK(22, 16), BIT(16));
+ return ret;
}
static const struct udevice_id jh7110_sys_pinctrl_ids[] = {
--
2.17.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 6/8] configs: starfive: Add visionfive2 cadence USB configuration
2024-07-19 1:38 [PATCH v3 0/8] Add Starfive JH7110 Cadence USB driver Minda Chen
` (4 preceding siblings ...)
2024-07-19 1:38 ` [PATCH v3 5/8] pinctrl: starfive: Setup USB default disable overcurrent pin Minda Chen
@ 2024-07-19 1:38 ` Minda Chen
2024-07-19 1:38 ` [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node Minda Chen
2024-07-19 1:38 ` [PATCH v3 8/8] MAINTAINERS: Update Starfive visionfive2 maintain files Minda Chen
7 siblings, 0 replies; 19+ messages in thread
From: Minda Chen @ 2024-07-19 1:38 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
Add cadence USB confiuration.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
configs/starfive_visionfive2_defconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 174ac24dc7..35137eec59 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -69,6 +69,7 @@ CONFIG_SYS_EEPROM_SIZE=512
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_BIND is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
@@ -112,6 +113,8 @@ CONFIG_NVME_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCIE_STARFIVE_JH7110=y
+CONFIG_PHY_STARFIVE_JH7110_PCIE=y
+CONFIG_PHY_STARFIVE_JH7110_USB2=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
@@ -127,13 +130,19 @@ CONFIG_CADENCE_QSPI=y
CONFIG_SYSRESET=y
CONFIG_TIMER_EARLY=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_PCI=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+# CONFIG_USB_CDNS3_TI is not set
CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
# CONFIG_WATCHDOG is not set
# CONFIG_WATCHDOG_AUTOSTART is not set
CONFIG_WDT=y
--
2.17.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node
2024-07-19 1:38 [PATCH v3 0/8] Add Starfive JH7110 Cadence USB driver Minda Chen
` (5 preceding siblings ...)
2024-07-19 1:38 ` [PATCH v3 6/8] configs: starfive: Add visionfive2 cadence USB configuration Minda Chen
@ 2024-07-19 1:38 ` Minda Chen
2024-07-21 1:47 ` E Shattow
2024-07-19 1:38 ` [PATCH v3 8/8] MAINTAINERS: Update Starfive visionfive2 maintain files Minda Chen
7 siblings, 1 reply; 19+ messages in thread
From: Minda Chen @ 2024-07-19 1:38 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
Add Jh7110 Cadence USB dts node, Visionfive2 default setting
is USB 2.0 device.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
.../dts/jh7110-starfive-visionfive-2.dtsi | 5 ++
arch/riscv/dts/jh7110.dtsi | 52 +++++++++++++++++++
2 files changed, 57 insertions(+)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index e11babc1cd..44785bbee3 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -378,3 +378,8 @@
};
};
};
+
+&usb_cdns3 {
+ dr_mode = "peripheral";
+ status = "okay";
+};
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 2cdc683d49..1eee924e1d 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -371,6 +371,58 @@
status = "disabled";
};
+ usb0: usb@10100000 {
+ compatible = "starfive,jh7110-usb";
+ ranges = <0x0 0x0 0x10100000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ starfive,stg-syscon = <&stg_syscon 0x4>;
+ clocks = <&stgcrg JH7110_STGCLK_USB_LPM>,
+ <&stgcrg JH7110_STGCLK_USB_STB>,
+ <&stgcrg JH7110_STGCLK_USB_APB>,
+ <&stgcrg JH7110_STGCLK_USB_AXI>,
+ <&stgcrg JH7110_STGCLK_USB_UTMI_APB>;
+ clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
+ resets = <&stgcrg JH7110_STGRST_USB_PWRUP>,
+ <&stgcrg JH7110_STGRST_USB_APB>,
+ <&stgcrg JH7110_STGRST_USB_AXI>,
+ <&stgcrg JH7110_STGRST_USB_UTMI_APB>;
+ reset-names = "pwrup", "apb", "axi", "utmi_apb";
+
+ usb_cdns3: usb@0 {
+ compatible = "cdns,usb3";
+ reg = <0x0 0x10000>,
+ <0x10000 0x10000>,
+ <0x20000 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <100>, <108>, <110>;
+ interrupt-names = "host", "peripheral", "otg";
+ phys = <&usbphy0>;
+ phy-names = "cdns3,usb2-phy";
+ };
+ };
+
+ usbphy0: phy@10200000 {
+ compatible = "starfive,jh7110-usb-phy";
+ reg = <0x0 0x10200000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
+ <&stgcrg JH7110_STGCLK_USB_APP_125>;
+ clock-names = "125m", "app_125m";
+ #phy-cells = <0>;
+ };
+
+ pciephy0: phy@10210000 {
+ compatible = "starfive,jh7110-pcie-phy";
+ reg = <0x0 0x10210000 0x0 0x10000>;
+ #phy-cells = <0>;
+ };
+
+ pciephy1: phy@10220000 {
+ compatible = "starfive,jh7110-pcie-phy";
+ reg = <0x0 0x10220000 0x0 0x10000>;
+ #phy-cells = <0>;
+ };
+
stgcrg: clock-controller@10230000 {
compatible = "starfive,jh7110-stgcrg";
reg = <0x0 0x10230000 0x0 0x10000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 8/8] MAINTAINERS: Update Starfive visionfive2 maintain files.
2024-07-19 1:38 [PATCH v3 0/8] Add Starfive JH7110 Cadence USB driver Minda Chen
` (6 preceding siblings ...)
2024-07-19 1:38 ` [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node Minda Chen
@ 2024-07-19 1:38 ` Minda Chen
7 siblings, 0 replies; 19+ messages in thread
From: Minda Chen @ 2024-07-19 1:38 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang
Cc: u-boot, Heinrich Schuchardt, Simon Glass, E Shattow, Minda Chen
Add USB related files to Starfive visionfive2 MAINTAINERS.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Marek Vasut <marex@denx.de>
---
board/starfive/visionfive2/MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS
index d7f638f9b4..1faf83f581 100644
--- a/board/starfive/visionfive2/MAINTAINERS
+++ b/board/starfive/visionfive2/MAINTAINERS
@@ -6,3 +6,5 @@ F: board/starfive/visionfive2/
F: include/configs/starfive-visionfive2.h
F: configs/starfive_visionfive2_defconfig
F: drivers/pci/pcie_starfive_jh7110.c
+F: drivers/phy/starfive/
+F: drivers/usb/cdns3/cdns3-starfive.c
--
2.17.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node
2024-07-19 1:38 ` [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node Minda Chen
@ 2024-07-21 1:47 ` E Shattow
2024-07-21 18:27 ` E Shattow
0 siblings, 1 reply; 19+ messages in thread
From: E Shattow @ 2024-07-21 1:47 UTC (permalink / raw)
To: Minda Chen
Cc: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang, u-boot, Heinrich Schuchardt,
Simon Glass
Hi, I am testing on Milk-V Mars CM Lite, and I add to these devicetree
changes at runtime from board/starfive/visionfive2/spl.c
On Thu, Jul 18, 2024 at 6:38 PM Minda Chen <minda.chen@starfivetech.com> wrote:
>
> Add Jh7110 Cadence USB dts node, Visionfive2 default setting
> is USB 2.0 device.
>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
> .../dts/jh7110-starfive-visionfive-2.dtsi | 5 ++
> arch/riscv/dts/jh7110.dtsi | 52 +++++++++++++++++++
> 2 files changed, 57 insertions(+)
>
> diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> index e11babc1cd..44785bbee3 100644
> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> @@ -378,3 +378,8 @@
> };
> };
> };
> +
> +&usb_cdns3 {
> + dr_mode = "peripheral";
> + status = "okay";
> +};
> diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
> index 2cdc683d49..1eee924e1d 100644
> --- a/arch/riscv/dts/jh7110.dtsi
> +++ b/arch/riscv/dts/jh7110.dtsi
> @@ -371,6 +371,58 @@
> status = "disabled";
> };
>
> + usb0: usb@10100000 {
> + compatible = "starfive,jh7110-usb";
> + ranges = <0x0 0x0 0x10100000 0x100000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + starfive,stg-syscon = <&stg_syscon 0x4>;
> + clocks = <&stgcrg JH7110_STGCLK_USB_LPM>,
> + <&stgcrg JH7110_STGCLK_USB_STB>,
> + <&stgcrg JH7110_STGCLK_USB_APB>,
> + <&stgcrg JH7110_STGCLK_USB_AXI>,
> + <&stgcrg JH7110_STGCLK_USB_UTMI_APB>;
> + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
> + resets = <&stgcrg JH7110_STGRST_USB_PWRUP>,
> + <&stgcrg JH7110_STGRST_USB_APB>,
> + <&stgcrg JH7110_STGRST_USB_AXI>,
> + <&stgcrg JH7110_STGRST_USB_UTMI_APB>;
> + reset-names = "pwrup", "apb", "axi", "utmi_apb";
> +
> + usb_cdns3: usb@0 {
> + compatible = "cdns,usb3";
> + reg = <0x0 0x10000>,
> + <0x10000 0x10000>,
> + <0x20000 0x10000>;
> + reg-names = "otg", "xhci", "dev";
> + interrupts = <100>, <108>, <110>;
> + interrupt-names = "host", "peripheral", "otg";
> + phys = <&usbphy0>;
> + phy-names = "cdns3,usb2-phy";
> + };
> + };
> +
> + usbphy0: phy@10200000 {
> + compatible = "starfive,jh7110-usb-phy";
> + reg = <0x0 0x10200000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
> + <&stgcrg JH7110_STGCLK_USB_APP_125>;
> + clock-names = "125m", "app_125m";
> + #phy-cells = <0>;
> + };
> +
> + pciephy0: phy@10210000 {
> + compatible = "starfive,jh7110-pcie-phy";
> + reg = <0x0 0x10210000 0x0 0x10000>;
> + #phy-cells = <0>;
> + };
> +
> + pciephy1: phy@10220000 {
> + compatible = "starfive,jh7110-pcie-phy";
> + reg = <0x0 0x10220000 0x0 0x10000>;
> + #phy-cells = <0>;
> + };
> +
> stgcrg: clock-controller@10230000 {
> compatible = "starfive,jh7110-stgcrg";
> reg = <0x0 0x10230000 0x0 0x10000>;
> --
> 2.17.1
>
Access fault
starting USB...
Bus usb@0: cdns-usb3-host usb@0: set 1 has failed, back to 0
scanning bus usb@0 for devices... Unhandled exception: Load access fault
EPC: 00000000fff85ce2 RA: 00000000fff85cdc TVAL: 0000000000000004
EPC: 0000000040246ce2 RA: 0000000040246cdc reloc adjusted
Code: 9863 3ee7 8526 f0ef c37f 651c 3a03 0105 (43dc)
resetting ...
when I add only these:
int offset;
offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /* &sysgpio */
fdt_add_subnode(fdt, offset, "usb0-0");
fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),
"usb_pins", "/soc/pinctrl@13040000/usb0-0");
offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0");
/* usb_pins */
fdt_create_phandle(fdt, offset);
fdt_add_subnode(fdt, offset, "driver-vbus-pin");
offset = fdt_path_offset(fdt,
"/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */
fdt_setprop_empty(fdt, offset, "bias-disable");
fdt_setprop_empty(fdt, offset, "input-disable");
fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
fdt_setprop_u32(fdt, offset, "slew-rate", 0);
offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */
fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
fdt_setprop_u32(fdt, offset, "pinctrl-0", fdt_get_phandle(fdt,
fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0")));
fdt_setprop_string(fdt, offset, "status", "okay");
offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /*
&usb_cdns3 */
fdt_setprop_string(fdt, offset, "dr_mode", "host");
Success USB is working but PCI disabled if instead I add all of this:
int offset;
offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /* &sysgpio */
fdt_add_subnode(fdt, offset, "usb0-0");
fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),
"usb_pins", "/soc/pinctrl@13040000/usb0-0");
offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0");
/* usb_pins */
fdt_create_phandle(fdt, offset);
fdt_add_subnode(fdt, offset, "driver-vbus-pin");
offset = fdt_path_offset(fdt,
"/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */
fdt_setprop_empty(fdt, offset, "bias-disable");
fdt_setprop_empty(fdt, offset, "input-disable");
fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
fdt_setprop_u32(fdt, offset, "slew-rate", 0);
offset = fdt_path_offset(fdt, "/soc/pcie@2b000000"); /* &pcie0 */
fdt_setprop_string(fdt, offset, "status", "disabled");
offset = fdt_path_offset(fdt, "/soc/phy@10210000"); /* &pciephy0 */
fdt_setprop_u32(fdt, offset, "starfive,sys-syscon",
fdt_get_phandle(fdt, fdt_path_offset(fdt,
"/soc/sys_syscon@13030000"))); /* = <&sys_syscon> */
fdt_appendprop_u32(fdt, offset, "starfive,sys-syscon", 0x18);
/* append <magic number> */
fdt_setprop_u32(fdt, offset, "starfive,stg-syscon",
fdt_get_phandle(fdt, fdt_path_offset(fdt,
"/soc/stg_syscon@10240000"))); /* = <&stg_syscon> */
fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x148);
/* append <magic number> */
fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x1f4);
/* append <magic number> */
fdt_setprop_string(fdt, offset, "status", "okay");
offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */
fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
fdt_setprop_u32(fdt, offset, "pinctrl-0", fdt_get_phandle(fdt,
fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0")));
fdt_setprop_string(fdt, offset, "status", "okay");
offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /*
&usb_cdns3 */
fdt_setprop_u32(fdt, offset, "phys",
fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/phy@10200000"))); /* =
<&usbphy0> */
fdt_appendprop_u32(fdt, offset, "phys",
fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/phy@10210000"))); /*
append <&pciephy0> */
fdt_setprop(fdt, offset, "phy-names",
"cdns3,usb2-phy\0cdns3,usb3-phy",
sizeof("cdns3,usb2-phy\0cdns3,usb3-phy"));
fdt_setprop_string(fdt, offset, "dr_mode", "host");
I have made some mistake for devicetree and USB2.0 with keeping pcie0
(not disable)? or is there a problem with the implementation?
Best regards, -E Shattow
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node
2024-07-21 1:47 ` E Shattow
@ 2024-07-21 18:27 ` E Shattow
2024-07-23 1:29 ` Minda Chen
0 siblings, 1 reply; 19+ messages in thread
From: E Shattow @ 2024-07-21 18:27 UTC (permalink / raw)
To: Minda Chen
Cc: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang, u-boot, Heinrich Schuchardt,
Simon Glass
On Sat, Jul 20, 2024 at 6:47 PM E Shattow <lucent@gmail.com> wrote:
>
> Hi, I am testing on Milk-V Mars CM Lite, and I add to these devicetree
> changes at runtime from board/starfive/visionfive2/spl.c
>
> On Thu, Jul 18, 2024 at 6:38 PM Minda Chen <minda.chen@starfivetech.com> wrote:
> >
> > Add Jh7110 Cadence USB dts node, Visionfive2 default setting
> > is USB 2.0 device.
> >
> > Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> > ---
> > .../dts/jh7110-starfive-visionfive-2.dtsi | 5 ++
> > arch/riscv/dts/jh7110.dtsi | 52 +++++++++++++++++++
> > 2 files changed, 57 insertions(+)
> >
> > diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > index e11babc1cd..44785bbee3 100644
> > --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > @@ -378,3 +378,8 @@
> > };
> > };
> > };
> > +
> > +&usb_cdns3 {
> > + dr_mode = "peripheral";
> > + status = "okay";
> > +};
> > diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
> > index 2cdc683d49..1eee924e1d 100644
> > --- a/arch/riscv/dts/jh7110.dtsi
> > +++ b/arch/riscv/dts/jh7110.dtsi
> > @@ -371,6 +371,58 @@
> > status = "disabled";
> > };
> >
> > + usb0: usb@10100000 {
> > + compatible = "starfive,jh7110-usb";
> > + ranges = <0x0 0x0 0x10100000 0x100000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + starfive,stg-syscon = <&stg_syscon 0x4>;
> > + clocks = <&stgcrg JH7110_STGCLK_USB_LPM>,
> > + <&stgcrg JH7110_STGCLK_USB_STB>,
> > + <&stgcrg JH7110_STGCLK_USB_APB>,
> > + <&stgcrg JH7110_STGCLK_USB_AXI>,
> > + <&stgcrg JH7110_STGCLK_USB_UTMI_APB>;
> > + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
> > + resets = <&stgcrg JH7110_STGRST_USB_PWRUP>,
> > + <&stgcrg JH7110_STGRST_USB_APB>,
> > + <&stgcrg JH7110_STGRST_USB_AXI>,
> > + <&stgcrg JH7110_STGRST_USB_UTMI_APB>;
> > + reset-names = "pwrup", "apb", "axi", "utmi_apb";
> > +
> > + usb_cdns3: usb@0 {
> > + compatible = "cdns,usb3";
> > + reg = <0x0 0x10000>,
> > + <0x10000 0x10000>,
> > + <0x20000 0x10000>;
> > + reg-names = "otg", "xhci", "dev";
> > + interrupts = <100>, <108>, <110>;
> > + interrupt-names = "host", "peripheral", "otg";
> > + phys = <&usbphy0>;
> > + phy-names = "cdns3,usb2-phy";
> > + };
> > + };
> > +
> > + usbphy0: phy@10200000 {
> > + compatible = "starfive,jh7110-usb-phy";
> > + reg = <0x0 0x10200000 0x0 0x10000>;
> > + clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
> > + <&stgcrg JH7110_STGCLK_USB_APP_125>;
> > + clock-names = "125m", "app_125m";
> > + #phy-cells = <0>;
> > + };
> > +
> > + pciephy0: phy@10210000 {
> > + compatible = "starfive,jh7110-pcie-phy";
> > + reg = <0x0 0x10210000 0x0 0x10000>;
> > + #phy-cells = <0>;
> > + };
> > +
> > + pciephy1: phy@10220000 {
> > + compatible = "starfive,jh7110-pcie-phy";
> > + reg = <0x0 0x10220000 0x0 0x10000>;
> > + #phy-cells = <0>;
> > + };
> > +
> > stgcrg: clock-controller@10230000 {
> > compatible = "starfive,jh7110-stgcrg";
> > reg = <0x0 0x10230000 0x0 0x10000>;
> > --
> > 2.17.1
> >
>
> Access fault
>
> starting USB...
> Bus usb@0: cdns-usb3-host usb@0: set 1 has failed, back to 0
> scanning bus usb@0 for devices... Unhandled exception: Load access fault
> EPC: 00000000fff85ce2 RA: 00000000fff85cdc TVAL: 0000000000000004
> EPC: 0000000040246ce2 RA: 0000000040246cdc reloc adjusted
>
> Code: 9863 3ee7 8526 f0ef c37f 651c 3a03 0105 (43dc)
>
>
> resetting ...
>
> when I add only these:
>
> int offset;
>
> offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /* &sysgpio */
> fdt_add_subnode(fdt, offset, "usb0-0");
> fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),
> "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0");
> /* usb_pins */
> fdt_create_phandle(fdt, offset);
> fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> offset = fdt_path_offset(fdt,
> "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
> GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */
> fdt_setprop_empty(fdt, offset, "bias-disable");
> fdt_setprop_empty(fdt, offset, "input-disable");
> fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> fdt_setprop_u32(fdt, offset, "slew-rate", 0);
>
> offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */
> fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> fdt_setprop_u32(fdt, offset, "pinctrl-0", fdt_get_phandle(fdt,
> fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0")));
> fdt_setprop_string(fdt, offset, "status", "okay");
>
> offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /*
> &usb_cdns3 */
> fdt_setprop_string(fdt, offset, "dr_mode", "host");
>
> Success USB is working but PCI disabled if instead I add all of this:
>
> int offset;
>
> offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /* &sysgpio */
> fdt_add_subnode(fdt, offset, "usb0-0");
> fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),
> "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0");
> /* usb_pins */
> fdt_create_phandle(fdt, offset);
> fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> offset = fdt_path_offset(fdt,
> "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
> GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */
> fdt_setprop_empty(fdt, offset, "bias-disable");
> fdt_setprop_empty(fdt, offset, "input-disable");
> fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> fdt_setprop_u32(fdt, offset, "slew-rate", 0);
>
> offset = fdt_path_offset(fdt, "/soc/pcie@2b000000"); /* &pcie0 */
> fdt_setprop_string(fdt, offset, "status", "disabled");
>
> offset = fdt_path_offset(fdt, "/soc/phy@10210000"); /* &pciephy0 */
> fdt_setprop_u32(fdt, offset, "starfive,sys-syscon",
> fdt_get_phandle(fdt, fdt_path_offset(fdt,
> "/soc/sys_syscon@13030000"))); /* = <&sys_syscon> */
> fdt_appendprop_u32(fdt, offset, "starfive,sys-syscon", 0x18);
> /* append <magic number> */
> fdt_setprop_u32(fdt, offset, "starfive,stg-syscon",
> fdt_get_phandle(fdt, fdt_path_offset(fdt,
> "/soc/stg_syscon@10240000"))); /* = <&stg_syscon> */
> fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x148);
> /* append <magic number> */
> fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x1f4);
> /* append <magic number> */
> fdt_setprop_string(fdt, offset, "status", "okay");
>
> offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */
> fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> fdt_setprop_u32(fdt, offset, "pinctrl-0", fdt_get_phandle(fdt,
> fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0")));
> fdt_setprop_string(fdt, offset, "status", "okay");
>
> offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /*
> &usb_cdns3 */
> fdt_setprop_u32(fdt, offset, "phys",
> fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/phy@10200000"))); /* =
> <&usbphy0> */
> fdt_appendprop_u32(fdt, offset, "phys",
> fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/phy@10210000"))); /*
> append <&pciephy0> */
> fdt_setprop(fdt, offset, "phy-names",
> "cdns3,usb2-phy\0cdns3,usb3-phy",
> sizeof("cdns3,usb2-phy\0cdns3,usb3-phy"));
> fdt_setprop_string(fdt, offset, "dr_mode", "host");
>
> I have made some mistake for devicetree and USB2.0 with keeping pcie0
> (not disable)? or is there a problem with the implementation?
>
> Best regards, -E Shattow
P.S. here is with debug logging:
drivers/core/ofnode.c:517- ofnode_read_prop() ofnode_read_prop:
assigned-clock-rates: <not found>
drivers/core/uclass.c:537-uclass_get_device_by_ofnode() Looking for phy@10200000
drivers/core/uclass.c:388-uclass_find_device_by_ofnode() Looking for
phy@10200000
drivers/core/uclass.c:407-uclass_find_device_by_ofnode() - result
for phy@10200000: phy@10200000 (ret=0)
drivers/core/uclass.c:540-uclass_get_device_by_ofnode() - result
for phy@10200000: phy@10200000 (ret=0)
drivers/core/ofnode.c:517- ofnode_read_prop() ofnode_read_prop:
assigned-clock-rates: <not found>
drivers/core/uclass.c:537-uclass_get_device_by_ofnode() Looking for
clock-controller@13020000
drivers/core/uclass.c:388-uclass_find_device_by_ofnode() Looking for
clock-controller@13020000
drivers/core/uclass.c:407-uclass_find_device_by_ofnode() - result
for clock-controller@13020000: clock-controller@13020000 (ret=0)
drivers/core/uclass.c:540-uclass_get_device_by_ofnode() - result
for clock-controller@13020000: clock-controller@13020000 (ret=0)
drivers/core/uclass.c:537-uclass_get_device_by_ofnode() Looking for
clock-controller@10230000
drivers/core/uclass.c:388-uclass_find_device_by_ofnode() Looking for
clock-controller@10230000
drivers/core/uclass.c:407-uclass_find_device_by_ofnode() - result
for clock-controller@10230000: clock-controller@10230000 (ret=0)
drivers/core/uclass.c:540-uclass_get_device_by_ofnode() - result
for clock-controller@10230000: clock-controller@10230000 (ret=0)
common/event.c:113- notify_dynamic() Sending event 5/(unknown) to
spy 'efi_disk add'
drivers/usb/cdns3/drd.c:287- cdns3_drd_init() cdns-usb3-host
usb@0: DRD version v1 (ID: 0004024e, rev: 00000200)
drivers/usb/cdns3/drd.c:297- cdns3_drd_init() cdns-usb3-host
usb@0: Controller strapped to HOST
drivers/core/ofnode.c:517- ofnode_read_prop() ofnode_read_prop: dr_mode: host
drivers/phy/starfive/phy-jh7110-usb2.c:58- usb2_phy_set_mode()
jh7110_usb2_phy phy@10200000: Changing phy to 1
drivers/usb/cdns3/core.c:304-cdns3_hw_role_switch() cdns-usb3-host
usb@0: Switching role 0 -> 1cdns-usb3-host usb@0: Waiting till Host
mode is turned on
drivers/usb/cdns3/core.c:309-cdns3_hw_role_switch() cdns-usb3-host
usb@0: set 1 has failed, back to 0
drivers/usb/cdns3/core.c:375- cdns3_probe() cdns-usb3-host
usb@0: Cadence USB3 core: probe succeed
common/event.c:113- notify_dynamic() Sending event 5/(unknown) to
spy 'efi_disk add'
drivers/core/ofnode.c:394-ofnode_read_u32_index()
ofnode_read_u32_index: companion: (not found)
scanning bus usb@0 for devices... Unhandled exception: Load access fault
EPC: 00000000fff7f50e RA: 00000000fff7f508 TVAL: 0000000000000004
EPC: 000000004024d50e RA: 000000004024d508 reloc adjusted
Code: 9863 3ee7 8526 f0ef c37f 651c 3a03 0105 (43dc)
resetting ...
-E
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node
2024-07-21 18:27 ` E Shattow
@ 2024-07-23 1:29 ` Minda Chen
2024-07-23 3:53 ` E Shattow
0 siblings, 1 reply; 19+ messages in thread
From: Minda Chen @ 2024-07-23 1:29 UTC (permalink / raw)
To: E Shattow
Cc: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang, u-boot@lists.denx.de,
Heinrich Schuchardt, Simon Glass
>
> On Sat, Jul 20, 2024 at 6:47 PM E Shattow <lucent@gmail.com> wrote:
> >
> > Hi, I am testing on Milk-V Mars CM Lite, and I add to these devicetree
> > changes at runtime from board/starfive/visionfive2/spl.c
> >
> > On Thu, Jul 18, 2024 at 6:38 PM Minda Chen <minda.chen@starfivetech.com>
> wrote:
> > >
> > > Add Jh7110 Cadence USB dts node, Visionfive2 default setting is USB
> > > 2.0 device.
> > >
> > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> > > ---
> > > .../dts/jh7110-starfive-visionfive-2.dtsi | 5 ++
> > > arch/riscv/dts/jh7110.dtsi | 52
> +++++++++++++++++++
> > > 2 files changed, 57 insertions(+)
> > >
> > > diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > index e11babc1cd..44785bbee3 100644
> > > --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > @@ -378,3 +378,8 @@
> > > };
> > > };
> > > };
> > > +
> > > +&usb_cdns3 {
> > > + dr_mode = "peripheral";
> > > + status = "okay";
> > > +};
> > > diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
> > > index 2cdc683d49..1eee924e1d 100644
> > > --- a/arch/riscv/dts/jh7110.dtsi
> > > +++ b/arch/riscv/dts/jh7110.dtsi
> > > @@ -371,6 +371,58 @@
> > > status = "disabled";
> > > };
> > >
> > > + usb0: usb@10100000 {
> > > + compatible = "starfive,jh7110-usb";
> > > + ranges = <0x0 0x0 0x10100000 0x100000>;
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + starfive,stg-syscon = <&stg_syscon 0x4>;
> > > + clocks = <&stgcrg
> JH7110_STGCLK_USB_LPM>,
> > > + <&stgcrg
> JH7110_STGCLK_USB_STB>,
> > > + <&stgcrg
> JH7110_STGCLK_USB_APB>,
> > > + <&stgcrg
> JH7110_STGCLK_USB_AXI>,
> > > + <&stgcrg
> JH7110_STGCLK_USB_UTMI_APB>;
> > > + clock-names = "lpm", "stb", "apb", "axi",
> "utmi_apb";
> > > + resets = <&stgcrg
> JH7110_STGRST_USB_PWRUP>,
> > > + <&stgcrg
> JH7110_STGRST_USB_APB>,
> > > + <&stgcrg
> JH7110_STGRST_USB_AXI>,
> > > + <&stgcrg
> JH7110_STGRST_USB_UTMI_APB>;
> > > + reset-names = "pwrup", "apb", "axi",
> > > + "utmi_apb";
> > > +
> > > + usb_cdns3: usb@0 {
> > > + compatible = "cdns,usb3";
> > > + reg = <0x0 0x10000>,
> > > + <0x10000 0x10000>,
> > > + <0x20000 0x10000>;
> > > + reg-names = "otg", "xhci", "dev";
> > > + interrupts = <100>, <108>, <110>;
> > > + interrupt-names = "host",
> "peripheral", "otg";
> > > + phys = <&usbphy0>;
> > > + phy-names = "cdns3,usb2-phy";
> > > + };
> > > + };
> > > +
> > > + usbphy0: phy@10200000 {
> > > + compatible = "starfive,jh7110-usb-phy";
> > > + reg = <0x0 0x10200000 0x0 0x10000>;
> > > + clocks = <&syscrg
> JH7110_SYSCLK_USB_125M>,
> > > + <&stgcrg
> JH7110_STGCLK_USB_APP_125>;
> > > + clock-names = "125m", "app_125m";
> > > + #phy-cells = <0>;
> > > + };
> > > +
> > > + pciephy0: phy@10210000 {
> > > + compatible = "starfive,jh7110-pcie-phy";
> > > + reg = <0x0 0x10210000 0x0 0x10000>;
> > > + #phy-cells = <0>;
> > > + };
> > > +
> > > + pciephy1: phy@10220000 {
> > > + compatible = "starfive,jh7110-pcie-phy";
> > > + reg = <0x0 0x10220000 0x0 0x10000>;
> > > + #phy-cells = <0>;
> > > + };
> > > +
> > > stgcrg: clock-controller@10230000 {
> > > compatible = "starfive,jh7110-stgcrg";
> > > reg = <0x0 0x10230000 0x0 0x10000>;
> > > --
> > > 2.17.1
> > >
> >
> > Access fault
> >
> > starting USB...
> > Bus usb@0: cdns-usb3-host usb@0: set 1 has failed, back to 0
> > scanning bus usb@0 for devices... Unhandled exception: Load
> access fault
> > EPC: 00000000fff85ce2 RA: 00000000fff85cdc TVAL:
> 0000000000000004
> > EPC: 0000000040246ce2 RA: 0000000040246cdc reloc adjusted
> >
> > Code: 9863 3ee7 8526 f0ef c37f 651c 3a03 0105 (43dc)
> >
> >
> > resetting ...
> >
> > when I add only these:
> >
> > int offset;
> >
> > offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /*
> &sysgpio */
> > fdt_add_subnode(fdt, offset, "usb0-0");
> > fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),
> > "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> > offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0");
> > /* usb_pins */
> > fdt_create_phandle(fdt, offset);
> > fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> > offset = fdt_path_offset(fdt,
> > "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> > fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
> > GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE)
> */
> > fdt_setprop_empty(fdt, offset, "bias-disable");
> > fdt_setprop_empty(fdt, offset, "input-disable");
> > fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> > fdt_setprop_u32(fdt, offset, "slew-rate", 0);
> >
> > offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */
> > fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> > fdt_setprop_u32(fdt, offset, "pinctrl-0", fdt_get_phandle(fdt,
> > fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0")));
> > fdt_setprop_string(fdt, offset, "status", "okay");
> >
> > offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /*
> > &usb_cdns3 */
> > fdt_setprop_string(fdt, offset, "dr_mode", "host");
> >
> > Success USB is working but PCI disabled if instead I add all of this:
> >
I checked t Milk-V CM board do not contain USB3.0 host
So I think the USB 3.0 configuration is not required.
> > int offset;
> >
> > offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /*
> &sysgpio */
> > fdt_add_subnode(fdt, offset, "usb0-0");
> > fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),
> > "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> > offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0");
> > /* usb_pins */
> > fdt_create_phandle(fdt, offset);
> > fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> > offset = fdt_path_offset(fdt,
> > "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> > fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
> > GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE)
> */
> > fdt_setprop_empty(fdt, offset, "bias-disable");
> > fdt_setprop_empty(fdt, offset, "input-disable");
> > fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> > fdt_setprop_u32(fdt, offset, "slew-rate", 0);
> >
> > offset = fdt_path_offset(fdt, "/soc/pcie@2b000000"); /* &pcie0 */
> > fdt_setprop_string(fdt, offset, "status", "disabled");
> >
> > offset = fdt_path_offset(fdt, "/soc/phy@10210000"); /* &pciephy0
> */
> > fdt_setprop_u32(fdt, offset, "starfive,sys-syscon",
> > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > "/soc/sys_syscon@13030000"))); /* = <&sys_syscon> */
> > fdt_appendprop_u32(fdt, offset, "starfive,sys-syscon", 0x18);
> > /* append <magic number> */
> > fdt_setprop_u32(fdt, offset, "starfive,stg-syscon",
> > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > "/soc/stg_syscon@10240000"))); /* = <&stg_syscon> */
> > fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x148);
> > /* append <magic number> */
> > fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x1f4);
> > /* append <magic number> */
> > fdt_setprop_string(fdt, offset, "status", "okay");
> >
> > offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */
> > fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> > fdt_setprop_u32(fdt, offset, "pinctrl-0", fdt_get_phandle(fdt,
> > fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0")));
> > fdt_setprop_string(fdt, offset, "status", "okay");
> >
> > offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /*
> > &usb_cdns3 */
> > fdt_setprop_u32(fdt, offset, "phys",
> > fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/phy@10200000"))); /* =
> > <&usbphy0> */
> > fdt_appendprop_u32(fdt, offset, "phys", fdt_get_phandle(fdt,
> > fdt_path_offset(fdt, "/soc/phy@10210000"))); /* append <&pciephy0> */
> > fdt_setprop(fdt, offset, "phy-names",
> > "cdns3,usb2-phy\0cdns3,usb3-phy",
> > sizeof("cdns3,usb2-phy\0cdns3,usb3-phy"));
> > fdt_setprop_string(fdt, offset, "dr_mode", "host");
> >
> > I have made some mistake for devicetree and USB2.0 with keeping pcie0
> > (not disable)? or is there a problem with the implementation?
> >
> > Best regards, -E Shattow
>
I don’t have a Milk-V CM board. So I just can test this code to Star64.
Thanks. I will test this and add the code to board_fixup_star64().
> P.S. here is with debug logging:
>
> drivers/core/ofnode.c:517- ofnode_read_prop() ofnode_read_prop:
> assigned-clock-rates: <not found>
> drivers/core/uclass.c:537-uclass_get_device_by_ofnode() Looking for
> phy@10200000
> drivers/core/uclass.c:388-uclass_find_device_by_ofnode() Looking for
> phy@10200000
> drivers/core/uclass.c:407-uclass_find_device_by_ofnode() - result
> for phy@10200000: phy@10200000 (ret=0)
> drivers/core/uclass.c:540-uclass_get_device_by_ofnode() - result
> for phy@10200000: phy@10200000 (ret=0)
> drivers/core/ofnode.c:517- ofnode_read_prop() ofnode_read_prop:
> assigned-clock-rates: <not found>
> drivers/core/uclass.c:537-uclass_get_device_by_ofnode() Looking for
> clock-controller@13020000
> drivers/core/uclass.c:388-uclass_find_device_by_ofnode() Looking for
> clock-controller@13020000
> drivers/core/uclass.c:407-uclass_find_device_by_ofnode() - result
> for clock-controller@13020000: clock-controller@13020000 (ret=0)
> drivers/core/uclass.c:540-uclass_get_device_by_ofnode() - result
> for clock-controller@13020000: clock-controller@13020000 (ret=0)
> drivers/core/uclass.c:537-uclass_get_device_by_ofnode() Looking for
> clock-controller@10230000
> drivers/core/uclass.c:388-uclass_find_device_by_ofnode() Looking for
> clock-controller@10230000
> drivers/core/uclass.c:407-uclass_find_device_by_ofnode() - result
> for clock-controller@10230000: clock-controller@10230000 (ret=0)
> drivers/core/uclass.c:540-uclass_get_device_by_ofnode() - result
> for clock-controller@10230000: clock-controller@10230000 (ret=0)
> common/event.c:113- notify_dynamic() Sending event 5/(unknown) to
> spy 'efi_disk add'
> drivers/usb/cdns3/drd.c:287- cdns3_drd_init() cdns-usb3-host
> usb@0: DRD version v1 (ID: 0004024e, rev: 00000200)
> drivers/usb/cdns3/drd.c:297- cdns3_drd_init() cdns-usb3-host
> usb@0: Controller strapped to HOST
> drivers/core/ofnode.c:517- ofnode_read_prop() ofnode_read_prop:
> dr_mode: host
> drivers/phy/starfive/phy-jh7110-usb2.c:58- usb2_phy_set_mode()
> jh7110_usb2_phy phy@10200000: Changing phy to 1
> drivers/usb/cdns3/core.c:304-cdns3_hw_role_switch() cdns-usb3-host
> usb@0: Switching role 0 -> 1cdns-usb3-host usb@0: Waiting till Host mode is
> turned on
> drivers/usb/cdns3/core.c:309-cdns3_hw_role_switch() cdns-usb3-host
> usb@0: set 1 has failed, back to 0
> drivers/usb/cdns3/core.c:375- cdns3_probe() cdns-usb3-host
> usb@0: Cadence USB3 core: probe succeed
> common/event.c:113- notify_dynamic() Sending event 5/(unknown) to
> spy 'efi_disk add'
> drivers/core/ofnode.c:394-ofnode_read_u32_index()
> ofnode_read_u32_index: companion: (not found) scanning bus usb@0 for
> devices... Unhandled exception: Load access fault
> EPC: 00000000fff7f50e RA: 00000000fff7f508 TVAL: 0000000000000004
> EPC: 000000004024d50e RA: 000000004024d508 reloc adjusted
>
> Code: 9863 3ee7 8526 f0ef c37f 651c 3a03 0105 (43dc)
>
>
> resetting ...
>
> -E
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node
2024-07-23 1:29 ` Minda Chen
@ 2024-07-23 3:53 ` E Shattow
2024-07-23 10:16 ` Minda Chen
0 siblings, 1 reply; 19+ messages in thread
From: E Shattow @ 2024-07-23 3:53 UTC (permalink / raw)
To: Minda Chen
Cc: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang, u-boot@lists.denx.de,
Heinrich Schuchardt, Simon Glass
On Mon, Jul 22, 2024 at 6:29 PM Minda Chen <minda.chen@starfivetech.com> wrote:
>
>
>
> >
> > On Sat, Jul 20, 2024 at 6:47 PM E Shattow <lucent@gmail.com> wrote:
> > >
> > > Hi, I am testing on Milk-V Mars CM Lite, and I add to these devicetree
> > > changes at runtime from board/starfive/visionfive2/spl.c
> > >
> > > On Thu, Jul 18, 2024 at 6:38 PM Minda Chen <minda.chen@starfivetech.com>
> > wrote:
> > > >
> > > > Add Jh7110 Cadence USB dts node, Visionfive2 default setting is USB
> > > > 2.0 device.
> > > >
> > > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> > > > ---
> > > > .../dts/jh7110-starfive-visionfive-2.dtsi | 5 ++
> > > > arch/riscv/dts/jh7110.dtsi | 52
> > +++++++++++++++++++
> > > > 2 files changed, 57 insertions(+)
> > > >
> > > > diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > index e11babc1cd..44785bbee3 100644
> > > > --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > @@ -378,3 +378,8 @@
> > > > };
> > > > };
> > > > };
> > > > +
> > > > +&usb_cdns3 {
> > > > + dr_mode = "peripheral";
> > > > + status = "okay";
> > > > +};
> > > > diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
> > > > index 2cdc683d49..1eee924e1d 100644
> > > > --- a/arch/riscv/dts/jh7110.dtsi
> > > > +++ b/arch/riscv/dts/jh7110.dtsi
> > > > @@ -371,6 +371,58 @@
> > > > status = "disabled";
> > > > };
> > > >
> > > > + usb0: usb@10100000 {
> > > > + compatible = "starfive,jh7110-usb";
> > > > + ranges = <0x0 0x0 0x10100000 0x100000>;
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + starfive,stg-syscon = <&stg_syscon 0x4>;
> > > > + clocks = <&stgcrg
> > JH7110_STGCLK_USB_LPM>,
> > > > + <&stgcrg
> > JH7110_STGCLK_USB_STB>,
> > > > + <&stgcrg
> > JH7110_STGCLK_USB_APB>,
> > > > + <&stgcrg
> > JH7110_STGCLK_USB_AXI>,
> > > > + <&stgcrg
> > JH7110_STGCLK_USB_UTMI_APB>;
> > > > + clock-names = "lpm", "stb", "apb", "axi",
> > "utmi_apb";
> > > > + resets = <&stgcrg
> > JH7110_STGRST_USB_PWRUP>,
> > > > + <&stgcrg
> > JH7110_STGRST_USB_APB>,
> > > > + <&stgcrg
> > JH7110_STGRST_USB_AXI>,
> > > > + <&stgcrg
> > JH7110_STGRST_USB_UTMI_APB>;
> > > > + reset-names = "pwrup", "apb", "axi",
> > > > + "utmi_apb";
> > > > +
> > > > + usb_cdns3: usb@0 {
> > > > + compatible = "cdns,usb3";
> > > > + reg = <0x0 0x10000>,
> > > > + <0x10000 0x10000>,
> > > > + <0x20000 0x10000>;
> > > > + reg-names = "otg", "xhci", "dev";
> > > > + interrupts = <100>, <108>, <110>;
> > > > + interrupt-names = "host",
> > "peripheral", "otg";
> > > > + phys = <&usbphy0>;
> > > > + phy-names = "cdns3,usb2-phy";
> > > > + };
> > > > + };
> > > > +
> > > > + usbphy0: phy@10200000 {
> > > > + compatible = "starfive,jh7110-usb-phy";
> > > > + reg = <0x0 0x10200000 0x0 0x10000>;
> > > > + clocks = <&syscrg
> > JH7110_SYSCLK_USB_125M>,
> > > > + <&stgcrg
> > JH7110_STGCLK_USB_APP_125>;
> > > > + clock-names = "125m", "app_125m";
> > > > + #phy-cells = <0>;
> > > > + };
> > > > +
> > > > + pciephy0: phy@10210000 {
> > > > + compatible = "starfive,jh7110-pcie-phy";
> > > > + reg = <0x0 0x10210000 0x0 0x10000>;
> > > > + #phy-cells = <0>;
> > > > + };
> > > > +
> > > > + pciephy1: phy@10220000 {
> > > > + compatible = "starfive,jh7110-pcie-phy";
> > > > + reg = <0x0 0x10220000 0x0 0x10000>;
> > > > + #phy-cells = <0>;
> > > > + };
> > > > +
> > > > stgcrg: clock-controller@10230000 {
> > > > compatible = "starfive,jh7110-stgcrg";
> > > > reg = <0x0 0x10230000 0x0 0x10000>;
> > > > --
> > > > 2.17.1
> > > >
> > >
> > > Access fault
> > >
> > > starting USB...
> > > Bus usb@0: cdns-usb3-host usb@0: set 1 has failed, back to 0
> > > scanning bus usb@0 for devices... Unhandled exception: Load
> > access fault
> > > EPC: 00000000fff85ce2 RA: 00000000fff85cdc TVAL:
> > 0000000000000004
> > > EPC: 0000000040246ce2 RA: 0000000040246cdc reloc adjusted
> > >
> > > Code: 9863 3ee7 8526 f0ef c37f 651c 3a03 0105 (43dc)
> > >
> > >
> > > resetting ...
> > >
> > > when I add only these:
> > >
> > > int offset;
> > >
> > > offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /*
> > &sysgpio */
> > > fdt_add_subnode(fdt, offset, "usb0-0");
> > > fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),
> > > "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> > > offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0");
> > > /* usb_pins */
> > > fdt_create_phandle(fdt, offset);
> > > fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> > > offset = fdt_path_offset(fdt,
> > > "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> > > fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
> > > GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE)
> > */
> > > fdt_setprop_empty(fdt, offset, "bias-disable");
> > > fdt_setprop_empty(fdt, offset, "input-disable");
> > > fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> > > fdt_setprop_u32(fdt, offset, "slew-rate", 0);
> > >
> > > offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */
> > > fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> > > fdt_setprop_u32(fdt, offset, "pinctrl-0", fdt_get_phandle(fdt,
> > > fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0")));
> > > fdt_setprop_string(fdt, offset, "status", "okay");
> > >
> > > offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /*
> > > &usb_cdns3 */
> > > fdt_setprop_string(fdt, offset, "dr_mode", "host");
> > >
> > > Success USB is working but PCI disabled if instead I add all of this:
> > >
> I checked t Milk-V CM board do not contain USB3.0 host
> So I think the USB 3.0 configuration is not required.
I agree it should be USB 2.0, but with your patch this is the only
configuration that does anything successful with USB2.0 or 3.0
>
> > > int offset;
> > >
> > > offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /*
> > &sysgpio */
> > > fdt_add_subnode(fdt, offset, "usb0-0");
> > > fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),
> > > "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> > > offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0");
> > > /* usb_pins */
> > > fdt_create_phandle(fdt, offset);
> > > fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> > > offset = fdt_path_offset(fdt,
> > > "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> > > fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
> > > GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE)
> > */
> > > fdt_setprop_empty(fdt, offset, "bias-disable");
> > > fdt_setprop_empty(fdt, offset, "input-disable");
> > > fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> > > fdt_setprop_u32(fdt, offset, "slew-rate", 0);
> > >
> > > offset = fdt_path_offset(fdt, "/soc/pcie@2b000000"); /* &pcie0 */
> > > fdt_setprop_string(fdt, offset, "status", "disabled");
> > >
> > > offset = fdt_path_offset(fdt, "/soc/phy@10210000"); /* &pciephy0
> > */
> > > fdt_setprop_u32(fdt, offset, "starfive,sys-syscon",
> > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > "/soc/sys_syscon@13030000"))); /* = <&sys_syscon> */
> > > fdt_appendprop_u32(fdt, offset, "starfive,sys-syscon", 0x18);
> > > /* append <magic number> */
> > > fdt_setprop_u32(fdt, offset, "starfive,stg-syscon",
> > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > "/soc/stg_syscon@10240000"))); /* = <&stg_syscon> */
> > > fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x148);
> > > /* append <magic number> */
> > > fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x1f4);
> > > /* append <magic number> */
> > > fdt_setprop_string(fdt, offset, "status", "okay");
> > >
> > > offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */
> > > fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> > > fdt_setprop_u32(fdt, offset, "pinctrl-0", fdt_get_phandle(fdt,
> > > fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0")));
> > > fdt_setprop_string(fdt, offset, "status", "okay");
> > >
> > > offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /*
> > > &usb_cdns3 */
> > > fdt_setprop_u32(fdt, offset, "phys",
> > > fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/phy@10200000"))); /* =
> > > <&usbphy0> */
> > > fdt_appendprop_u32(fdt, offset, "phys", fdt_get_phandle(fdt,
> > > fdt_path_offset(fdt, "/soc/phy@10210000"))); /* append <&pciephy0> */
> > > fdt_setprop(fdt, offset, "phy-names",
> > > "cdns3,usb2-phy\0cdns3,usb3-phy",
> > > sizeof("cdns3,usb2-phy\0cdns3,usb3-phy"));
> > > fdt_setprop_string(fdt, offset, "dr_mode", "host");
> > >
> > > I have made some mistake for devicetree and USB2.0 with keeping pcie0
> > > (not disable)? or is there a problem with the implementation?
> > >
> > > Best regards, -E Shattow
> >
> I don’t have a Milk-V CM board. So I just can test this code to Star64.
> Thanks. I will test this and add the code to board_fixup_star64().
Can you try to configure in USB2.0-only mode on Star64? Do you see
the same problem with "load access fault"?
...snip...
Same devicetree fixup code but separated some of the statements to
multiple lines:
https://paste.debian.net/1324036/
```
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index b794b73b6b..b4b0930e75 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -123,6 +123,53 @@ static const struct starfive_vf2_pro star64_pine64[] = {
"tx-internal-delay-ps", "300"},
};
+void spl_fdt_fixup_jh7110_cadence_usb3_host(void *fdt)
+{
+ int offset;
+ u32 phandle;
+
+ offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /* &sysgpio */
+ fdt_add_subnode(fdt, offset, "usb0-0");
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),
"usb_pins", "/soc/pinctrl@13040000/usb0-0");
+ offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0"); /* usb_pins */
+ fdt_create_phandle(fdt, offset);
+ fdt_add_subnode(fdt, offset, "driver-vbus-pin");
+ offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
+ fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /* GPIOMUX(25,
GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */
+ fdt_setprop_empty(fdt, offset, "bias-disable");
+ fdt_setprop_empty(fdt, offset, "input-disable");
+ fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
+ fdt_setprop_u32(fdt, offset, "slew-rate", 0);
+
+ offset = fdt_path_offset(fdt, "/soc/pcie@2b000000"); /* &pcie0 */
+ fdt_setprop_string(fdt, offset, "status", "disabled");
+
+ offset = fdt_path_offset(fdt, "/soc/phy@10210000"); /* &pciephy0 */
+ phandle = fdt_get_phandle(fdt, fdt_path_offset(fdt,
"/soc/sys_syscon@13030000")); /* = <&sys_syscon> */
+ fdt_setprop_u32(fdt, offset, "starfive,sys-syscon", phandle);
+ fdt_appendprop_u32(fdt, offset, "starfive,sys-syscon", 0x18); /*
append <magic number> */
+ phandle = fdt_get_phandle(fdt, fdt_path_offset(fdt,
"/soc/stg_syscon@10240000")); /* = <&stg_syscon> */
+ fdt_setprop_u32(fdt, offset, "starfive,stg-syscon", phandle);
+ fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x148); /*
append <magic number> */
+ fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x1f4); /*
append <magic number> */
+ fdt_setprop_string(fdt, offset, "status", "okay");
+
+ offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */
+ fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
+ phandle = fdt_get_phandle(fdt, fdt_path_offset(fdt,
"/soc/pinctrl@13040000/usb0-0")); /* <&usb_pins> */
+ fdt_setprop_u32(fdt, offset, "pinctrl-0", phandle);
+ fdt_setprop_string(fdt, offset, "status", "okay");
+
+ offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /* &usb_cdns3 */
+ phandle = fdt_get_phandle(fdt, fdt_path_offset(fdt,
"/soc/phy@10200000")); /* = <&usbphy0> */
+ fdt_setprop_u32(fdt, offset, "phys", phandle);
+ phandle = fdt_get_phandle(fdt, fdt_path_offset(fdt,
"/soc/phy@10210000")); /* append <&pciephy0> */
+ fdt_appendprop_u32(fdt, offset, "phys", phandle);
+ fdt_setprop_string(fdt, offset, "phy-names", "cdns3,usb2-phy");
+ fdt_appendprop_string(fdt, offset, "phy-names", "cdns3,usb3-phy");
+ fdt_setprop_string(fdt, offset, "dr_mode", "host");
+}
+
void spl_fdt_fixup_mars(void *fdt)
{
static const char compat[] = "milkv,mars\0starfive,jh7110";
@@ -335,6 +382,8 @@ void spl_fdt_fixup_star64(void *fdt)
break;
}
}
+
+ spl_fdt_fixup_jh7110_cadence_usb3_host(fdt);
}
void spl_perform_fixups(struct spl_image_info *spl_image)
```
I think there is missing some of the USB2.0-only logic in your patch.
Can you try some more testing to understand why this fault happens
here?
Thanks,
-E
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node
2024-07-23 3:53 ` E Shattow
@ 2024-07-23 10:16 ` Minda Chen
2024-07-23 13:05 ` E Shattow
0 siblings, 1 reply; 19+ messages in thread
From: Minda Chen @ 2024-07-23 10:16 UTC (permalink / raw)
To: E Shattow
Cc: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang, u-boot@lists.denx.de,
Heinrich Schuchardt, Simon Glass
>
> On Mon, Jul 22, 2024 at 6:29 PM Minda Chen <minda.chen@starfivetech.com>
> wrote:
> >
> >
> >
> > >
> > > On Sat, Jul 20, 2024 at 6:47 PM E Shattow <lucent@gmail.com> wrote:
> > > >
> > > > Hi, I am testing on Milk-V Mars CM Lite, and I add to these
> > > > devicetree changes at runtime from
> > > > board/starfive/visionfive2/spl.c
> > > >
> > > > On Thu, Jul 18, 2024 at 6:38 PM Minda Chen
> > > > <minda.chen@starfivetech.com>
> > > wrote:
> > > > >
> > > > > Add Jh7110 Cadence USB dts node, Visionfive2 default setting is
> > > > > USB
> > > > > 2.0 device.
> > > > >
> > > > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> > > > > ---
> > > > > .../dts/jh7110-starfive-visionfive-2.dtsi | 5 ++
> > > > > arch/riscv/dts/jh7110.dtsi | 52
> > > +++++++++++++++++++
> > > > > 2 files changed, 57 insertions(+)
> > > > >
> > > > > diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > index e11babc1cd..44785bbee3 100644
> > > > > --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > @@ -378,3 +378,8 @@
> > > > > };
> > > > > };
> > > > > };
> > > > > +
> > > > > +&usb_cdns3 {
> > > > > + dr_mode = "peripheral";
> > > > > + status = "okay";
> > > > > +};
> > > > > diff --git a/arch/riscv/dts/jh7110.dtsi
> > > > > b/arch/riscv/dts/jh7110.dtsi index 2cdc683d49..1eee924e1d 100644
> > > > > --- a/arch/riscv/dts/jh7110.dtsi
> > > > > +++ b/arch/riscv/dts/jh7110.dtsi
> > > > > @@ -371,6 +371,58 @@
> > > > > status = "disabled";
> > > > > };
> > > > >
> > > > > + usb0: usb@10100000 {
> > > > > + compatible = "starfive,jh7110-usb";
> > > > > + ranges = <0x0 0x0 0x10100000 0x100000>;
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <1>;
> > > > > + starfive,stg-syscon = <&stg_syscon 0x4>;
> > > > > + clocks = <&stgcrg
> > > JH7110_STGCLK_USB_LPM>,
> > > > > + <&stgcrg
> > > JH7110_STGCLK_USB_STB>,
> > > > > + <&stgcrg
> > > JH7110_STGCLK_USB_APB>,
> > > > > + <&stgcrg
> > > JH7110_STGCLK_USB_AXI>,
> > > > > + <&stgcrg
> > > JH7110_STGCLK_USB_UTMI_APB>;
> > > > > + clock-names = "lpm", "stb", "apb",
> > > > > + "axi",
> > > "utmi_apb";
> > > > > + resets = <&stgcrg
> > > JH7110_STGRST_USB_PWRUP>,
> > > > > + <&stgcrg
> > > JH7110_STGRST_USB_APB>,
> > > > > + <&stgcrg
> > > JH7110_STGRST_USB_AXI>,
> > > > > + <&stgcrg
> > > JH7110_STGRST_USB_UTMI_APB>;
> > > > > + reset-names = "pwrup", "apb", "axi",
> > > > > + "utmi_apb";
> > > > > +
> > > > > + usb_cdns3: usb@0 {
> > > > > + compatible = "cdns,usb3";
> > > > > + reg = <0x0 0x10000>,
> > > > > + <0x10000 0x10000>,
> > > > > + <0x20000 0x10000>;
> > > > > + reg-names = "otg", "xhci",
> "dev";
> > > > > + interrupts = <100>, <108>,
> <110>;
> > > > > + interrupt-names = "host",
> > > "peripheral", "otg";
> > > > > + phys = <&usbphy0>;
> > > > > + phy-names = "cdns3,usb2-phy";
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + usbphy0: phy@10200000 {
> > > > > + compatible = "starfive,jh7110-usb-phy";
> > > > > + reg = <0x0 0x10200000 0x0 0x10000>;
> > > > > + clocks = <&syscrg
> > > JH7110_SYSCLK_USB_125M>,
> > > > > + <&stgcrg
> > > JH7110_STGCLK_USB_APP_125>;
> > > > > + clock-names = "125m", "app_125m";
> > > > > + #phy-cells = <0>;
> > > > > + };
> > > > > +
> > > > > + pciephy0: phy@10210000 {
> > > > > + compatible = "starfive,jh7110-pcie-phy";
> > > > > + reg = <0x0 0x10210000 0x0 0x10000>;
> > > > > + #phy-cells = <0>;
> > > > > + };
> > > > > +
> > > > > + pciephy1: phy@10220000 {
> > > > > + compatible = "starfive,jh7110-pcie-phy";
> > > > > + reg = <0x0 0x10220000 0x0 0x10000>;
> > > > > + #phy-cells = <0>;
> > > > > + };
> > > > > +
> > > > > stgcrg: clock-controller@10230000 {
> > > > > compatible = "starfive,jh7110-stgcrg";
> > > > > reg = <0x0 0x10230000 0x0 0x10000>;
> > > > > --
> > > > > 2.17.1
> > > > >
> > > >
> > > > Access fault
> > > >
> > > > starting USB...
> > > > Bus usb@0: cdns-usb3-host usb@0: set 1 has failed, back to 0
> > > > scanning bus usb@0 for devices... Unhandled exception:
> > > > Load
> > > access fault
> > > > EPC: 00000000fff85ce2 RA: 00000000fff85cdc TVAL:
> > > 0000000000000004
> > > > EPC: 0000000040246ce2 RA: 0000000040246cdc reloc adjusted
> > > >
> > > > Code: 9863 3ee7 8526 f0ef c37f 651c 3a03 0105 (43dc)
> > > >
> > > >
> > > > resetting ...
> > > >
> > > > when I add only these:
> > > >
> > > > int offset;
> > > >
> > > > offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /*
> > > &sysgpio */
> > > > fdt_add_subnode(fdt, offset, "usb0-0");
> > > > fdt_setprop_string(fdt, fdt_path_offset(fdt,
> > > > "/__symbols__"), "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> > > > offset = fdt_path_offset(fdt,
> > > > "/soc/pinctrl@13040000/usb0-0");
> > > > /* usb_pins */
> > > > fdt_create_phandle(fdt, offset);
> > > > fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> > > > offset = fdt_path_offset(fdt,
> > > > "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> > > > fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
> > > > GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE,
> GPI_NONE)
> > > */
> > > > fdt_setprop_empty(fdt, offset, "bias-disable");
> > > > fdt_setprop_empty(fdt, offset, "input-disable");
> > > > fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> > > > fdt_setprop_u32(fdt, offset, "slew-rate", 0);
> > > >
> > > > offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0
> */
> > > > fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> > > > fdt_setprop_u32(fdt, offset, "pinctrl-0",
> > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> "/soc/pinctrl@13040000/usb0-0")));
> > > > fdt_setprop_string(fdt, offset, "status", "okay");
> > > >
> > > > offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0");
> > > > /*
> > > > &usb_cdns3 */
> > > > fdt_setprop_string(fdt, offset, "dr_mode", "host");
> > > >
> > > > Success USB is working but PCI disabled if instead I add all of this:
> > > >
>
> > I checked t Milk-V CM board do not contain USB3.0 host So I think the
> > USB 3.0 configuration is not required.
>
> I agree it should be USB 2.0, but with your patch this is the only configuration
> that does anything successful with USB2.0 or 3.0
>
>
> >
> > > > int offset;
> > > >
> > > > offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /*
> > > &sysgpio */
> > > > fdt_add_subnode(fdt, offset, "usb0-0");
> > > > fdt_setprop_string(fdt, fdt_path_offset(fdt,
> > > > "/__symbols__"), "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> > > > offset = fdt_path_offset(fdt,
> > > > "/soc/pinctrl@13040000/usb0-0");
> > > > /* usb_pins */
> > > > fdt_create_phandle(fdt, offset);
> > > > fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> > > > offset = fdt_path_offset(fdt,
> > > > "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> > > > fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
> > > > GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE,
> GPI_NONE)
> > > */
> > > > fdt_setprop_empty(fdt, offset, "bias-disable");
> > > > fdt_setprop_empty(fdt, offset, "input-disable");
> > > > fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> > > > fdt_setprop_u32(fdt, offset, "slew-rate", 0);
> > > >
> > > > offset = fdt_path_offset(fdt, "/soc/pcie@2b000000"); /* &pcie0
> */
> > > > fdt_setprop_string(fdt, offset, "status", "disabled");
> > > >
> > > > offset = fdt_path_offset(fdt, "/soc/phy@10210000"); /*
> > > > &pciephy0
> > > */
> > > > fdt_setprop_u32(fdt, offset, "starfive,sys-syscon",
> > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > > "/soc/sys_syscon@13030000"))); /* = <&sys_syscon> */
> > > > fdt_appendprop_u32(fdt, offset, "starfive,sys-syscon",
> > > > 0x18);
> > > > /* append <magic number> */
> > > > fdt_setprop_u32(fdt, offset, "starfive,stg-syscon",
> > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > > "/soc/stg_syscon@10240000"))); /* = <&stg_syscon> */
> > > > fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon",
> > > > 0x148);
> > > > /* append <magic number> */
> > > > fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon",
> > > > 0x1f4);
> > > > /* append <magic number> */
> > > > fdt_setprop_string(fdt, offset, "status", "okay");
> > > >
> > > > offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0
> */
> > > > fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> > > > fdt_setprop_u32(fdt, offset, "pinctrl-0",
> > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> "/soc/pinctrl@13040000/usb0-0")));
> > > > fdt_setprop_string(fdt, offset, "status", "okay");
> > > >
> > > > offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0");
> > > > /*
> > > > &usb_cdns3 */
> > > > fdt_setprop_u32(fdt, offset, "phys",
> > > > fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/phy@10200000")));
> > > > /* = <&usbphy0> */
> > > > fdt_appendprop_u32(fdt, offset, "phys",
> > > > fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/phy@10210000"))); /*
> append <&pciephy0> */
> > > > fdt_setprop(fdt, offset, "phy-names",
> > > > "cdns3,usb2-phy\0cdns3,usb3-phy",
> > > > sizeof("cdns3,usb2-phy\0cdns3,usb3-phy"));
> > > > fdt_setprop_string(fdt, offset, "dr_mode", "host");
> > > >
> > > > I have made some mistake for devicetree and USB2.0 with keeping
> > > > pcie0 (not disable)? or is there a problem with the implementation?
> > > >
> > > > Best regards, -E Shattow
> > >
>
> > I don’t have a Milk-V CM board. So I just can test this code to Star64.
> > Thanks. I will test this and add the code to board_fixup_star64().
>
> Can you try to configure in USB2.0-only mode on Star64? Do you see the same
> problem with "load access fault"?
>
Yes ，USB 2.0 only can work.
> ...snip...
>
> Same devicetree fixup code but separated some of the statements to multiple
> lines:
>
> https://paste.debian.net/1324036/
>
> ```
Now I can see the issue,Usb 2.0 host can work in Milk-V CM, but PCIe can not work.
Is that correct?
The PCIe in CM board is PCIe0， The PCIe1 is not used. So I think
disable PCIe1 node and just set USB 2.0 to host is OK.
milkV CM PCIe0 setting is the same with VisionFive v2.
The USB 3.0 setting should not be added.
This USB 3.0 setting. Should NOT be added to Milk-V CM board.
&pciephy0 {
starfive,sys-syscon = <&sys_syscon 0x18>;
starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
status = "okay";
};
&usb_cdns3 {
phys = <&usbphy0>, <&pciephy0>;
phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
dr_mode = "host";
status = "okay";
};
> diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
> index b794b73b6b..b4b0930e75 100644
> --- a/board/starfive/visionfive2/spl.c
> +++ b/board/starfive/visionfive2/spl.c
> @@ -123,6 +123,53 @@ static const struct starfive_vf2_pro star64_pine64[] = {
> "tx-internal-delay-ps", "300"},
> };
>
> +void spl_fdt_fixup_jh7110_cadence_usb3_host(void *fdt) { int offset;
> + u32 phandle;
> +
> + offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /* &sysgpio */
> + fdt_add_subnode(fdt, offset, "usb0-0"); fdt_setprop_string(fdt,
> + fdt_path_offset(fdt, "/__symbols__"),
> "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> + offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0"); /*
> + usb_pins */ fdt_create_phandle(fdt, offset); fdt_add_subnode(fdt,
> + offset, "driver-vbus-pin"); offset = fdt_path_offset(fdt,
> + "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> + fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /* GPIOMUX(25,
> GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */
> + fdt_setprop_empty(fdt, offset, "bias-disable"); fdt_setprop_empty(fdt,
> + offset, "input-disable"); fdt_setprop_empty(fdt, offset,
> + "input-schmitt-disable"); fdt_setprop_u32(fdt, offset, "slew-rate",
> + 0);
> +
> + offset = fdt_path_offset(fdt, "/soc/pcie@2b000000"); /* &pcie0 */
> + fdt_setprop_string(fdt, offset, "status", "disabled");
> +
> + offset = fdt_path_offset(fdt, "/soc/phy@10210000"); /* &pciephy0 */
> + phandle = fdt_get_phandle(fdt, fdt_path_offset(fdt,
> "/soc/sys_syscon@13030000")); /* = <&sys_syscon> */
> + fdt_setprop_u32(fdt, offset, "starfive,sys-syscon", phandle);
> + fdt_appendprop_u32(fdt, offset, "starfive,sys-syscon", 0x18); /*
> append <magic number> */
> + phandle = fdt_get_phandle(fdt, fdt_path_offset(fdt,
> "/soc/stg_syscon@10240000")); /* = <&stg_syscon> */
> + fdt_setprop_u32(fdt, offset, "starfive,stg-syscon", phandle);
> + fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x148); /*
> append <magic number> */
> + fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x1f4); /*
> append <magic number> */
> + fdt_setprop_string(fdt, offset, "status", "okay");
> +
> + offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */
> + fdt_setprop_string(fdt, offset, "pinctrl-names", "default"); phandle =
> + fdt_get_phandle(fdt, fdt_path_offset(fdt,
> "/soc/pinctrl@13040000/usb0-0")); /* <&usb_pins> */
> + fdt_setprop_u32(fdt, offset, "pinctrl-0", phandle);
> + fdt_setprop_string(fdt, offset, "status", "okay");
> +
> + offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /*
> + &usb_cdns3 */ phandle = fdt_get_phandle(fdt, fdt_path_offset(fdt,
> "/soc/phy@10200000")); /* = <&usbphy0> */
> + fdt_setprop_u32(fdt, offset, "phys", phandle); phandle =
> + fdt_get_phandle(fdt, fdt_path_offset(fdt,
> "/soc/phy@10210000")); /* append <&pciephy0> */
> + fdt_appendprop_u32(fdt, offset, "phys", phandle);
> +fdt_setprop_string(fdt, offset, "phy-names", "cdns3,usb2-phy");
> +fdt_appendprop_string(fdt, offset, "phy-names", "cdns3,usb3-phy");
> +fdt_setprop_string(fdt, offset, "dr_mode", "host"); }
> +
> void spl_fdt_fixup_mars(void *fdt)
> {
> static const char compat[] = "milkv,mars\0starfive,jh7110"; @@ -335,6
> +382,8 @@ void spl_fdt_fixup_star64(void *fdt)
> break;
> }
> }
> +
> + spl_fdt_fixup_jh7110_cadence_usb3_host(fdt);
> }
>
> void spl_perform_fixups(struct spl_image_info *spl_image) ```
>
> I think there is missing some of the USB2.0-only logic in your patch.
> Can you try some more testing to understand why this fault happens here?
>
> Thanks,
>
> -E
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node
2024-07-23 10:16 ` Minda Chen
@ 2024-07-23 13:05 ` E Shattow
2024-07-24 3:24 ` Minda Chen
0 siblings, 1 reply; 19+ messages in thread
From: E Shattow @ 2024-07-23 13:05 UTC (permalink / raw)
To: Minda Chen
Cc: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang, u-boot@lists.denx.de,
Heinrich Schuchardt, Simon Glass
On Tue, Jul 23, 2024 at 3:16 AM Minda Chen <minda.chen@starfivetech.com> wrote:
>
>
>
> >
> > On Mon, Jul 22, 2024 at 6:29 PM Minda Chen <minda.chen@starfivetech.com>
> > wrote:
> > >
> > >
> > >
> > > >
> > > > On Sat, Jul 20, 2024 at 6:47 PM E Shattow <lucent@gmail.com> wrote:
> > > > >
> > > > > Hi, I am testing on Milk-V Mars CM Lite, and I add to these
> > > > > devicetree changes at runtime from
> > > > > board/starfive/visionfive2/spl.c
> > > > >
> > > > > On Thu, Jul 18, 2024 at 6:38 PM Minda Chen
> > > > > <minda.chen@starfivetech.com>
> > > > wrote:
> > > > > >
> > > > > > Add Jh7110 Cadence USB dts node, Visionfive2 default setting is
> > > > > > USB
> > > > > > 2.0 device.
> > > > > >
> > > > > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> > > > > > ---
> > > > > > .../dts/jh7110-starfive-visionfive-2.dtsi | 5 ++
> > > > > > arch/riscv/dts/jh7110.dtsi | 52
> > > > +++++++++++++++++++
> > > > > > 2 files changed, 57 insertions(+)
> > > > > >
> > > > > > diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > > b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > > index e11babc1cd..44785bbee3 100644
> > > > > > --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > > +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > > @@ -378,3 +378,8 @@
> > > > > > };
> > > > > > };
> > > > > > };
> > > > > > +
> > > > > > +&usb_cdns3 {
> > > > > > + dr_mode = "peripheral";
> > > > > > + status = "okay";
> > > > > > +};
> > > > > > diff --git a/arch/riscv/dts/jh7110.dtsi
> > > > > > b/arch/riscv/dts/jh7110.dtsi index 2cdc683d49..1eee924e1d 100644
> > > > > > --- a/arch/riscv/dts/jh7110.dtsi
> > > > > > +++ b/arch/riscv/dts/jh7110.dtsi
> > > > > > @@ -371,6 +371,58 @@
> > > > > > status = "disabled";
> > > > > > };
> > > > > >
> > > > > > + usb0: usb@10100000 {
> > > > > > + compatible = "starfive,jh7110-usb";
> > > > > > + ranges = <0x0 0x0 0x10100000 0x100000>;
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <1>;
> > > > > > + starfive,stg-syscon = <&stg_syscon 0x4>;
> > > > > > + clocks = <&stgcrg
> > > > JH7110_STGCLK_USB_LPM>,
> > > > > > + <&stgcrg
> > > > JH7110_STGCLK_USB_STB>,
> > > > > > + <&stgcrg
> > > > JH7110_STGCLK_USB_APB>,
> > > > > > + <&stgcrg
> > > > JH7110_STGCLK_USB_AXI>,
> > > > > > + <&stgcrg
> > > > JH7110_STGCLK_USB_UTMI_APB>;
> > > > > > + clock-names = "lpm", "stb", "apb",
> > > > > > + "axi",
> > > > "utmi_apb";
> > > > > > + resets = <&stgcrg
> > > > JH7110_STGRST_USB_PWRUP>,
> > > > > > + <&stgcrg
> > > > JH7110_STGRST_USB_APB>,
> > > > > > + <&stgcrg
> > > > JH7110_STGRST_USB_AXI>,
> > > > > > + <&stgcrg
> > > > JH7110_STGRST_USB_UTMI_APB>;
> > > > > > + reset-names = "pwrup", "apb", "axi",
> > > > > > + "utmi_apb";
> > > > > > +
> > > > > > + usb_cdns3: usb@0 {
> > > > > > + compatible = "cdns,usb3";
> > > > > > + reg = <0x0 0x10000>,
> > > > > > + <0x10000 0x10000>,
> > > > > > + <0x20000 0x10000>;
> > > > > > + reg-names = "otg", "xhci",
> > "dev";
> > > > > > + interrupts = <100>, <108>,
> > <110>;
> > > > > > + interrupt-names = "host",
> > > > "peripheral", "otg";
> > > > > > + phys = <&usbphy0>;
> > > > > > + phy-names = "cdns3,usb2-phy";
> > > > > > + };
> > > > > > + };
> > > > > > +
> > > > > > + usbphy0: phy@10200000 {
> > > > > > + compatible = "starfive,jh7110-usb-phy";
> > > > > > + reg = <0x0 0x10200000 0x0 0x10000>;
> > > > > > + clocks = <&syscrg
> > > > JH7110_SYSCLK_USB_125M>,
> > > > > > + <&stgcrg
> > > > JH7110_STGCLK_USB_APP_125>;
> > > > > > + clock-names = "125m", "app_125m";
> > > > > > + #phy-cells = <0>;
> > > > > > + };
> > > > > > +
> > > > > > + pciephy0: phy@10210000 {
> > > > > > + compatible = "starfive,jh7110-pcie-phy";
> > > > > > + reg = <0x0 0x10210000 0x0 0x10000>;
> > > > > > + #phy-cells = <0>;
> > > > > > + };
> > > > > > +
> > > > > > + pciephy1: phy@10220000 {
> > > > > > + compatible = "starfive,jh7110-pcie-phy";
> > > > > > + reg = <0x0 0x10220000 0x0 0x10000>;
> > > > > > + #phy-cells = <0>;
> > > > > > + };
> > > > > > +
> > > > > > stgcrg: clock-controller@10230000 {
> > > > > > compatible = "starfive,jh7110-stgcrg";
> > > > > > reg = <0x0 0x10230000 0x0 0x10000>;
> > > > > > --
> > > > > > 2.17.1
> > > > > >
> > > > >
> > > > > Access fault
> > > > >
> > > > > starting USB...
> > > > > Bus usb@0: cdns-usb3-host usb@0: set 1 has failed, back to 0
> > > > > scanning bus usb@0 for devices... Unhandled exception:
> > > > > Load
> > > > access fault
> > > > > EPC: 00000000fff85ce2 RA: 00000000fff85cdc TVAL:
> > > > 0000000000000004
> > > > > EPC: 0000000040246ce2 RA: 0000000040246cdc reloc adjusted
> > > > >
> > > > > Code: 9863 3ee7 8526 f0ef c37f 651c 3a03 0105 (43dc)
> > > > >
> > > > >
> > > > > resetting ...
> > > > >
> > > > > when I add only these:
> > > > >
> > > > > int offset;
> > > > >
> > > > > offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /*
> > > > &sysgpio */
> > > > > fdt_add_subnode(fdt, offset, "usb0-0");
> > > > > fdt_setprop_string(fdt, fdt_path_offset(fdt,
> > > > > "/__symbols__"), "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> > > > > offset = fdt_path_offset(fdt,
> > > > > "/soc/pinctrl@13040000/usb0-0");
> > > > > /* usb_pins */
> > > > > fdt_create_phandle(fdt, offset);
> > > > > fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> > > > > offset = fdt_path_offset(fdt,
> > > > > "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> > > > > fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
> > > > > GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE,
> > GPI_NONE)
> > > > */
> > > > > fdt_setprop_empty(fdt, offset, "bias-disable");
> > > > > fdt_setprop_empty(fdt, offset, "input-disable");
> > > > > fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> > > > > fdt_setprop_u32(fdt, offset, "slew-rate", 0);
> > > > >
> > > > > offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0
> > */
> > > > > fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> > > > > fdt_setprop_u32(fdt, offset, "pinctrl-0",
> > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > "/soc/pinctrl@13040000/usb0-0")));
> > > > > fdt_setprop_string(fdt, offset, "status", "okay");
> > > > >
> > > > > offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0");
> > > > > /*
> > > > > &usb_cdns3 */
> > > > > fdt_setprop_string(fdt, offset, "dr_mode", "host");
> > > > >
> > > > > Success USB is working but PCI disabled if instead I add all of this:
> > > > >
> >
> > > I checked t Milk-V CM board do not contain USB3.0 host So I think the
> > > USB 3.0 configuration is not required.
> >
> > I agree it should be USB 2.0, but with your patch this is the only configuration
> > that does anything successful with USB2.0 or 3.0
> >
> >
> > >
> > > > > int offset;
> > > > >
> > > > > offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /*
> > > > &sysgpio */
> > > > > fdt_add_subnode(fdt, offset, "usb0-0");
> > > > > fdt_setprop_string(fdt, fdt_path_offset(fdt,
> > > > > "/__symbols__"), "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> > > > > offset = fdt_path_offset(fdt,
> > > > > "/soc/pinctrl@13040000/usb0-0");
> > > > > /* usb_pins */
> > > > > fdt_create_phandle(fdt, offset);
> > > > > fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> > > > > offset = fdt_path_offset(fdt,
> > > > > "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> > > > > fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
> > > > > GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE,
> > GPI_NONE)
> > > > */
> > > > > fdt_setprop_empty(fdt, offset, "bias-disable");
> > > > > fdt_setprop_empty(fdt, offset, "input-disable");
> > > > > fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> > > > > fdt_setprop_u32(fdt, offset, "slew-rate", 0);
> > > > >
> > > > > offset = fdt_path_offset(fdt, "/soc/pcie@2b000000"); /* &pcie0
> > */
> > > > > fdt_setprop_string(fdt, offset, "status", "disabled");
> > > > >
> > > > > offset = fdt_path_offset(fdt, "/soc/phy@10210000"); /*
> > > > > &pciephy0
> > > > */
> > > > > fdt_setprop_u32(fdt, offset, "starfive,sys-syscon",
> > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > > > "/soc/sys_syscon@13030000"))); /* = <&sys_syscon> */
> > > > > fdt_appendprop_u32(fdt, offset, "starfive,sys-syscon",
> > > > > 0x18);
> > > > > /* append <magic number> */
> > > > > fdt_setprop_u32(fdt, offset, "starfive,stg-syscon",
> > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > > > "/soc/stg_syscon@10240000"))); /* = <&stg_syscon> */
> > > > > fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon",
> > > > > 0x148);
> > > > > /* append <magic number> */
> > > > > fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon",
> > > > > 0x1f4);
> > > > > /* append <magic number> */
> > > > > fdt_setprop_string(fdt, offset, "status", "okay");
> > > > >
> > > > > offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0
> > */
> > > > > fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> > > > > fdt_setprop_u32(fdt, offset, "pinctrl-0",
> > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > "/soc/pinctrl@13040000/usb0-0")));
> > > > > fdt_setprop_string(fdt, offset, "status", "okay");
> > > > >
> > > > > offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0");
> > > > > /*
> > > > > &usb_cdns3 */
> > > > > fdt_setprop_u32(fdt, offset, "phys",
> > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/phy@10200000")));
> > > > > /* = <&usbphy0> */
> > > > > fdt_appendprop_u32(fdt, offset, "phys",
> > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/phy@10210000"))); /*
> > append <&pciephy0> */
> > > > > fdt_setprop(fdt, offset, "phy-names",
> > > > > "cdns3,usb2-phy\0cdns3,usb3-phy",
> > > > > sizeof("cdns3,usb2-phy\0cdns3,usb3-phy"));
> > > > > fdt_setprop_string(fdt, offset, "dr_mode", "host");
> > > > >
> > > > > I have made some mistake for devicetree and USB2.0 with keeping
> > > > > pcie0 (not disable)? or is there a problem with the implementation?
> > > > >
> > > > > Best regards, -E Shattow
> > > >
> >
> > > I don’t have a Milk-V CM board. So I just can test this code to Star64.
> > > Thanks. I will test this and add the code to board_fixup_star64().
> >
> > Can you try to configure in USB2.0-only mode on Star64? Do you see the same
> > problem with "load access fault"?
> >
> Yes ，USB 2.0 only can work.
> > ...snip...
> >
> > Same devicetree fixup code but separated some of the statements to multiple
> > lines:
> >
> > https://paste.debian.net/1324036/
> >
> > ```
> Now I can see the issue,Usb 2.0 host can work in Milk-V CM, but PCIe can not work.
> Is that correct?
> The PCIe in CM board is PCIe0， The PCIe1 is not used. So I think
> disable PCIe1 node and just set USB 2.0 to host is OK.
> milkV CM PCIe0 setting is the same with VisionFive v2.
> The USB 3.0 setting should not be added.
>
> This USB 3.0 setting. Should NOT be added to Milk-V CM board.
> &pciephy0 {
> starfive,sys-syscon = <&sys_syscon 0x18>;
> starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
> status = "okay";
> };
>
> &usb_cdns3 {
> phys = <&usbphy0>, <&pciephy0>;
> phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
> dr_mode = "host";
> status = "okay";
> };
>
Here is Mars CM Lite:
StarFive # pci
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
00.00.00 0x1556 0x1111 Bridge device 0x04
01.00.00 0x10ec 0x8168 Network controller 0x00
02.00.00 0x1556 0x1111 Bridge device 0x04
This is the DFRobot Mini Router carrier and the Mars CM Lite. There
is a network interface connected to PCIe.
When I apply this fixup:
void spl_fdt_fixup_jh7110_cadence_usb2_host(void *fdt)
{
int offset;
u32 phandle;
offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /* &sysgpio */
fdt_add_subnode(fdt, offset, "usb0-0");
fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),
"usb_pins", "/soc/pinctrl@13040000/usb0-0");
offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0");
/* usb_pins */
fdt_create_phandle(fdt, offset);
fdt_add_subnode(fdt, offset, "driver-vbus-pin");
offset = fdt_path_offset(fdt,
"/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */
fdt_setprop_empty(fdt, offset, "bias-disable");
fdt_setprop_empty(fdt, offset, "input-disable");
fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
fdt_setprop_u32(fdt, offset, "slew-rate", 0);
offset = fdt_path_offset(fdt, "/soc/pcie@2c000000"); /* &pcie1 */
fdt_setprop_string(fdt, offset, "status", "disabled");
offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */
fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
phandle = fdt_get_phandle(fdt, fdt_path_offset(fdt,
"/soc/pinctrl@13040000/usb0-0")); /* <&usb_pins> */
fdt_setprop_u32(fdt, offset, "pinctrl-0", phandle);
fdt_setprop_string(fdt, offset, "status", "okay");
offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /*
&usb_cdns3 */
fdt_setprop_string(fdt, offset, "dr_mode", "host");
}
at the last instruction of spl_fdt_fixup_mars_cm() then there is this
error I am telling you about:
U-Boot 2024.07-00971-g8eed381de5ef-dirty (Jul 23 2024 - 05:49:09 -0700)
CPU: sifive,u74-mc
Model: Milk-V Mars CM Lite
DRAM: 4 GiB
Core: 139 devices, 29 uclasses, devicetree: board
WDT: Not starting watchdog@13070000
MMC: mmc@16010000: 0, mmc@16020000: 1
Loading Environment from SPIFlash... SF: Detected gd25lq128 with page
size 256 Bytes, erase size 4 KiB, total 16 MiB
OK
StarFive EEPROM format v2
--------EEPROM INFO--------
Vendor : MILK-V
Product full SN: MARC-V10-2340-D004E000-000006DF
data version: 0x2
PCB revision: 0xc1
BOM revision: A
Ethernet MAC0 address: 6c:cf:39:00:83:11
Ethernet MAC1 address: 6c:cf:39:00:83:12
--------EEPROM INFO--------
starfive_7110_pcie pcie@2b000000: Starfive PCIe bus probed.
PCI: Failed autoconfig bar 10
In: serial@10000000
Out: serial@10000000
Err: serial@10000000
Net: eth0: ethernet@16030000
Error: eth_rtl8169 No valid MAC address found.
starting USB...
Bus usb@0: cdns-usb3-host usb@0: set 1 has failed, back to 0
scanning bus usb@0 for devices... Unhandled exception: Load access fault
EPC: 00000000fff85b2e RA: 00000000fff85b28 TVAL: 0000000000000004
EPC: 0000000040246b2e RA: 0000000040246b28 reloc adjusted
Code: 9863 3ee7 8526 f0ef c37f 651c 3a03 0105 (43dc)
resetting ...
(C)StarFive
CCC
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node
2024-07-23 13:05 ` E Shattow
@ 2024-07-24 3:24 ` Minda Chen
2024-07-24 18:05 ` E Shattow
0 siblings, 1 reply; 19+ messages in thread
From: Minda Chen @ 2024-07-24 3:24 UTC (permalink / raw)
To: E Shattow
Cc: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang, u-boot@lists.denx.de,
Heinrich Schuchardt, Simon Glass
> -----邮件原件-----
> 发件人: E Shattow <lucent@gmail.com>
> 发送时间: 2024年7月23日 21:06
> 收件人: Minda Chen <minda.chen@starfivetech.com>
> 抄送: Marek Vasut <marex@denx.de>; Tom Rini <trini@konsulko.com>; Roger
> Quadros <rogerq@kernel.org>; Neil Armstrong <neil.armstrong@linaro.org>;
> Alexey Romanov <avromanov@salutedevices.com>; Sumit Garg
> <sumit.garg@linaro.org>; Mark Kettenis <kettenis@openbsd.org>; Nishanth
> Menon <nm@ti.com>; Rick Chen <rick@andestech.com>; Leo Yu-Chi Liang
> <ycliang@andestech.com>; u-boot@lists.denx.de; Heinrich Schuchardt
> <xypron.glpk@gmx.de>; Simon Glass <sjg@chromium.org>
> 主题: Re: [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node
>
> On Tue, Jul 23, 2024 at 3:16 AM Minda Chen <minda.chen@starfivetech.com>
> wrote:
> >
> >
> >
> > >
> > > On Mon, Jul 22, 2024 at 6:29 PM Minda Chen
> > > <minda.chen@starfivetech.com>
> > > wrote:
> > > >
> > > >
> > > >
> > > > >
> > > > > On Sat, Jul 20, 2024 at 6:47 PM E Shattow <lucent@gmail.com> wrote:
> > > > > >
> > > > > > Hi, I am testing on Milk-V Mars CM Lite, and I add to these
> > > > > > devicetree changes at runtime from
> > > > > > board/starfive/visionfive2/spl.c
> > > > > >
> > > > > > On Thu, Jul 18, 2024 at 6:38 PM Minda Chen
> > > > > > <minda.chen@starfivetech.com>
> > > > > wrote:
> > > > > > >
> > > > > > > Add Jh7110 Cadence USB dts node, Visionfive2 default setting
> > > > > > > is USB
> > > > > > > 2.0 device.
> > > > > > >
> > > > > > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> > > > > > > ---
> > > > > > > .../dts/jh7110-starfive-visionfive-2.dtsi | 5 ++
> > > > > > > arch/riscv/dts/jh7110.dtsi | 52
> > > > > +++++++++++++++++++
> > > > > > > 2 files changed, 57 insertions(+)
> > > > > > >
> > > > > > > diff --git
> > > > > > > a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > > > b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > > > index e11babc1cd..44785bbee3 100644
> > > > > > > --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > > > +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > > > @@ -378,3 +378,8 @@
> > > > > > > };
> > > > > > > };
> > > > > > > };
> > > > > > > +
> > > > > > > +&usb_cdns3 {
> > > > > > > + dr_mode = "peripheral";
> > > > > > > + status = "okay";
> > > > > > > +};
> > > > > > > diff --git a/arch/riscv/dts/jh7110.dtsi
> > > > > > > b/arch/riscv/dts/jh7110.dtsi index 2cdc683d49..1eee924e1d
> > > > > > > 100644
> > > > > > > --- a/arch/riscv/dts/jh7110.dtsi
> > > > > > > +++ b/arch/riscv/dts/jh7110.dtsi
> > > > > > > @@ -371,6 +371,58 @@
> > > > > > > status = "disabled";
> > > > > > > };
> > > > > > >
> > > > > > > + usb0: usb@10100000 {
> > > > > > > + compatible = "starfive,jh7110-usb";
> > > > > > > + ranges = <0x0 0x0 0x10100000
> 0x100000>;
> > > > > > > + #address-cells = <1>;
> > > > > > > + #size-cells = <1>;
> > > > > > > + starfive,stg-syscon = <&stg_syscon
> 0x4>;
> > > > > > > + clocks = <&stgcrg
> > > > > JH7110_STGCLK_USB_LPM>,
> > > > > > > + <&stgcrg
> > > > > JH7110_STGCLK_USB_STB>,
> > > > > > > + <&stgcrg
> > > > > JH7110_STGCLK_USB_APB>,
> > > > > > > + <&stgcrg
> > > > > JH7110_STGCLK_USB_AXI>,
> > > > > > > + <&stgcrg
> > > > > JH7110_STGCLK_USB_UTMI_APB>;
> > > > > > > + clock-names = "lpm", "stb", "apb",
> > > > > > > + "axi",
> > > > > "utmi_apb";
> > > > > > > + resets = <&stgcrg
> > > > > JH7110_STGRST_USB_PWRUP>,
> > > > > > > + <&stgcrg
> > > > > JH7110_STGRST_USB_APB>,
> > > > > > > + <&stgcrg
> > > > > JH7110_STGRST_USB_AXI>,
> > > > > > > + <&stgcrg
> > > > > JH7110_STGRST_USB_UTMI_APB>;
> > > > > > > + reset-names = "pwrup", "apb", "axi",
> > > > > > > + "utmi_apb";
> > > > > > > +
> > > > > > > + usb_cdns3: usb@0 {
> > > > > > > + compatible = "cdns,usb3";
> > > > > > > + reg = <0x0 0x10000>,
> > > > > > > + <0x10000 0x10000>,
> > > > > > > + <0x20000 0x10000>;
> > > > > > > + reg-names = "otg", "xhci",
> > > "dev";
> > > > > > > + interrupts = <100>, <108>,
> > > <110>;
> > > > > > > + interrupt-names = "host",
> > > > > "peripheral", "otg";
> > > > > > > + phys = <&usbphy0>;
> > > > > > > + phy-names =
> "cdns3,usb2-phy";
> > > > > > > + };
> > > > > > > + };
> > > > > > > +
> > > > > > > + usbphy0: phy@10200000 {
> > > > > > > + compatible =
> "starfive,jh7110-usb-phy";
> > > > > > > + reg = <0x0 0x10200000 0x0 0x10000>;
> > > > > > > + clocks = <&syscrg
> > > > > JH7110_SYSCLK_USB_125M>,
> > > > > > > + <&stgcrg
> > > > > JH7110_STGCLK_USB_APP_125>;
> > > > > > > + clock-names = "125m", "app_125m";
> > > > > > > + #phy-cells = <0>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + pciephy0: phy@10210000 {
> > > > > > > + compatible =
> "starfive,jh7110-pcie-phy";
> > > > > > > + reg = <0x0 0x10210000 0x0 0x10000>;
> > > > > > > + #phy-cells = <0>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + pciephy1: phy@10220000 {
> > > > > > > + compatible =
> "starfive,jh7110-pcie-phy";
> > > > > > > + reg = <0x0 0x10220000 0x0 0x10000>;
> > > > > > > + #phy-cells = <0>;
> > > > > > > + };
> > > > > > > +
> > > > > > > stgcrg: clock-controller@10230000 {
> > > > > > > compatible = "starfive,jh7110-stgcrg";
> > > > > > > reg = <0x0 0x10230000 0x0 0x10000>;
> > > > > > > --
> > > > > > > 2.17.1
> > > > > > >
> > > > > >
> > > > > > Access fault
> > > > > >
> > > > > > starting USB...
> > > > > > Bus usb@0: cdns-usb3-host usb@0: set 1 has failed, back to
> 0
> > > > > > scanning bus usb@0 for devices... Unhandled exception:
> > > > > > Load
> > > > > access fault
> > > > > > EPC: 00000000fff85ce2 RA: 00000000fff85cdc TVAL:
> > > > > 0000000000000004
> > > > > > EPC: 0000000040246ce2 RA: 0000000040246cdc reloc
> > > > > > adjusted
> > > > > >
> > > > > > Code: 9863 3ee7 8526 f0ef c37f 651c 3a03 0105 (43dc)
> > > > > >
> > > > > >
> > > > > > resetting ...
> > > > > >
> > > > > > when I add only these:
> > > > > >
> > > > > > int offset;
> > > > > >
> > > > > > offset = fdt_path_offset(fdt,
> > > > > > "/soc/pinctrl@13040000"); /*
> > > > > &sysgpio */
> > > > > > fdt_add_subnode(fdt, offset, "usb0-0");
> > > > > > fdt_setprop_string(fdt, fdt_path_offset(fdt,
> > > > > > "/__symbols__"), "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> > > > > > offset = fdt_path_offset(fdt,
> > > > > > "/soc/pinctrl@13040000/usb0-0");
> > > > > > /* usb_pins */
> > > > > > fdt_create_phandle(fdt, offset);
> > > > > > fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> > > > > > offset = fdt_path_offset(fdt,
> > > > > > "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> > > > > > fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
> > > > > > GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE,
> > > GPI_NONE)
> > > > > */
> > > > > > fdt_setprop_empty(fdt, offset, "bias-disable");
> > > > > > fdt_setprop_empty(fdt, offset, "input-disable");
> > > > > > fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> > > > > > fdt_setprop_u32(fdt, offset, "slew-rate", 0);
> > > > > >
> > > > > > offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /*
> > > > > > &usb0
> > > */
> > > > > > fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> > > > > > fdt_setprop_u32(fdt, offset, "pinctrl-0",
> > > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > "/soc/pinctrl@13040000/usb0-0")));
> > > > > > fdt_setprop_string(fdt, offset, "status", "okay");
> > > > > >
> > > > > > offset = fdt_path_offset(fdt,
> > > > > > "/soc/usb@10100000/usb@0");
> > > > > > /*
> > > > > > &usb_cdns3 */
> > > > > > fdt_setprop_string(fdt, offset, "dr_mode", "host");
> > > > > >
> > > > > > Success USB is working but PCI disabled if instead I add all of this:
> > > > > >
> > >
> > > > I checked t Milk-V CM board do not contain USB3.0 host So I think
> > > > the USB 3.0 configuration is not required.
> > >
> > > I agree it should be USB 2.0, but with your patch this is the only
> > > configuration that does anything successful with USB2.0 or 3.0
> > >
> > >
> > > >
> > > > > > int offset;
> > > > > >
> > > > > > offset = fdt_path_offset(fdt,
> > > > > > "/soc/pinctrl@13040000"); /*
> > > > > &sysgpio */
> > > > > > fdt_add_subnode(fdt, offset, "usb0-0");
> > > > > > fdt_setprop_string(fdt, fdt_path_offset(fdt,
> > > > > > "/__symbols__"), "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> > > > > > offset = fdt_path_offset(fdt,
> > > > > > "/soc/pinctrl@13040000/usb0-0");
> > > > > > /* usb_pins */
> > > > > > fdt_create_phandle(fdt, offset);
> > > > > > fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> > > > > > offset = fdt_path_offset(fdt,
> > > > > > "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> > > > > > fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
> > > > > > GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE,
> > > GPI_NONE)
> > > > > */
> > > > > > fdt_setprop_empty(fdt, offset, "bias-disable");
> > > > > > fdt_setprop_empty(fdt, offset, "input-disable");
> > > > > > fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> > > > > > fdt_setprop_u32(fdt, offset, "slew-rate", 0);
> > > > > >
> > > > > > offset = fdt_path_offset(fdt, "/soc/pcie@2b000000");
> > > > > > /* &pcie0
> > > */
> > > > > > fdt_setprop_string(fdt, offset, "status", "disabled");
> > > > > >
> > > > > > offset = fdt_path_offset(fdt, "/soc/phy@10210000"); /*
> > > > > > &pciephy0
> > > > > */
> > > > > > fdt_setprop_u32(fdt, offset, "starfive,sys-syscon",
> > > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > > > > "/soc/sys_syscon@13030000"))); /* = <&sys_syscon> */
> > > > > > fdt_appendprop_u32(fdt, offset, "starfive,sys-syscon",
> > > > > > 0x18);
> > > > > > /* append <magic number> */
> > > > > > fdt_setprop_u32(fdt, offset, "starfive,stg-syscon",
> > > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > > > > "/soc/stg_syscon@10240000"))); /* = <&stg_syscon> */
> > > > > > fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon",
> > > > > > 0x148);
> > > > > > /* append <magic number> */
> > > > > > fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon",
> > > > > > 0x1f4);
> > > > > > /* append <magic number> */
> > > > > > fdt_setprop_string(fdt, offset, "status", "okay");
> > > > > >
> > > > > > offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /*
> > > > > > &usb0
> > > */
> > > > > > fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> > > > > > fdt_setprop_u32(fdt, offset, "pinctrl-0",
> > > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > "/soc/pinctrl@13040000/usb0-0")));
> > > > > > fdt_setprop_string(fdt, offset, "status", "okay");
> > > > > >
> > > > > > offset = fdt_path_offset(fdt,
> > > > > > "/soc/usb@10100000/usb@0");
> > > > > > /*
> > > > > > &usb_cdns3 */
> > > > > > fdt_setprop_u32(fdt, offset, "phys",
> > > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > > > > "/soc/phy@10200000")));
> > > > > > /* = <&usbphy0> */
> > > > > > fdt_appendprop_u32(fdt, offset, "phys",
> > > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > > > > "/soc/phy@10210000"))); /*
> > > append <&pciephy0> */
> > > > > > fdt_setprop(fdt, offset, "phy-names",
> > > > > > "cdns3,usb2-phy\0cdns3,usb3-phy",
> > > > > > sizeof("cdns3,usb2-phy\0cdns3,usb3-phy"));
> > > > > > fdt_setprop_string(fdt, offset, "dr_mode", "host");
> > > > > >
> > > > > > I have made some mistake for devicetree and USB2.0 with
> > > > > > keeping
> > > > > > pcie0 (not disable)? or is there a problem with the implementation?
> > > > > >
> > > > > > Best regards, -E Shattow
> > > > >
> > >
> > > > I don’t have a Milk-V CM board. So I just can test this code to Star64.
> > > > Thanks. I will test this and add the code to board_fixup_star64().
> > >
> > > Can you try to configure in USB2.0-only mode on Star64? Do you see
> > > the same problem with "load access fault"?
> > >
> > Yes ，USB 2.0 only can work.
> > > ...snip...
> > >
> > > Same devicetree fixup code but separated some of the statements to
> > > multiple
> > > lines:
> > >
> > > https://paste.debian.net/1324036/
> > >
> > > ```
> > Now I can see the issue,Usb 2.0 host can work in Milk-V CM, but PCIe can not
> work.
> > Is that correct?
> > The PCIe in CM board is PCIe0， The PCIe1 is not used. So I think
> > disable PCIe1 node and just set USB 2.0 to host is OK.
> > milkV CM PCIe0 setting is the same with VisionFive v2.
> > The USB 3.0 setting should not be added.
> >
> > This USB 3.0 setting. Should NOT be added to Milk-V CM board.
> > &pciephy0 {
> > starfive,sys-syscon = <&sys_syscon 0x18>;
> > starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
> > status = "okay";
> > };
> >
> > &usb_cdns3 {
> > phys = <&usbphy0>, <&pciephy0>;
> > phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
> > dr_mode = "host";
> > status = "okay";
> > };
> >
>
> Here is Mars CM Lite:
>
> StarFive # pci
> BusDevFun VendorId DeviceId Device Class Sub-Class
> _____________________________________________________________
> 00.00.00 0x1556 0x1111 Bridge device 0x04
> 01.00.00 0x10ec 0x8168 Network controller 0x00
> 02.00.00 0x1556 0x1111 Bridge device 0x04
>
> This is the DFRobot Mini Router carrier and the Mars CM Lite. There is a
> network interface connected to PCIe.
>
> When I apply this fixup:
>
> void spl_fdt_fixup_jh7110_cadence_usb2_host(void *fdt) {
> int offset;
> u32 phandle;
>
> offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /* &sysgpio
> */
> fdt_add_subnode(fdt, offset, "usb0-0");
> fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),
> "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0");
> /* usb_pins */
> fdt_create_phandle(fdt, offset);
> fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> offset = fdt_path_offset(fdt,
> "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /* GPIOMUX(25,
> GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */
> fdt_setprop_empty(fdt, offset, "bias-disable");
> fdt_setprop_empty(fdt, offset, "input-disable");
> fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> fdt_setprop_u32(fdt, offset, "slew-rate", 0);
>
> offset = fdt_path_offset(fdt, "/soc/pcie@2c000000"); /* &pcie1 */
> fdt_setprop_string(fdt, offset, "status", "disabled");
>
> offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */
> fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> phandle = fdt_get_phandle(fdt, fdt_path_offset(fdt,
> "/soc/pinctrl@13040000/usb0-0")); /* <&usb_pins> */
> fdt_setprop_u32(fdt, offset, "pinctrl-0", phandle);
> fdt_setprop_string(fdt, offset, "status", "okay");
>
> offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /*
> &usb_cdns3 */
> fdt_setprop_string(fdt, offset, "dr_mode", "host"); }
>
> at the last instruction of spl_fdt_fixup_mars_cm() then there is this error I am
> telling you about:
>
> U-Boot 2024.07-00971-g8eed381de5ef-dirty (Jul 23 2024 - 05:49:09 -0700)
>
> CPU: sifive,u74-mc
> Model: Milk-V Mars CM Lite
> DRAM: 4 GiB
> Core: 139 devices, 29 uclasses, devicetree: board
> WDT: Not starting watchdog@13070000
> MMC: mmc@16010000: 0, mmc@16020000: 1
> Loading Environment from SPIFlash... SF: Detected gd25lq128 with page size
> 256 Bytes, erase size 4 KiB, total 16 MiB OK StarFive EEPROM format v2
>
> --------EEPROM INFO--------
> Vendor : MILK-V
> Product full SN: MARC-V10-2340-D004E000-000006DF data version: 0x2 PCB
> revision: 0xc1 BOM revision: A Ethernet MAC0 address: 6c:cf:39:00:83:11
> Ethernet MAC1 address: 6c:cf:39:00:83:12 --------EEPROM INFO--------
>
> starfive_7110_pcie pcie@2b000000: Starfive PCIe bus probed.
> PCI: Failed autoconfig bar 10
> In: serial@10000000
> Out: serial@10000000
> Err: serial@10000000
> Net: eth0: ethernet@16030000
> Error: eth_rtl8169 No valid MAC address found.
>
> starting USB...
> Bus usb@0: cdns-usb3-host usb@0: set 1 has failed, back to 0 scanning bus
> usb@0 for devices... Unhandled exception: Load access fault
> EPC: 00000000fff85b2e RA: 00000000fff85b28 TVAL: 0000000000000004
> EPC: 0000000040246b2e RA: 0000000040246b28 reloc adjusted
>
> Code: 9863 3ee7 8526 f0ef c37f 651c 3a03 0105 (43dc)
>
>
> resetting ...
>
> (C)StarFive
> CCC
I can reproduce USB 2.0 only on Star64 now. I know this.
Next version I will fix this.
You can test with this patch to check whether can fix this.
diff --git a/drivers/phy/starfive/phy-jh7110-usb2.c b/drivers/phy/starfive/phy-jh7110-usb2.c
index d48c9f8a74..a09fb2efea 100644
--- a/drivers/phy/starfive/phy-jh7110-usb2.c
+++ b/drivers/phy/starfive/phy-jh7110-usb2.c
@@ -116,7 +116,7 @@ int jh7110_usb2_phy_probe(struct udevice *dev)
dev_err(dev, "Failed to get app 125m clock\n");
return PTR_ERR(phy->app_125m);
}
-
+ writel(BIT(17), 0x13030018);
return 0;
}
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node
2024-07-24 3:24 ` Minda Chen
@ 2024-07-24 18:05 ` E Shattow
0 siblings, 0 replies; 19+ messages in thread
From: E Shattow @ 2024-07-24 18:05 UTC (permalink / raw)
To: Minda Chen
Cc: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang, u-boot@lists.denx.de,
Heinrich Schuchardt, Simon Glass
On Tue, Jul 23, 2024 at 8:24 PM Minda Chen <minda.chen@starfivetech.com> wrote:
>
>
>
> > -----邮件原件-----
> > 发件人: E Shattow <lucent@gmail.com>
> > 发送时间: 2024年7月23日 21:06
> > 收件人: Minda Chen <minda.chen@starfivetech.com>
> > 抄送: Marek Vasut <marex@denx.de>; Tom Rini <trini@konsulko.com>; Roger
> > Quadros <rogerq@kernel.org>; Neil Armstrong <neil.armstrong@linaro.org>;
> > Alexey Romanov <avromanov@salutedevices.com>; Sumit Garg
> > <sumit.garg@linaro.org>; Mark Kettenis <kettenis@openbsd.org>; Nishanth
> > Menon <nm@ti.com>; Rick Chen <rick@andestech.com>; Leo Yu-Chi Liang
> > <ycliang@andestech.com>; u-boot@lists.denx.de; Heinrich Schuchardt
> > <xypron.glpk@gmx.de>; Simon Glass <sjg@chromium.org>
> > 主题: Re: [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node
> >
> > On Tue, Jul 23, 2024 at 3:16 AM Minda Chen <minda.chen@starfivetech.com>
> > wrote:
> > >
> > >
> > >
> > > >
> > > > On Mon, Jul 22, 2024 at 6:29 PM Minda Chen
> > > > <minda.chen@starfivetech.com>
> > > > wrote:
> > > > >
> > > > >
> > > > >
> > > > > >
> > > > > > On Sat, Jul 20, 2024 at 6:47 PM E Shattow <lucent@gmail.com> wrote:
> > > > > > >
> > > > > > > Hi, I am testing on Milk-V Mars CM Lite, and I add to these
> > > > > > > devicetree changes at runtime from
> > > > > > > board/starfive/visionfive2/spl.c
> > > > > > >
> > > > > > > On Thu, Jul 18, 2024 at 6:38 PM Minda Chen
> > > > > > > <minda.chen@starfivetech.com>
> > > > > > wrote:
> > > > > > > >
> > > > > > > > Add Jh7110 Cadence USB dts node, Visionfive2 default setting
> > > > > > > > is USB
> > > > > > > > 2.0 device.
> > > > > > > >
> > > > > > > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> > > > > > > > ---
> > > > > > > > .../dts/jh7110-starfive-visionfive-2.dtsi | 5 ++
> > > > > > > > arch/riscv/dts/jh7110.dtsi | 52
> > > > > > +++++++++++++++++++
> > > > > > > > 2 files changed, 57 insertions(+)
> > > > > > > >
> > > > > > > > diff --git
> > > > > > > > a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > > > > b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > > > > index e11babc1cd..44785bbee3 100644
> > > > > > > > --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > > > > +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > > > > @@ -378,3 +378,8 @@
> > > > > > > > };
> > > > > > > > };
> > > > > > > > };
> > > > > > > > +
> > > > > > > > +&usb_cdns3 {
> > > > > > > > + dr_mode = "peripheral";
> > > > > > > > + status = "okay";
> > > > > > > > +};
> > > > > > > > diff --git a/arch/riscv/dts/jh7110.dtsi
> > > > > > > > b/arch/riscv/dts/jh7110.dtsi index 2cdc683d49..1eee924e1d
> > > > > > > > 100644
> > > > > > > > --- a/arch/riscv/dts/jh7110.dtsi
> > > > > > > > +++ b/arch/riscv/dts/jh7110.dtsi
> > > > > > > > @@ -371,6 +371,58 @@
> > > > > > > > status = "disabled";
> > > > > > > > };
> > > > > > > >
> > > > > > > > + usb0: usb@10100000 {
> > > > > > > > + compatible = "starfive,jh7110-usb";
> > > > > > > > + ranges = <0x0 0x0 0x10100000
> > 0x100000>;
> > > > > > > > + #address-cells = <1>;
> > > > > > > > + #size-cells = <1>;
> > > > > > > > + starfive,stg-syscon = <&stg_syscon
> > 0x4>;
> > > > > > > > + clocks = <&stgcrg
> > > > > > JH7110_STGCLK_USB_LPM>,
> > > > > > > > + <&stgcrg
> > > > > > JH7110_STGCLK_USB_STB>,
> > > > > > > > + <&stgcrg
> > > > > > JH7110_STGCLK_USB_APB>,
> > > > > > > > + <&stgcrg
> > > > > > JH7110_STGCLK_USB_AXI>,
> > > > > > > > + <&stgcrg
> > > > > > JH7110_STGCLK_USB_UTMI_APB>;
> > > > > > > > + clock-names = "lpm", "stb", "apb",
> > > > > > > > + "axi",
> > > > > > "utmi_apb";
> > > > > > > > + resets = <&stgcrg
> > > > > > JH7110_STGRST_USB_PWRUP>,
> > > > > > > > + <&stgcrg
> > > > > > JH7110_STGRST_USB_APB>,
> > > > > > > > + <&stgcrg
> > > > > > JH7110_STGRST_USB_AXI>,
> > > > > > > > + <&stgcrg
> > > > > > JH7110_STGRST_USB_UTMI_APB>;
> > > > > > > > + reset-names = "pwrup", "apb", "axi",
> > > > > > > > + "utmi_apb";
> > > > > > > > +
> > > > > > > > + usb_cdns3: usb@0 {
> > > > > > > > + compatible = "cdns,usb3";
> > > > > > > > + reg = <0x0 0x10000>,
> > > > > > > > + <0x10000 0x10000>,
> > > > > > > > + <0x20000 0x10000>;
> > > > > > > > + reg-names = "otg", "xhci",
> > > > "dev";
> > > > > > > > + interrupts = <100>, <108>,
> > > > <110>;
> > > > > > > > + interrupt-names = "host",
> > > > > > "peripheral", "otg";
> > > > > > > > + phys = <&usbphy0>;
> > > > > > > > + phy-names =
> > "cdns3,usb2-phy";
> > > > > > > > + };
> > > > > > > > + };
> > > > > > > > +
> > > > > > > > + usbphy0: phy@10200000 {
> > > > > > > > + compatible =
> > "starfive,jh7110-usb-phy";
> > > > > > > > + reg = <0x0 0x10200000 0x0 0x10000>;
> > > > > > > > + clocks = <&syscrg
> > > > > > JH7110_SYSCLK_USB_125M>,
> > > > > > > > + <&stgcrg
> > > > > > JH7110_STGCLK_USB_APP_125>;
> > > > > > > > + clock-names = "125m", "app_125m";
> > > > > > > > + #phy-cells = <0>;
> > > > > > > > + };
> > > > > > > > +
> > > > > > > > + pciephy0: phy@10210000 {
> > > > > > > > + compatible =
> > "starfive,jh7110-pcie-phy";
> > > > > > > > + reg = <0x0 0x10210000 0x0 0x10000>;
> > > > > > > > + #phy-cells = <0>;
> > > > > > > > + };
> > > > > > > > +
> > > > > > > > + pciephy1: phy@10220000 {
> > > > > > > > + compatible =
> > "starfive,jh7110-pcie-phy";
> > > > > > > > + reg = <0x0 0x10220000 0x0 0x10000>;
> > > > > > > > + #phy-cells = <0>;
> > > > > > > > + };
> > > > > > > > +
> > > > > > > > stgcrg: clock-controller@10230000 {
> > > > > > > > compatible = "starfive,jh7110-stgcrg";
> > > > > > > > reg = <0x0 0x10230000 0x0 0x10000>;
> > > > > > > > --
> > > > > > > > 2.17.1
> > > > > > > >
> > > > > > >
> > > > > > > Access fault
> > > > > > >
> > > > > > > starting USB...
> > > > > > > Bus usb@0: cdns-usb3-host usb@0: set 1 has failed, back to
> > 0
> > > > > > > scanning bus usb@0 for devices... Unhandled exception:
> > > > > > > Load
> > > > > > access fault
> > > > > > > EPC: 00000000fff85ce2 RA: 00000000fff85cdc TVAL:
> > > > > > 0000000000000004
> > > > > > > EPC: 0000000040246ce2 RA: 0000000040246cdc reloc
> > > > > > > adjusted
> > > > > > >
> > > > > > > Code: 9863 3ee7 8526 f0ef c37f 651c 3a03 0105 (43dc)
> > > > > > >
> > > > > > >
> > > > > > > resetting ...
> > > > > > >
> > > > > > > when I add only these:
> > > > > > >
> > > > > > > int offset;
> > > > > > >
> > > > > > > offset = fdt_path_offset(fdt,
> > > > > > > "/soc/pinctrl@13040000"); /*
> > > > > > &sysgpio */
> > > > > > > fdt_add_subnode(fdt, offset, "usb0-0");
> > > > > > > fdt_setprop_string(fdt, fdt_path_offset(fdt,
> > > > > > > "/__symbols__"), "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> > > > > > > offset = fdt_path_offset(fdt,
> > > > > > > "/soc/pinctrl@13040000/usb0-0");
> > > > > > > /* usb_pins */
> > > > > > > fdt_create_phandle(fdt, offset);
> > > > > > > fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> > > > > > > offset = fdt_path_offset(fdt,
> > > > > > > "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> > > > > > > fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
> > > > > > > GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE,
> > > > GPI_NONE)
> > > > > > */
> > > > > > > fdt_setprop_empty(fdt, offset, "bias-disable");
> > > > > > > fdt_setprop_empty(fdt, offset, "input-disable");
> > > > > > > fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> > > > > > > fdt_setprop_u32(fdt, offset, "slew-rate", 0);
> > > > > > >
> > > > > > > offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /*
> > > > > > > &usb0
> > > > */
> > > > > > > fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> > > > > > > fdt_setprop_u32(fdt, offset, "pinctrl-0",
> > > > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > > "/soc/pinctrl@13040000/usb0-0")));
> > > > > > > fdt_setprop_string(fdt, offset, "status", "okay");
> > > > > > >
> > > > > > > offset = fdt_path_offset(fdt,
> > > > > > > "/soc/usb@10100000/usb@0");
> > > > > > > /*
> > > > > > > &usb_cdns3 */
> > > > > > > fdt_setprop_string(fdt, offset, "dr_mode", "host");
> > > > > > >
> > > > > > > Success USB is working but PCI disabled if instead I add all of this:
> > > > > > >
> > > >
> > > > > I checked t Milk-V CM board do not contain USB3.0 host So I think
> > > > > the USB 3.0 configuration is not required.
> > > >
> > > > I agree it should be USB 2.0, but with your patch this is the only
> > > > configuration that does anything successful with USB2.0 or 3.0
> > > >
> > > >
> > > > >
> > > > > > > int offset;
> > > > > > >
> > > > > > > offset = fdt_path_offset(fdt,
> > > > > > > "/soc/pinctrl@13040000"); /*
> > > > > > &sysgpio */
> > > > > > > fdt_add_subnode(fdt, offset, "usb0-0");
> > > > > > > fdt_setprop_string(fdt, fdt_path_offset(fdt,
> > > > > > > "/__symbols__"), "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> > > > > > > offset = fdt_path_offset(fdt,
> > > > > > > "/soc/pinctrl@13040000/usb0-0");
> > > > > > > /* usb_pins */
> > > > > > > fdt_create_phandle(fdt, offset);
> > > > > > > fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> > > > > > > offset = fdt_path_offset(fdt,
> > > > > > > "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> > > > > > > fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
> > > > > > > GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE,
> > > > GPI_NONE)
> > > > > > */
> > > > > > > fdt_setprop_empty(fdt, offset, "bias-disable");
> > > > > > > fdt_setprop_empty(fdt, offset, "input-disable");
> > > > > > > fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> > > > > > > fdt_setprop_u32(fdt, offset, "slew-rate", 0);
> > > > > > >
> > > > > > > offset = fdt_path_offset(fdt, "/soc/pcie@2b000000");
> > > > > > > /* &pcie0
> > > > */
> > > > > > > fdt_setprop_string(fdt, offset, "status", "disabled");
> > > > > > >
> > > > > > > offset = fdt_path_offset(fdt, "/soc/phy@10210000"); /*
> > > > > > > &pciephy0
> > > > > > */
> > > > > > > fdt_setprop_u32(fdt, offset, "starfive,sys-syscon",
> > > > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > > > > > "/soc/sys_syscon@13030000"))); /* = <&sys_syscon> */
> > > > > > > fdt_appendprop_u32(fdt, offset, "starfive,sys-syscon",
> > > > > > > 0x18);
> > > > > > > /* append <magic number> */
> > > > > > > fdt_setprop_u32(fdt, offset, "starfive,stg-syscon",
> > > > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > > > > > "/soc/stg_syscon@10240000"))); /* = <&stg_syscon> */
> > > > > > > fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon",
> > > > > > > 0x148);
> > > > > > > /* append <magic number> */
> > > > > > > fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon",
> > > > > > > 0x1f4);
> > > > > > > /* append <magic number> */
> > > > > > > fdt_setprop_string(fdt, offset, "status", "okay");
> > > > > > >
> > > > > > > offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /*
> > > > > > > &usb0
> > > > */
> > > > > > > fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> > > > > > > fdt_setprop_u32(fdt, offset, "pinctrl-0",
> > > > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > > "/soc/pinctrl@13040000/usb0-0")));
> > > > > > > fdt_setprop_string(fdt, offset, "status", "okay");
> > > > > > >
> > > > > > > offset = fdt_path_offset(fdt,
> > > > > > > "/soc/usb@10100000/usb@0");
> > > > > > > /*
> > > > > > > &usb_cdns3 */
> > > > > > > fdt_setprop_u32(fdt, offset, "phys",
> > > > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > > > > > "/soc/phy@10200000")));
> > > > > > > /* = <&usbphy0> */
> > > > > > > fdt_appendprop_u32(fdt, offset, "phys",
> > > > > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > > > > > "/soc/phy@10210000"))); /*
> > > > append <&pciephy0> */
> > > > > > > fdt_setprop(fdt, offset, "phy-names",
> > > > > > > "cdns3,usb2-phy\0cdns3,usb3-phy",
> > > > > > > sizeof("cdns3,usb2-phy\0cdns3,usb3-phy"));
> > > > > > > fdt_setprop_string(fdt, offset, "dr_mode", "host");
> > > > > > >
> > > > > > > I have made some mistake for devicetree and USB2.0 with
> > > > > > > keeping
> > > > > > > pcie0 (not disable)? or is there a problem with the implementation?
> > > > > > >
> > > > > > > Best regards, -E Shattow
> > > > > >
> > > >
> > > > > I don’t have a Milk-V CM board. So I just can test this code to Star64.
> > > > > Thanks. I will test this and add the code to board_fixup_star64().
> > > >
> > > > Can you try to configure in USB2.0-only mode on Star64? Do you see
> > > > the same problem with "load access fault"?
> > > >
> > > Yes ，USB 2.0 only can work.
> > > > ...snip...
> > > >
> > > > Same devicetree fixup code but separated some of the statements to
> > > > multiple
> > > > lines:
> > > >
> > > > https://paste.debian.net/1324036/
> > > >
> > > > ```
> > > Now I can see the issue,Usb 2.0 host can work in Milk-V CM, but PCIe can not
> > work.
> > > Is that correct?
> > > The PCIe in CM board is PCIe0， The PCIe1 is not used. So I think
> > > disable PCIe1 node and just set USB 2.0 to host is OK.
> > > milkV CM PCIe0 setting is the same with VisionFive v2.
> > > The USB 3.0 setting should not be added.
> > >
> > > This USB 3.0 setting. Should NOT be added to Milk-V CM board.
> > > &pciephy0 {
> > > starfive,sys-syscon = <&sys_syscon 0x18>;
> > > starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
> > > status = "okay";
> > > };
> > >
> > > &usb_cdns3 {
> > > phys = <&usbphy0>, <&pciephy0>;
> > > phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
> > > dr_mode = "host";
> > > status = "okay";
> > > };
> > >
> >
> > Here is Mars CM Lite:
> >
> > StarFive # pci
> > BusDevFun VendorId DeviceId Device Class Sub-Class
> > _____________________________________________________________
> > 00.00.00 0x1556 0x1111 Bridge device 0x04
> > 01.00.00 0x10ec 0x8168 Network controller 0x00
> > 02.00.00 0x1556 0x1111 Bridge device 0x04
> >
> > This is the DFRobot Mini Router carrier and the Mars CM Lite. There is a
> > network interface connected to PCIe.
> >
> > When I apply this fixup:
> >
> > void spl_fdt_fixup_jh7110_cadence_usb2_host(void *fdt) {
> > int offset;
> > u32 phandle;
> >
> > offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /* &sysgpio
> > */
> > fdt_add_subnode(fdt, offset, "usb0-0");
> > fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),
> > "usb_pins", "/soc/pinctrl@13040000/usb0-0");
> > offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0");
> > /* usb_pins */
> > fdt_create_phandle(fdt, offset);
> > fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> > offset = fdt_path_offset(fdt,
> > "/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
> > fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /* GPIOMUX(25,
> > GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */
> > fdt_setprop_empty(fdt, offset, "bias-disable");
> > fdt_setprop_empty(fdt, offset, "input-disable");
> > fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> > fdt_setprop_u32(fdt, offset, "slew-rate", 0);
> >
> > offset = fdt_path_offset(fdt, "/soc/pcie@2c000000"); /* &pcie1 */
> > fdt_setprop_string(fdt, offset, "status", "disabled");
> >
> > offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */
> > fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> > phandle = fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > "/soc/pinctrl@13040000/usb0-0")); /* <&usb_pins> */
> > fdt_setprop_u32(fdt, offset, "pinctrl-0", phandle);
> > fdt_setprop_string(fdt, offset, "status", "okay");
> >
> > offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /*
> > &usb_cdns3 */
> > fdt_setprop_string(fdt, offset, "dr_mode", "host"); }
> >
> > at the last instruction of spl_fdt_fixup_mars_cm() then there is this error I am
> > telling you about:
> >
> > U-Boot 2024.07-00971-g8eed381de5ef-dirty (Jul 23 2024 - 05:49:09 -0700)
> >
> > CPU: sifive,u74-mc
> > Model: Milk-V Mars CM Lite
> > DRAM: 4 GiB
> > Core: 139 devices, 29 uclasses, devicetree: board
> > WDT: Not starting watchdog@13070000
> > MMC: mmc@16010000: 0, mmc@16020000: 1
> > Loading Environment from SPIFlash... SF: Detected gd25lq128 with page size
> > 256 Bytes, erase size 4 KiB, total 16 MiB OK StarFive EEPROM format v2
> >
> > --------EEPROM INFO--------
> > Vendor : MILK-V
> > Product full SN: MARC-V10-2340-D004E000-000006DF data version: 0x2 PCB
> > revision: 0xc1 BOM revision: A Ethernet MAC0 address: 6c:cf:39:00:83:11
> > Ethernet MAC1 address: 6c:cf:39:00:83:12 --------EEPROM INFO--------
> >
> > starfive_7110_pcie pcie@2b000000: Starfive PCIe bus probed.
> > PCI: Failed autoconfig bar 10
> > In: serial@10000000
> > Out: serial@10000000
> > Err: serial@10000000
> > Net: eth0: ethernet@16030000
> > Error: eth_rtl8169 No valid MAC address found.
> >
> > starting USB...
> > Bus usb@0: cdns-usb3-host usb@0: set 1 has failed, back to 0 scanning bus
> > usb@0 for devices... Unhandled exception: Load access fault
> > EPC: 00000000fff85b2e RA: 00000000fff85b28 TVAL: 0000000000000004
> > EPC: 0000000040246b2e RA: 0000000040246b28 reloc adjusted
> >
> > Code: 9863 3ee7 8526 f0ef c37f 651c 3a03 0105 (43dc)
> >
> >
> > resetting ...
> >
> > (C)StarFive
> > CCC
> I can reproduce USB 2.0 only on Star64 now. I know this.
> Next version I will fix this.
I follow the "load access fault" problem to
drivers/usb/host/usb-uclass.c: err = ops->control(bus, udev, pipe,
buffer, length, setup);
ops->control has the value set from drivers/usb/host/xhci.c:
struct dm_usb_ops xhci_usb_ops = {
.control = xhci_submit_control_msg,
...
I verify this by assigning a unique value to xhci_usb_ops.control and
printf from submit_control_msg() in drivers/usb/host/usb-uclass.c and
the value is the same.
So why does this cause a load access fault when calling this function
pointer of &xhci_submit_control_msg, but just when we are having a
problem in the Cadence USB wrapper with USB2.0-only, and not USB3.0?
The load access fault is a problem because it is a crash / halt and
nothing else can be done, and so after then a different U-Boot must be
flashed with a recovery method.
I think the USB2.0-only problem is different, but anyway it should not
be possible to crash U-Boot this way. How is this possible?
>
> You can test with this patch to check whether can fix this.
>
> diff --git a/drivers/phy/starfive/phy-jh7110-usb2.c b/drivers/phy/starfive/phy-jh7110-usb2.c
> index d48c9f8a74..a09fb2efea 100644
> --- a/drivers/phy/starfive/phy-jh7110-usb2.c
> +++ b/drivers/phy/starfive/phy-jh7110-usb2.c
> @@ -116,7 +116,7 @@ int jh7110_usb2_phy_probe(struct udevice *dev)
> dev_err(dev, "Failed to get app 125m clock\n");
> return PTR_ERR(phy->app_125m);
> }
> -
> + writel(BIT(17), 0x13030018);
> return 0;
> }
>
Yes, adding the writel() this avoids the load access fault for Mars CM
Lite, and USB with also PCIe are active:
void spl_fdt_fixup_jh7110_cadence_usb2_host(void *fdt)
{
int offset;
u32 phandle;
offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000"); /* &sysgpio */
fdt_add_subnode(fdt, offset, "usb0-0");
fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),
"usb_pins", "/soc/pinctrl@13040000/usb0-0");
offset = fdt_path_offset(fdt, "/soc/pinctrl@13040000/usb0-0");
/* usb_pins */
fdt_create_phandle(fdt, offset);
fdt_add_subnode(fdt, offset, "driver-vbus-pin");
offset = fdt_path_offset(fdt,
"/soc/pinctrl@13040000/usb0-0/driver-vbus-pin");
fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */
fdt_setprop_empty(fdt, offset, "bias-disable");
fdt_setprop_empty(fdt, offset, "input-disable");
fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
fdt_setprop_u32(fdt, offset, "slew-rate", 0);
offset = fdt_path_offset(fdt, "/soc/usb@10100000"); /* &usb0 */
fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
phandle = fdt_get_phandle(fdt, fdt_path_offset(fdt,
"/soc/pinctrl@13040000/usb0-0")); /* <&usb_pins> */
fdt_setprop_u32(fdt, offset, "pinctrl-0", phandle);
fdt_setprop_string(fdt, offset, "status", "okay");
offset = fdt_path_offset(fdt, "/soc/usb@10100000/usb@0"); /*
&usb_cdns3 */
fdt_setprop_string(fdt, offset, "dr_mode", "host");
}
StarFive # pci;usb tree
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
00.00.00 0x1556 0x1111 Bridge device 0x04
01.00.00 0x10ec 0x8168 Network controller 0x00
02.00.00 0x1556 0x1111 Bridge device 0x04
USB device tree:
1 Hub (5 Gb/s, 0mA)
U-Boot XHCI Host Controller
The output text says USB 3.0, and 5Gb/s speeds, which is probably
wrong for USB 2.0 but anyway I was able to usb stop;usb start for a
storage device and it reports 480Mb/s:
StarFive # usb tree
USB device tree:
1 Hub (5 Gb/s, 0mA)
| U-Boot XHCI Host Controller
|
+-2 Mass Storage (480 Mb/s, 500mA)
Kingston UHS-II SD Reader 202006003857
StarFive # usb info
1: Hub, USB Revision 3.0
- U-Boot XHCI Host Controller
- Class: Hub
- PacketSize: 512 Configurations: 1
- Vendor: 0x0000 Product 0x0000 Version 1.0
Configuration: 1
- Interfaces: 1 Self Powered 0mA
Interface: 0
- Alternate Setting 0, Endpoints: 1
- Class Hub
- Endpoint 1 In Interrupt MaxPacket 8 Interval 255ms
2: Mass Storage, USB Revision 2.10
- Kingston UHS-II SD Reader 202006003857
- Class: (from Interface) Mass Storage
- PacketSize: 64 Configurations: 1
- Vendor: 0x11b0 Product 0x3306 Version 0.3
Configuration: 1
- Interfaces: 1 Bus Powered 500mA
Interface: 0
- Alternate Setting 0, Endpoints: 2
- Class Mass Storage, Transp. SCSI, Bulk only
- Endpoint 1 In Bulk MaxPacket 512
- Endpoint 2 Out Bulk MaxPacket 512
StarFive # load usb 0:2 $loadaddr /boot/initrd.img-6.9.8-riscv64
46072333 bytes read in 2760 ms (15.9 MiB/s)
However, when Linux kernel is loaded using U-Boot internal fdt there
is USB but not any PCIe active:
# lspci -v; lsusb -v
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass 9 Hub
bDeviceSubClass 0 [unknown]
bDeviceProtocol 1 Single TT
bMaxPacketSize0 64
idVendor 0x1d6b Linux Foundation
idProduct 0x0002 2.0 root hub
bcdDevice 6.10
iManufacturer 3 Linux 6.10.0-jh7110 xhci-hcd
iProduct 2 xHCI Host Controller
iSerial 1 xhci-hcd.0.auto
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 0x0019
bNumInterfaces 1
bConfigurationValue 1
iConfiguration 0
bmAttributes 0xe0
Self Powered
Remote Wakeup
MaxPower 0mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 1
bInterfaceClass 9 Hub
bInterfaceSubClass 0 [unknown]
bInterfaceProtocol 0 Full speed (or root) hub
iInterface 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 EP 1 IN
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0004 1x 4 bytes
bInterval 12
Hub Descriptor:
bLength 9
bDescriptorType 41
nNbrPorts 1
wHubCharacteristic 0x0009
Per-port power switching
Per-port overcurrent protection
TT think time 8 FS bits
bPwrOn2PwrGood 10 * 2 milli seconds
bHubContrCurrent 0 milli Ampere
DeviceRemovable 0x00
PortPwrCtrlMask 0xff
Hub Port Status:
Port 1: 0000.0100 power
Device Status: 0x0001
Self Powered
Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 3.00
bDeviceClass 9 Hub
bDeviceSubClass 0 [unknown]
bDeviceProtocol 3
bMaxPacketSize0 9
idVendor 0x1d6b Linux Foundation
idProduct 0x0003 3.0 root hub
bcdDevice 6.10
iManufacturer 3 Linux 6.10.0-jh7110 xhci-hcd
iProduct 2 xHCI Host Controller
iSerial 1 xhci-hcd.0.auto
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 0x001f
bNumInterfaces 1
bConfigurationValue 1
iConfiguration 0
bmAttributes 0xe0
Self Powered
Remote Wakeup
MaxPower 0mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 1
bInterfaceClass 9 Hub
bInterfaceSubClass 0 [unknown]
bInterfaceProtocol 0 Full speed (or root) hub
iInterface 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 EP 1 IN
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0004 1x 4 bytes
bInterval 12
bMaxBurst 0
Binary Object Store Descriptor:
bLength 5
bDescriptorType 15
wTotalLength 0x000f
bNumDeviceCaps 1
SuperSpeed USB Device Capability:
bLength 10
bDescriptorType 16
bDevCapabilityType 3
bmAttributes 0x02
Latency Tolerance Messages (LTM) Supported
wSpeedsSupported 0x0008
Device can operate at SuperSpeed (5Gbps)
bFunctionalitySupport 1
Lowest fully-functional device speed is Full Speed (12Mbps)
bU1DevExitLat 0 micro seconds
bU2DevExitLat 0 micro seconds
Hub Descriptor:
bLength 12
bDescriptorType 42
nNbrPorts 1
wHubCharacteristic 0x0009
Per-port power switching
Per-port overcurrent protection
bPwrOn2PwrGood 50 * 2 milli seconds
bHubContrCurrent 0 milli Ampere
bHubDecLat 0.0 micro seconds
wHubDelay 0 nano seconds
DeviceRemovable 0x00
Hub Port Status:
Port 1: 0000.02a0 5Gbps power Rx.Detect
Device Status: 0x0001
Self Powered
The USB storage device is not listed, this is because U-Boot was
trying to boot from the storage :-) so I remove it.
If I do not have USB devicetree nodes in fixup then it is like this
with PCIe active:
# lspci -v; lsusb -v
0000:00:00.0 PCI bridge: PLDA XpressRich-AXI Ref Design (rev 02)
(prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 40
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
Memory behind bridge: 30000000-300fffff [size=1M] [32-bit]
Capabilities: [80] Express Root Port (Slot+), IntMsgNum 0
Capabilities: [e0] MSI: Enable+ Count=1/32 Maskable+ 64bit+
Capabilities: [f8] Power Management version 3
Capabilities: [100] Vendor Specific Information: ID=1556 Rev=1
Len=008 <?>
Capabilities: [200] Advanced Error Reporting
Kernel driver in use: pcieport
0000:01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
RTL8111/8168/8211/8411 PCI Express Gigabit Ethernet Controller (rev
15)
Subsystem: Realtek Semiconductor Co., Ltd. RTL8111/8168 PCI
Express Gigabit Ethernet controller
Flags: fast devsel, IRQ 39
Memory at 30004000 (64-bit, non-prefetchable) [size=4K]
Memory at 30000000 (64-bit, non-prefetchable) [size=16K]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
Capabilities: [70] Express Endpoint, IntMsgNum 1
Capabilities: [b0] MSI-X: Enable+ Count=4 Masked-
Capabilities: [100] Advanced Error Reporting
Capabilities: [140] Virtual Channel
Capabilities: [160] Device Serial Number 00-00-00-00-00-00-00-00
Capabilities: [170] Latency Tolerance Reporting
Capabilities: [178] L1 PM Substates
Kernel driver in use: r8169
Kernel modules: r8169
0001:00:00.0 PCI bridge: PLDA XpressRich-AXI Ref Design (rev 02)
(prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 59
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
Memory behind bridge: [disabled] [32-bit]
Capabilities: [80] Express Root Port (Slot+), IntMsgNum 0
Capabilities: [e0] MSI: Enable+ Count=1/32 Maskable+ 64bit+
Capabilities: [f8] Power Management version 3
Capabilities: [100] Vendor Specific Information: ID=1556 Rev=1
Len=008 <?>
Capabilities: [200] Advanced Error Reporting
Kernel driver in use: pcieport
There is more to do for changing to USB2.0-only and also keep PCIe ?
Thank you Minda. -E
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 5/8] pinctrl: starfive: Setup USB default disable overcurrent pin
2024-07-19 1:38 ` [PATCH v3 5/8] pinctrl: starfive: Setup USB default disable overcurrent pin Minda Chen
@ 2024-07-26 8:35 ` Minda Chen
0 siblings, 0 replies; 19+ messages in thread
From: Minda Chen @ 2024-07-26 8:35 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang
Cc: u-boot@lists.denx.de, Heinrich Schuchardt, Simon Glass, E Shattow
>
> For some JH7110 boards, USB host overcurent pin is not reserved, To make USB
> host work, overcurrent pin must be disabled. So set the pin default disabled.
>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
> drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
> b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
> index dafba65eae..1102985ab9 100644
> --- a/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
> +++ b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
> @@ -378,8 +378,15 @@ static int jh7110_sys_pinctrl_probe(struct udevice
> *dev) {
> struct starfive_pinctrl_soc_info *info =
> (struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev);
> -
> - return starfive_pinctrl_probe(dev, info);
> + struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
> + int ret;
> +
> + ret = starfive_pinctrl_probe(dev, info);
> + /* Set default the usb controller overcurrent signal. */
> + if (!ret)
> + clrsetbits_le32(priv->base + JH7110_SYS_GPI,
> + GENMASK(22, 16), BIT(16));
> + return ret;
> }
>
> static const struct udevice_id jh7110_sys_pinctrl_ids[] = {
> --
> 2.17.1
Hi Rick and Leo
I think move this to spl is better.
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 1/8] usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode()
2024-07-19 1:38 ` [PATCH v3 1/8] usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode() Minda Chen
@ 2024-07-26 8:39 ` Minda Chen
0 siblings, 0 replies; 19+ messages in thread
From: Minda Chen @ 2024-07-26 8:39 UTC (permalink / raw)
To: Marek Vasut, Tom Rini, Roger Quadros, Neil Armstrong,
Alexey Romanov, Sumit Garg, Mark Kettenis, Nishanth Menon,
Rick Chen, Leo Yu-Chi Liang
Cc: u-boot@lists.denx.de, Heinrich Schuchardt, Simon Glass, E Shattow
>
> USB PHY maybe need to set PHY mode in different USB dr mode. So translate
> USB PHY mode to generic PHY mode and call generic_phy_set_mode().
>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
> drivers/usb/cdns3/drd.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/usb/cdns3/drd.c b/drivers/usb/cdns3/drd.c index
> 47874fec29..cbb1334234 100644
> --- a/drivers/usb/cdns3/drd.c
> +++ b/drivers/usb/cdns3/drd.c
> @@ -217,15 +217,19 @@ static int cdns3_init_otg_mode(struct cdns3 *cdns)
> int cdns3_drd_update_mode(struct cdns3 *cdns) {
> int ret = 0;
> + int mode;
>
> switch (cdns->dr_mode) {
> case USB_DR_MODE_PERIPHERAL:
> + mode = PHY_MODE_USB_DEVICE;
> ret = cdns3_set_mode(cdns, USB_DR_MODE_PERIPHERAL);
> break;
> case USB_DR_MODE_HOST:
> + mode = PHY_MODE_USB_HOST;
> ret = cdns3_set_mode(cdns, USB_DR_MODE_HOST);
> break;
> case USB_DR_MODE_OTG:
> + mode = PHY_MODE_USB_OTG;
> ret = cdns3_init_otg_mode(cdns);
> break;
> default:
> @@ -234,6 +238,16 @@ int cdns3_drd_update_mode(struct cdns3 *cdns)
> return -EINVAL;
> }
>
> + ret = generic_phy_set_mode(&cdns->usb2_phy, mode, 0);
> + if (ret) {
> + dev_err(cdns->dev, "Set usb 2.0 PHY mode failed %d\n", ret);
> + return ret;
> + }
> +
> + ret = generic_phy_set_mode(&cdns->usb3_phy, mode, 0);
> + if (ret)
> + dev_err(cdns->dev, "Set usb 3.0 PHY mode failed %d\n", ret);
> +
> return ret;
> }
>
Hi Roger
Is this patch OK now? Could you add review tag to this? Thanks.
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2024-07-26 8:39 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-07-19 1:38 [PATCH v3 0/8] Add Starfive JH7110 Cadence USB driver Minda Chen
2024-07-19 1:38 ` [PATCH v3 1/8] usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode() Minda Chen
2024-07-26 8:39 ` Minda Chen
2024-07-19 1:38 ` [PATCH v3 2/8] phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver Minda Chen
2024-07-19 1:38 ` [PATCH v3 3/8] phy: starfive: Add Starfive JH7110 PCIe " Minda Chen
2024-07-19 1:38 ` [PATCH v3 4/8] usb: cdns: starfive: Add cdns USB driver Minda Chen
2024-07-19 1:38 ` [PATCH v3 5/8] pinctrl: starfive: Setup USB default disable overcurrent pin Minda Chen
2024-07-26 8:35 ` Minda Chen
2024-07-19 1:38 ` [PATCH v3 6/8] configs: starfive: Add visionfive2 cadence USB configuration Minda Chen
2024-07-19 1:38 ` [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node Minda Chen
2024-07-21 1:47 ` E Shattow
2024-07-21 18:27 ` E Shattow
2024-07-23 1:29 ` Minda Chen
2024-07-23 3:53 ` E Shattow
2024-07-23 10:16 ` Minda Chen
2024-07-23 13:05 ` E Shattow
2024-07-24 3:24 ` Minda Chen
2024-07-24 18:05 ` E Shattow
2024-07-19 1:38 ` [PATCH v3 8/8] MAINTAINERS: Update Starfive visionfive2 maintain files Minda Chen
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