diff for duplicates of <20240726110355.2181563-9-kevin_chen@aspeedtech.com> diff --git a/a/1.txt b/N1/1.txt index 5a1b10d..f428e57 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -40,7 +40,7 @@ index 000000000000..858ab95251e4 + #address-cells = <1>; + #size-cells = <0>; + -+ cpu at 0 { ++ cpu@0 { + compatible = "arm,cortex-a35"; + enable-method = "psci"; + device_type = "cpu"; @@ -54,7 +54,7 @@ index 000000000000..858ab95251e4 + next-level-cache = <&l2>; + }; + -+ cpu at 1 { ++ cpu@1 { + compatible = "arm,cortex-a35"; + enable-method = "psci"; + device_type = "cpu"; @@ -68,7 +68,7 @@ index 000000000000..858ab95251e4 + next-level-cache = <&l2>; + }; + -+ cpu at 2 { ++ cpu@2 { + compatible = "arm,cortex-a35"; + enable-method = "psci"; + device_type = "cpu"; @@ -82,7 +82,7 @@ index 000000000000..858ab95251e4 + next-level-cache = <&l2>; + }; + -+ cpu at 3 { ++ cpu@3 { + compatible = "arm,cortex-a35"; + enable-method = "psci"; + device_type = "cpu"; @@ -116,7 +116,7 @@ index 000000000000..858ab95251e4 + method = "smc"; + }; + -+ gic: interrupt-controller at 12200000 { ++ gic: interrupt-controller@12200000 { + compatible = "arm,gic-v3"; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; @@ -139,13 +139,13 @@ index 000000000000..858ab95251e4 + always-on; + }; + -+ soc0: soc at 10000000 { ++ soc0: soc@10000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + -+ soc0_sram: sram at 10000000 { ++ soc0_sram: sram@10000000 { + compatible = "mmio-sram"; + reg = <0x0 0x10000000 0x0 0x20000>; /* 128KiB SRAM on soc0 */ + ranges = <0x0 0x0 0x0 0x10000000 0x0 0x20000>; @@ -153,13 +153,13 @@ index 000000000000..858ab95251e4 + #size-cells = <2>; + no-memory-wc; + -+ exported at 0 { ++ exported@0 { + reg = <0 0x0 0 0x20000>; + export; + }; + }; + -+ syscon0: syscon at 12c02000 { ++ syscon0: syscon@12c02000 { + compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd"; + reg = <0x0 0x12c02000 0x0 0x1000>; + ranges = <0x0 0x0 0 0x12c02000 0 0x1000>; @@ -168,12 +168,12 @@ index 000000000000..858ab95251e4 + #clock-cells = <1>; + #reset-cells = <1>; + -+ silicon-id at 0 { ++ silicon-id@0 { + compatible = "aspeed,ast2700-silicon-id", "aspeed,silicon-id"; + reg = <0 0x0 0 0x4>; + }; + -+ scu_ic0: interrupt-controller at 1D0 { ++ scu_ic0: interrupt-controller@1D0 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2700-scu-ic0"; + reg = <0 0x1d0 0 0xc>; @@ -181,7 +181,7 @@ index 000000000000..858ab95251e4 + interrupt-controller; + }; + -+ scu_ic1: interrupt-controller at 1E0 { ++ scu_ic1: interrupt-controller@1E0 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2700-scu-ic1"; + reg = <0 0x1e0 0 0xc>; @@ -189,24 +189,24 @@ index 000000000000..858ab95251e4 + interrupt-controller; + }; + -+ soc0_rst: reset-controller at 200 { ++ soc0_rst: reset-controller@200 { + reg = <0 0x200 0 0x40>; + }; + -+ soc0_clk: clock-controller at 240 { ++ soc0_clk: clock-controller@240 { + reg = <0 0x240 0 0x1c0>; + }; + }; + + }; + -+ soc1: soc at 14000000 { ++ soc1: soc@14000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + -+ syscon1: syscon at 14c02000 { ++ syscon1: syscon@14c02000 { + compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd"; + reg = <0x0 0x14c02000 0x0 0x1000>; + ranges = <0x0 0x0 0x0 0x14c02000 0x0 0x1000>; @@ -215,16 +215,16 @@ index 000000000000..858ab95251e4 + #clock-cells = <1>; + #reset-cells = <1>; + -+ soc1_rst: reset-controller at 200 { ++ soc1_rst: reset-controller@200 { + #reset-cells = <1>; + }; + -+ soc1_clk: clock-controller at 240 { ++ soc1_clk: clock-controller@240 { + reg = <0 0x240 0 0x1c0>; + }; + }; + -+ uart12: serial at 14c33b00 { ++ uart12: serial@14c33b00 { + compatible = "ns16550a"; + reg = <0x0 0x14c33b00 0x0 0x100>; + reg-shift = <2>; diff --git a/a/content_digest b/N1/content_digest index 0836c4f..f1d9e8f 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,35 @@ "ref\020240726110355.2181563-1-kevin_chen@aspeedtech.com\0" "From\0Kevin Chen <kevin_chen@aspeedtech.com>\0" "Subject\0[PATCH v1 08/10] arm64: dts: aspeed: Add initial AST27XX device tree\0" - "Date\0Fri, 26 Jul 2024 11:09:37 -0000\0" - "To\0linux-aspeed@lists.ozlabs.org\0" + "Date\0Fri, 26 Jul 2024 19:03:53 +0800\0" + "To\0<robh@kernel.org>" + <krzk+dt@kernel.org> + <conor+dt@kernel.org> + <joel@jms.id.au> + <andrew@codeconstruct.com.au> + <lee@kernel.org> + <catalin.marinas@arm.com> + <will@kernel.org> + <arnd@arndb.de> + <olof@lixom.net> + <soc@kernel.org> + <mturquette@baylibre.com> + <sboyd@kernel.org> + <p.zabel@pengutronix.de> + <quic_bjorande@quicinc.com> + <geert+renesas@glider.be> + <dmitry.baryshkov@linaro.org> + <shawnguo@kernel.org> + <neil.armstrong@linaro.org> + <m.szyprowski@samsung.com> + <nfraprado@collabora.com> + <u-kumar1@ti.com> + <kevin_chen@aspeedtech.com> + <devicetree@vger.kernel.org> + <linux-arm-kernel@lists.infradead.org> + <linux-aspeed@lists.ozlabs.org> + <linux-kernel@vger.kernel.org> + " <linux-clk@vger.kernel.org>\0" "\00:1\0" "b\0" "---\n" @@ -47,7 +74,7 @@ "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <0>;\n" "+\n" - "+\t\tcpu at 0 {\n" + "+\t\tcpu@0 {\n" "+\t\t\tcompatible = \"arm,cortex-a35\";\n" "+\t\t\tenable-method = \"psci\";\n" "+\t\t\tdevice_type = \"cpu\";\n" @@ -61,7 +88,7 @@ "+\t\t\tnext-level-cache = <&l2>;\n" "+\t\t};\n" "+\n" - "+\t\tcpu at 1 {\n" + "+\t\tcpu@1 {\n" "+\t\t\tcompatible = \"arm,cortex-a35\";\n" "+\t\t\tenable-method = \"psci\";\n" "+\t\t\tdevice_type = \"cpu\";\n" @@ -75,7 +102,7 @@ "+\t\t\tnext-level-cache = <&l2>;\n" "+\t\t};\n" "+\n" - "+\t\tcpu at 2 {\n" + "+\t\tcpu@2 {\n" "+\t\t\tcompatible = \"arm,cortex-a35\";\n" "+\t\t\tenable-method = \"psci\";\n" "+\t\t\tdevice_type = \"cpu\";\n" @@ -89,7 +116,7 @@ "+\t\t\tnext-level-cache = <&l2>;\n" "+\t\t};\n" "+\n" - "+\t\tcpu at 3 {\n" + "+\t\tcpu@3 {\n" "+\t\t\tcompatible = \"arm,cortex-a35\";\n" "+\t\t\tenable-method = \"psci\";\n" "+\t\t\tdevice_type = \"cpu\";\n" @@ -123,7 +150,7 @@ "+\t\tmethod = \"smc\";\n" "+\t};\n" "+\n" - "+\tgic: interrupt-controller at 12200000 {\n" + "+\tgic: interrupt-controller@12200000 {\n" "+\t\tcompatible = \"arm,gic-v3\";\n" "+\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;\n" "+\t\t#interrupt-cells = <3>;\n" @@ -146,13 +173,13 @@ "+\t\talways-on;\n" "+\t};\n" "+\n" - "+\tsoc0: soc at 10000000 {\n" + "+\tsoc0: soc@10000000 {\n" "+\t\tcompatible = \"simple-bus\";\n" "+\t\t#address-cells = <2>;\n" "+\t\t#size-cells = <2>;\n" "+\t\tranges;\n" "+\n" - "+\t\tsoc0_sram: sram at 10000000 {\n" + "+\t\tsoc0_sram: sram@10000000 {\n" "+\t\t\tcompatible = \"mmio-sram\";\n" "+\t\t\treg = <0x0 0x10000000 0x0 0x20000>;\t/* 128KiB SRAM on soc0 */\n" "+\t\t\tranges = <0x0 0x0 0x0 0x10000000 0x0 0x20000>;\n" @@ -160,13 +187,13 @@ "+\t\t\t#size-cells = <2>;\n" "+\t\t\tno-memory-wc;\n" "+\n" - "+\t\t\texported at 0 {\n" + "+\t\t\texported@0 {\n" "+\t\t\t\treg = <0 0x0 0 0x20000>;\n" "+\t\t\t\texport;\n" "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tsyscon0: syscon at 12c02000 {\n" + "+\t\tsyscon0: syscon@12c02000 {\n" "+\t\t\tcompatible = \"aspeed,ast2700-scu0\", \"syscon\", \"simple-mfd\";\n" "+\t\t\treg = <0x0 0x12c02000 0x0 0x1000>;\n" "+\t\t\tranges = <0x0 0x0 0 0x12c02000 0 0x1000>;\n" @@ -175,12 +202,12 @@ "+\t\t\t#clock-cells = <1>;\n" "+\t\t\t#reset-cells = <1>;\n" "+\n" - "+\t\t\tsilicon-id at 0 {\n" + "+\t\t\tsilicon-id@0 {\n" "+\t\t\t\tcompatible = \"aspeed,ast2700-silicon-id\", \"aspeed,silicon-id\";\n" "+\t\t\t\treg = <0 0x0 0 0x4>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tscu_ic0: interrupt-controller at 1D0 {\n" + "+\t\t\tscu_ic0: interrupt-controller@1D0 {\n" "+\t\t\t\t#interrupt-cells = <1>;\n" "+\t\t\t\tcompatible = \"aspeed,ast2700-scu-ic0\";\n" "+\t\t\t\treg = <0 0x1d0 0 0xc>;\n" @@ -188,7 +215,7 @@ "+\t\t\t\tinterrupt-controller;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tscu_ic1: interrupt-controller at 1E0 {\n" + "+\t\t\tscu_ic1: interrupt-controller@1E0 {\n" "+\t\t\t\t#interrupt-cells = <1>;\n" "+\t\t\t\tcompatible = \"aspeed,ast2700-scu-ic1\";\n" "+\t\t\t\treg = <0 0x1e0 0 0xc>;\n" @@ -196,24 +223,24 @@ "+\t\t\t\tinterrupt-controller;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tsoc0_rst: reset-controller at 200 {\n" + "+\t\t\tsoc0_rst: reset-controller@200 {\n" "+\t\t\t\treg = <0 0x200 0 0x40>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tsoc0_clk: clock-controller at 240 {\n" + "+\t\t\tsoc0_clk: clock-controller@240 {\n" "+\t\t\t\treg = <0 0x240 0 0x1c0>;\n" "+\t\t\t};\n" "+\t\t};\n" "+\n" "+\t};\n" "+\n" - "+\tsoc1: soc at 14000000 {\n" + "+\tsoc1: soc@14000000 {\n" "+\t\tcompatible = \"simple-bus\";\n" "+\t\t#address-cells = <2>;\n" "+\t\t#size-cells = <2>;\n" "+\t\tranges;\n" "+\n" - "+\t\tsyscon1: syscon at 14c02000 {\n" + "+\t\tsyscon1: syscon@14c02000 {\n" "+\t\t\tcompatible = \"aspeed,ast2700-scu1\", \"syscon\", \"simple-mfd\";\n" "+\t\t\treg = <0x0 0x14c02000 0x0 0x1000>;\n" "+\t\t\tranges = <0x0 0x0 0x0 0x14c02000 0x0 0x1000>;\n" @@ -222,16 +249,16 @@ "+\t\t\t#clock-cells = <1>;\n" "+\t\t\t#reset-cells = <1>;\n" "+\n" - "+\t\t\tsoc1_rst: reset-controller at 200 {\n" + "+\t\t\tsoc1_rst: reset-controller@200 {\n" "+\t\t\t\t#reset-cells = <1>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tsoc1_clk: clock-controller at 240 {\n" + "+\t\t\tsoc1_clk: clock-controller@240 {\n" "+\t\t\t\treg = <0 0x240 0 0x1c0>;\n" "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tuart12: serial at 14c33b00 {\n" + "+\t\tuart12: serial@14c33b00 {\n" "+\t\t\tcompatible = \"ns16550a\";\n" "+\t\t\treg = <0x0 0x14c33b00 0x0 0x100>;\n" "+\t\t\treg-shift = <2>;\n" @@ -246,4 +273,4 @@ "-- \n" 2.34.1 -190f6a732049c3e2c41cff00a97d9a4039cc3bd9ddccc8dc8cc16244be6aafa6 +5d1e45362b21cadb6eae2ebec7b6504e8524e29fae639be84e3107ab105924db
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