From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>,
Anup Patel <anup@brainfault.org>,
Thomas Gleixner <tglx@linutronix.de>,
Samuel Holland <samuel.holland@sifive.com>,
Robert Moore <robert.moore@intel.com>,
Conor Dooley <conor.dooley@microchip.com>,
Andrew Jones <ajones@ventanamicro.com>,
Haibo Xu <haibo1.xu@intel.com>,
Atish Kumar Patra <atishp@rivosinc.com>,
Drew Fustini <dfustini@tenstorrent.com>,
Sunil V L <sunilvl@ventanamicro.com>
Subject: [PATCH v7 17/17] irqchip/sifive-plic: Add ACPI support
Date: Mon, 29 Jul 2024 19:52:39 +0530 [thread overview]
Message-ID: <20240729142241.733357-18-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20240729142241.733357-1-sunilvl@ventanamicro.com>
Add ACPI support in PLIC driver. Use the mapping created early during
boot to get details about the PLIC.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Co-developed-by: Haibo Xu <haibo1.xu@intel.com>
Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
---
drivers/irqchip/irq-sifive-plic.c | 94 ++++++++++++++++++++++++-------
1 file changed, 73 insertions(+), 21 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 9e22f7e378f5..12d60728329c 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -3,6 +3,7 @@
* Copyright (C) 2017 SiFive
* Copyright (C) 2018 Christoph Hellwig
*/
+#include <linux/acpi.h>
#include <linux/cpu.h>
#include <linux/interrupt.h>
#include <linux/io.h>
@@ -70,6 +71,8 @@ struct plic_priv {
unsigned long plic_quirks;
unsigned int nr_irqs;
unsigned long *prio_save;
+ u32 gsi_base;
+ int id;
};
struct plic_handler {
@@ -324,6 +327,10 @@ static int plic_irq_domain_translate(struct irq_domain *d,
{
struct plic_priv *priv = d->host_data;
+ /* For DT, gsi_base is always zero. */
+ if (fwspec->param[0] >= priv->gsi_base)
+ fwspec->param[0] = fwspec->param[0] - priv->gsi_base;
+
if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
return irq_domain_translate_twocell(d, fwspec, hwirq, type);
@@ -424,18 +431,37 @@ static const struct of_device_id plic_match[] = {
{}
};
+#ifdef CONFIG_ACPI
+
+static const struct acpi_device_id plic_acpi_match[] = {
+ { "RSCV0001", 0 },
+ {}
+};
+MODULE_DEVICE_TABLE(acpi, plic_acpi_match);
+
+#endif
static int plic_parse_nr_irqs_and_contexts(struct platform_device *pdev,
- u32 *nr_irqs, u32 *nr_contexts)
+ u32 *nr_irqs, u32 *nr_contexts,
+ u32 *gsi_base, u32 *id)
{
struct device *dev = &pdev->dev;
int rc;
- /*
- * Currently, only OF fwnode is supported so extend this
- * function for ACPI support.
- */
- if (!is_of_node(dev->fwnode))
- return -EINVAL;
+ if (!is_of_node(dev->fwnode)) {
+ rc = riscv_acpi_get_gsi_info(dev->fwnode, gsi_base, id, nr_irqs, NULL);
+ if (rc) {
+ dev_err(dev, "failed to find GSI mapping\n");
+ return rc;
+ }
+
+ *nr_contexts = acpi_get_plic_nr_contexts(*id);
+ if (WARN_ON(!*nr_contexts)) {
+ dev_err(dev, "no PLIC context available\n");
+ return -EINVAL;
+ }
+
+ return 0;
+ }
rc = of_property_read_u32(to_of_node(dev->fwnode), "riscv,ndev", nr_irqs);
if (rc) {
@@ -449,23 +475,29 @@ static int plic_parse_nr_irqs_and_contexts(struct platform_device *pdev,
return -EINVAL;
}
+ *gsi_base = 0;
+ *id = 0;
+
return 0;
}
static int plic_parse_context_parent(struct platform_device *pdev, u32 context,
- u32 *parent_hwirq, int *parent_cpu)
+ u32 *parent_hwirq, int *parent_cpu, u32 id)
{
struct device *dev = &pdev->dev;
struct of_phandle_args parent;
unsigned long hartid;
int rc;
- /*
- * Currently, only OF fwnode is supported so extend this
- * function for ACPI support.
- */
- if (!is_of_node(dev->fwnode))
- return -EINVAL;
+ if (!is_of_node(dev->fwnode)) {
+ hartid = acpi_get_ext_intc_parent_hartid(id, context);
+ if (hartid == INVALID_HARTID)
+ return -EINVAL;
+
+ *parent_cpu = riscv_hartid_to_cpuid(hartid);
+ *parent_hwirq = RV_IRQ_EXT;
+ return 0;
+ }
rc = of_irq_parse_one(to_of_node(dev->fwnode), context, &parent);
if (rc)
@@ -489,6 +521,8 @@ static int plic_probe(struct platform_device *pdev)
u32 nr_irqs, parent_hwirq;
struct plic_priv *priv;
irq_hw_number_t hwirq;
+ int id, context_id;
+ u32 gsi_base;
if (is_of_node(dev->fwnode)) {
const struct of_device_id *id;
@@ -498,7 +532,7 @@ static int plic_probe(struct platform_device *pdev)
plic_quirks = (unsigned long)id->data;
}
- error = plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts);
+ error = plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts, &gsi_base, &id);
if (error)
return error;
@@ -509,6 +543,8 @@ static int plic_probe(struct platform_device *pdev)
priv->dev = dev;
priv->plic_quirks = plic_quirks;
priv->nr_irqs = nr_irqs;
+ priv->gsi_base = gsi_base;
+ priv->id = id;
priv->regs = devm_platform_ioremap_resource(pdev, 0);
if (WARN_ON(!priv->regs))
@@ -519,12 +555,22 @@ static int plic_probe(struct platform_device *pdev)
return -ENOMEM;
for (i = 0; i < nr_contexts; i++) {
- error = plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu);
+ error = plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu, priv->id);
if (error) {
dev_warn(dev, "hwirq for context%d not found\n", i);
continue;
}
+ if (is_of_node(dev->fwnode)) {
+ context_id = i;
+ } else {
+ context_id = acpi_get_plic_context(priv->id, i);
+ if (context_id == INVALID_CONTEXT) {
+ dev_warn(dev, "invalid context id for context%d\n", i);
+ continue;
+ }
+ }
+
/*
* Skip contexts other than external interrupts for our
* privilege level.
@@ -562,10 +608,10 @@ static int plic_probe(struct platform_device *pdev)
cpumask_set_cpu(cpu, &priv->lmask);
handler->present = true;
handler->hart_base = priv->regs + CONTEXT_BASE +
- i * CONTEXT_SIZE;
+ context_id * CONTEXT_SIZE;
raw_spin_lock_init(&handler->enable_lock);
handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE +
- i * CONTEXT_ENABLE_SIZE;
+ context_id * CONTEXT_ENABLE_SIZE;
handler->priv = priv;
handler->enable_save = devm_kcalloc(dev, DIV_ROUND_UP(nr_irqs, 32),
@@ -581,8 +627,8 @@ static int plic_probe(struct platform_device *pdev)
nr_handlers++;
}
- priv->irqdomain = irq_domain_add_linear(to_of_node(dev->fwnode), nr_irqs + 1,
- &plic_irqdomain_ops, priv);
+ priv->irqdomain = irq_domain_create_linear(dev->fwnode, nr_irqs + 1,
+ &plic_irqdomain_ops, priv);
if (WARN_ON(!priv->irqdomain))
goto fail_cleanup_contexts;
@@ -619,13 +665,18 @@ static int plic_probe(struct platform_device *pdev)
}
}
+#ifdef CONFIG_ACPI
+ if (!acpi_disabled)
+ acpi_dev_clear_dependencies(ACPI_COMPANION(dev));
+#endif
+
dev_info(dev, "mapped %d interrupts with %d handlers for %d contexts.\n",
nr_irqs, nr_handlers, nr_contexts);
return 0;
fail_cleanup_contexts:
for (i = 0; i < nr_contexts; i++) {
- if (plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu))
+ if (plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu, priv->id))
continue;
if (parent_hwirq != RV_IRQ_EXT || cpu < 0)
continue;
@@ -644,6 +695,7 @@ static struct platform_driver plic_driver = {
.driver = {
.name = "riscv-plic",
.of_match_table = plic_match,
+ .acpi_match_table = ACPI_PTR(plic_acpi_match),
},
.probe = plic_probe,
};
--
2.43.0
WARNING: multiple messages have this Message-ID (diff)
From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org
Cc: Albert Ou <aou@eecs.berkeley.edu>, Haibo Xu <haibo1.xu@intel.com>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Atish Kumar Patra <atishp@rivosinc.com>,
Robert Moore <robert.moore@intel.com>,
Samuel Holland <samuel.holland@sifive.com>,
Conor Dooley <conor.dooley@microchip.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Drew Fustini <dfustini@tenstorrent.com>,
Anup Patel <anup@brainfault.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Thomas Gleixner <tglx@linutronix.de>,
Andrew Jones <ajones@ventanamicro.com>,
Will Deacon <will@kernel.org>, Len Brown <lenb@kernel.org>
Subject: [PATCH v7 17/17] irqchip/sifive-plic: Add ACPI support
Date: Mon, 29 Jul 2024 19:52:39 +0530 [thread overview]
Message-ID: <20240729142241.733357-18-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20240729142241.733357-1-sunilvl@ventanamicro.com>
Add ACPI support in PLIC driver. Use the mapping created early during
boot to get details about the PLIC.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Co-developed-by: Haibo Xu <haibo1.xu@intel.com>
Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
---
drivers/irqchip/irq-sifive-plic.c | 94 ++++++++++++++++++++++++-------
1 file changed, 73 insertions(+), 21 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 9e22f7e378f5..12d60728329c 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -3,6 +3,7 @@
* Copyright (C) 2017 SiFive
* Copyright (C) 2018 Christoph Hellwig
*/
+#include <linux/acpi.h>
#include <linux/cpu.h>
#include <linux/interrupt.h>
#include <linux/io.h>
@@ -70,6 +71,8 @@ struct plic_priv {
unsigned long plic_quirks;
unsigned int nr_irqs;
unsigned long *prio_save;
+ u32 gsi_base;
+ int id;
};
struct plic_handler {
@@ -324,6 +327,10 @@ static int plic_irq_domain_translate(struct irq_domain *d,
{
struct plic_priv *priv = d->host_data;
+ /* For DT, gsi_base is always zero. */
+ if (fwspec->param[0] >= priv->gsi_base)
+ fwspec->param[0] = fwspec->param[0] - priv->gsi_base;
+
if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
return irq_domain_translate_twocell(d, fwspec, hwirq, type);
@@ -424,18 +431,37 @@ static const struct of_device_id plic_match[] = {
{}
};
+#ifdef CONFIG_ACPI
+
+static const struct acpi_device_id plic_acpi_match[] = {
+ { "RSCV0001", 0 },
+ {}
+};
+MODULE_DEVICE_TABLE(acpi, plic_acpi_match);
+
+#endif
static int plic_parse_nr_irqs_and_contexts(struct platform_device *pdev,
- u32 *nr_irqs, u32 *nr_contexts)
+ u32 *nr_irqs, u32 *nr_contexts,
+ u32 *gsi_base, u32 *id)
{
struct device *dev = &pdev->dev;
int rc;
- /*
- * Currently, only OF fwnode is supported so extend this
- * function for ACPI support.
- */
- if (!is_of_node(dev->fwnode))
- return -EINVAL;
+ if (!is_of_node(dev->fwnode)) {
+ rc = riscv_acpi_get_gsi_info(dev->fwnode, gsi_base, id, nr_irqs, NULL);
+ if (rc) {
+ dev_err(dev, "failed to find GSI mapping\n");
+ return rc;
+ }
+
+ *nr_contexts = acpi_get_plic_nr_contexts(*id);
+ if (WARN_ON(!*nr_contexts)) {
+ dev_err(dev, "no PLIC context available\n");
+ return -EINVAL;
+ }
+
+ return 0;
+ }
rc = of_property_read_u32(to_of_node(dev->fwnode), "riscv,ndev", nr_irqs);
if (rc) {
@@ -449,23 +475,29 @@ static int plic_parse_nr_irqs_and_contexts(struct platform_device *pdev,
return -EINVAL;
}
+ *gsi_base = 0;
+ *id = 0;
+
return 0;
}
static int plic_parse_context_parent(struct platform_device *pdev, u32 context,
- u32 *parent_hwirq, int *parent_cpu)
+ u32 *parent_hwirq, int *parent_cpu, u32 id)
{
struct device *dev = &pdev->dev;
struct of_phandle_args parent;
unsigned long hartid;
int rc;
- /*
- * Currently, only OF fwnode is supported so extend this
- * function for ACPI support.
- */
- if (!is_of_node(dev->fwnode))
- return -EINVAL;
+ if (!is_of_node(dev->fwnode)) {
+ hartid = acpi_get_ext_intc_parent_hartid(id, context);
+ if (hartid == INVALID_HARTID)
+ return -EINVAL;
+
+ *parent_cpu = riscv_hartid_to_cpuid(hartid);
+ *parent_hwirq = RV_IRQ_EXT;
+ return 0;
+ }
rc = of_irq_parse_one(to_of_node(dev->fwnode), context, &parent);
if (rc)
@@ -489,6 +521,8 @@ static int plic_probe(struct platform_device *pdev)
u32 nr_irqs, parent_hwirq;
struct plic_priv *priv;
irq_hw_number_t hwirq;
+ int id, context_id;
+ u32 gsi_base;
if (is_of_node(dev->fwnode)) {
const struct of_device_id *id;
@@ -498,7 +532,7 @@ static int plic_probe(struct platform_device *pdev)
plic_quirks = (unsigned long)id->data;
}
- error = plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts);
+ error = plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts, &gsi_base, &id);
if (error)
return error;
@@ -509,6 +543,8 @@ static int plic_probe(struct platform_device *pdev)
priv->dev = dev;
priv->plic_quirks = plic_quirks;
priv->nr_irqs = nr_irqs;
+ priv->gsi_base = gsi_base;
+ priv->id = id;
priv->regs = devm_platform_ioremap_resource(pdev, 0);
if (WARN_ON(!priv->regs))
@@ -519,12 +555,22 @@ static int plic_probe(struct platform_device *pdev)
return -ENOMEM;
for (i = 0; i < nr_contexts; i++) {
- error = plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu);
+ error = plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu, priv->id);
if (error) {
dev_warn(dev, "hwirq for context%d not found\n", i);
continue;
}
+ if (is_of_node(dev->fwnode)) {
+ context_id = i;
+ } else {
+ context_id = acpi_get_plic_context(priv->id, i);
+ if (context_id == INVALID_CONTEXT) {
+ dev_warn(dev, "invalid context id for context%d\n", i);
+ continue;
+ }
+ }
+
/*
* Skip contexts other than external interrupts for our
* privilege level.
@@ -562,10 +608,10 @@ static int plic_probe(struct platform_device *pdev)
cpumask_set_cpu(cpu, &priv->lmask);
handler->present = true;
handler->hart_base = priv->regs + CONTEXT_BASE +
- i * CONTEXT_SIZE;
+ context_id * CONTEXT_SIZE;
raw_spin_lock_init(&handler->enable_lock);
handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE +
- i * CONTEXT_ENABLE_SIZE;
+ context_id * CONTEXT_ENABLE_SIZE;
handler->priv = priv;
handler->enable_save = devm_kcalloc(dev, DIV_ROUND_UP(nr_irqs, 32),
@@ -581,8 +627,8 @@ static int plic_probe(struct platform_device *pdev)
nr_handlers++;
}
- priv->irqdomain = irq_domain_add_linear(to_of_node(dev->fwnode), nr_irqs + 1,
- &plic_irqdomain_ops, priv);
+ priv->irqdomain = irq_domain_create_linear(dev->fwnode, nr_irqs + 1,
+ &plic_irqdomain_ops, priv);
if (WARN_ON(!priv->irqdomain))
goto fail_cleanup_contexts;
@@ -619,13 +665,18 @@ static int plic_probe(struct platform_device *pdev)
}
}
+#ifdef CONFIG_ACPI
+ if (!acpi_disabled)
+ acpi_dev_clear_dependencies(ACPI_COMPANION(dev));
+#endif
+
dev_info(dev, "mapped %d interrupts with %d handlers for %d contexts.\n",
nr_irqs, nr_handlers, nr_contexts);
return 0;
fail_cleanup_contexts:
for (i = 0; i < nr_contexts; i++) {
- if (plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu))
+ if (plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu, priv->id))
continue;
if (parent_hwirq != RV_IRQ_EXT || cpu < 0)
continue;
@@ -644,6 +695,7 @@ static struct platform_driver plic_driver = {
.driver = {
.name = "riscv-plic",
.of_match_table = plic_match,
+ .acpi_match_table = ACPI_PTR(plic_acpi_match),
},
.probe = plic_probe,
};
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-07-29 14:24 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-29 14:22 [PATCH v7 00/17] RISC-V: ACPI: Add external interrupt controller support Sunil V L
2024-07-29 14:22 ` Sunil V L
2024-07-29 14:22 ` [PATCH v7 01/17] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Sunil V L
2024-07-29 14:22 ` Sunil V L
2024-07-29 14:22 ` [PATCH v7 02/17] ACPI: scan: Add a weak function to reorder the IRQCHIP probe Sunil V L
2024-07-29 14:22 ` Sunil V L
2024-07-31 19:41 ` Bjorn Helgaas
2024-07-31 19:41 ` Bjorn Helgaas
2024-07-29 14:22 ` [PATCH v7 03/17] ACPI: bus: Add acpi_riscv_init function Sunil V L
2024-07-29 14:22 ` Sunil V L
2024-07-31 19:42 ` Bjorn Helgaas
2024-07-31 19:42 ` Bjorn Helgaas
2024-07-29 14:22 ` [PATCH v7 04/17] ACPI: scan: Refactor dependency creation Sunil V L
2024-07-29 14:22 ` Sunil V L
2024-07-29 14:22 ` [PATCH v7 05/17] ACPI: scan: Add RISC-V interrupt controllers to honor list Sunil V L
2024-07-29 14:22 ` Sunil V L
2024-07-29 14:22 ` [PATCH v7 06/17] ACPI: scan: Define weak function to populate dependencies Sunil V L
2024-07-29 14:22 ` Sunil V L
2024-07-29 14:22 ` [PATCH v7 07/17] ACPI: bus: Add RINTC IRQ model for RISC-V Sunil V L
2024-07-29 14:22 ` Sunil V L
2024-07-29 14:22 ` [PATCH v7 08/17] ACPI: pci_link: Clear the dependencies after probe Sunil V L
2024-07-29 14:22 ` Sunil V L
2024-07-31 19:49 ` Bjorn Helgaas
2024-07-31 19:49 ` Bjorn Helgaas
2025-12-01 13:07 ` huyuye
2025-12-01 13:07 ` huyuye
2025-12-01 13:33 ` [PATCH " Sunil V L
2025-12-01 13:33 ` Sunil V L
2025-12-01 14:12 ` huyuye
2025-12-01 14:12 ` huyuye
2025-12-02 4:28 ` [PATCH " Sunil V L
2025-12-02 4:28 ` Sunil V L
2024-07-29 14:22 ` [PATCH v7 09/17] ACPI: RISC-V: Implement PCI related functionality Sunil V L
2024-07-29 14:22 ` Sunil V L
2024-07-29 14:22 ` [PATCH v7 10/17] ACPI: RISC-V: Implement function to reorder irqchip probe entries Sunil V L
2024-07-29 14:22 ` Sunil V L
2024-07-29 14:22 ` [PATCH v7 11/17] ACPI: RISC-V: Initialize GSI mapping structures Sunil V L
2024-07-29 14:22 ` Sunil V L
2024-07-29 14:22 ` [PATCH v7 12/17] ACPI: RISC-V: Implement function to add implicit dependencies Sunil V L
2024-07-29 14:22 ` Sunil V L
2024-07-29 14:22 ` [PATCH v7 13/17] irqchip/riscv-intc: Add ACPI support for AIA Sunil V L
2024-07-29 14:22 ` Sunil V L
2024-08-06 15:22 ` Anup Patel
2024-08-06 15:22 ` Anup Patel
2024-07-29 14:22 ` [PATCH v7 14/17] irqchip/riscv-imsic-state: Create separate function for DT Sunil V L
2024-07-29 14:22 ` Sunil V L
2024-08-06 15:25 ` Anup Patel
2024-08-06 15:25 ` Anup Patel
2024-07-29 14:22 ` [PATCH v7 15/17] irqchip/riscv-imsic: Add ACPI support Sunil V L
2024-07-29 14:22 ` Sunil V L
2024-08-06 15:30 ` Anup Patel
2024-08-06 15:30 ` Anup Patel
2024-07-29 14:22 ` [PATCH v7 16/17] irqchip/riscv-aplic: " Sunil V L
2024-07-29 14:22 ` Sunil V L
2024-08-06 15:54 ` Anup Patel
2024-08-06 15:54 ` Anup Patel
2024-07-29 14:22 ` Sunil V L [this message]
2024-07-29 14:22 ` [PATCH v7 17/17] irqchip/sifive-plic: " Sunil V L
2024-08-06 15:59 ` Anup Patel
2024-08-06 15:59 ` Anup Patel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240729142241.733357-18-sunilvl@ventanamicro.com \
--to=sunilvl@ventanamicro.com \
--cc=ajones@ventanamicro.com \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=atishp@rivosinc.com \
--cc=bhelgaas@google.com \
--cc=catalin.marinas@arm.com \
--cc=conor.dooley@microchip.com \
--cc=dfustini@tenstorrent.com \
--cc=haibo1.xu@intel.com \
--cc=lenb@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=rafael@kernel.org \
--cc=robert.moore@intel.com \
--cc=samuel.holland@sifive.com \
--cc=tglx@linutronix.de \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.