From: Octavian Purdila <tavip@google.com>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, stefanst@google.com, pbonzini@redhat.com,
alex.bennee@linaro.org, thuth@redhat.com,
peter.maydell@linaro.org, marcandre.lureau@redhat.com,
alistair@alistair23.me, berrange@redhat.com, philmd@linaro.org,
jsnow@redhat.com, crosa@redhat.com, bleal@redhat.com
Subject: [RFC PATCH 04/23] hw/arm: add SVD file for NXP i.MX RT595
Date: Mon, 5 Aug 2024 13:16:59 -0700 [thread overview]
Message-ID: <20240805201719.2345596-5-tavip@google.com> (raw)
In-Reply-To: <20240805201719.2345596-1-tavip@google.com>
Picked from:
https://github.com/nxp-mcuxpresso/mcux-soc-svd/blob/main/MIMXRT595S/MIMXRT595S_cm33.xml
NOTE: the file is truncated to keep the email size reasonable. Please
use the link above and download the full file if you want to try out
the patch.
Signed-off-by: Octavian Purdila <tavip@google.com>
---
hw/arm/svd/MIMXRT595S_cm33.xml | 224052 ++++++++++++++++++++++++++++++
1 file changed, 224052 insertions(+)
create mode 100644 hw/arm/svd/MIMXRT595S_cm33.xml
diff --git a/hw/arm/svd/MIMXRT595S_cm33.xml b/hw/arm/svd/MIMXRT595S_cm33.xml
new file mode 100644
index 0000000000..8943aa3555
--- /dev/null
+++ b/hw/arm/svd/MIMXRT595S_cm33.xml
@@ -0,0 +1,1725 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+ <vendor>nxp.com</vendor>
+ <name>MIMXRT595S_cm33</name>
+ <version>1.0</version>
+ <description>MIMXRT595SFAWC,MIMXRT595SFFOC</description>
+ <licenseText>
+Copyright 2016-2023 NXP
+SPDX-License-Identifier: BSD-3-Clause
+ </licenseText>
+ <cpu>
+ <name>CM33</name>
+ <revision>r2p0</revision>
+ <endian>little</endian>
+ <mpuPresent>true</mpuPresent>
+ <fpuPresent>true</fpuPresent>
+ <vtorPresent>true</vtorPresent>
+ <nvicPrioBits>3</nvicPrioBits>
+ <vendorSystickConfig>false</vendorSystickConfig>
+ </cpu>
+ <addressUnitBits>8</addressUnitBits>
+ <width>32</width>
+ <peripherals>
+ <peripheral>
+ <name>RSTCTL0</name>
+ <description>Reset Controller 0</description>
+ <groupName>RSTCTL0</groupName>
+ <baseAddress>0x40000000</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x7C</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>SYSRSTSTAT</name>
+ <description>System Reset Status Register</description>
+ <addressOffset>0</addressOffset>
+ <size>32</size>
+ <access>read-write</access>
+ <resetValue>0x1</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>VDD_POR</name>
+ <description>VDD CORE Power-On Reset (POR) was detected</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>VDD_POR_EVENT_IS_NOT_DETECTED</name>
+ <description>No VDD CORE POR event is detected</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>VDD_POR_EVENT_WAS_DETECTED</name>
+ <description>VDD CORE POR event was detected</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PAD_RESET</name>
+ <description>RESETN pin reset was detected</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>PAD_RESET_IS_NOT_DETECTED</name>
+ <description>No RESETN pin event is detected</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PAD_RESET_WAS_DETECTED</name>
+ <description>RESETN pin event was detected. Write '1' to clear this bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ARM_RESET</name>
+ <description>ARM reset was detected</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ARM_RESET_IS_NOT_DETECTED</name>
+ <description>No ARM reset event is detected</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ARM_RESET_WAS_DETECTED</name>
+ <description>ARM reset was detected. Write '1' to clear this bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>WDT0_RESET</name>
+ <description>WatchDog Timer 0 reset was detected</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>WDT0_RESET_IS_NOT_DETECTED</name>
+ <description>No WDT0 reset event detected</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>WDT0_RESET_WAS_DETECTED</name>
+ <description>WDT0 reset event detected. Write '1' to clear this bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>WDT1_RESET</name>
+ <description>WatchDog Timer 1 reset was detected</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>WDT1_RESET_IS_NOT_DETECTED</name>
+ <description>No WDT1 reset event detected</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>WDT1_RESET_WAS_DETECTED</name>
+ <description>WDT1 reset event detected. Write '1' to clear this bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PRSTCTL0</name>
+ <description>Peripheral Reset Control Register 0</description>
+ <addressOffset>0x10</addressOffset>
+ <size>32</size>
+ <access>read-write</access>
+ <resetValue>0x7DF51F0A</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DSP</name>
+ <description>Fusion F1 DSP reset control</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>DSP_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DSP_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>AXI_SWITCH</name>
+ <description>AXI Switch reset control</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>AXI_SWITCH_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AXI_SWITCH_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>POWERQUAD</name>
+ <description>POWERQUAD reset control</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>POWERQUAD_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>POWERQUAD_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CASPER</name>
+ <description>CASPER reset control</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>CASPER_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CASPER_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>HASHCRYPT</name>
+ <description>Hash-Crypt reset control</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>HASHCRYPT_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>HASHCRYPT_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PUF</name>
+ <description>PUF reset control</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>PUF_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PUF_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RNG</name>
+ <description>RNG reset control</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>RNG_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RNG_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>FLEXSPI0_OTFAD</name>
+ <description>FLEXSPI0 and OTFAD reset control</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>FLEXSPI0_OTFAD_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FLEXSPI0_OTFAD_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>FLEXSPI1</name>
+ <description>FLEXSPI1 reset control</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>FLEXSPI1_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FLEXSPI1_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>USBHS_PHY</name>
+ <description>USB PHY reset control</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>USBHS_PHY_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USBHS_PHY_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>USBHS_DEVICE</name>
+ <description>USB HS Device reset control</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>USBHS_DEVICE_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USBHS_DEVICE_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>USBHS_HOST</name>
+ <description>USB HOST reset control</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>USBHS_HOST_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USBHS_HOST_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>USBHS_SRAM</name>
+ <description>USB RAM reset control</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>USBHS_SRAM_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USBHS_SRAM_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SCT</name>
+ <description>SCTimer reset control</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SCT_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SCT_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>GPU</name>
+ <description>GPU reset control</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>GPU_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>GPU_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DISPLAY_CONTROLLER</name>
+ <description>LCDIF Display Controller reset control</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>DISPLAY_CONTROLLER_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISPLAY_CONTROLLER_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MIPI_DSI_CONTROLLER</name>
+ <description>MIPI Digital serial Interface controller reset control</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>MIPI_DSI_CONTROLLER_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MIPI_DSI_CONTROLLER_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MIPI_DSI_PHY</name>
+ <description>MIPI DSI PHY reset control</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>MIPI_DSI_PHY_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MIPI_DSI_PHY_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SMARTDMA</name>
+ <description>SMARTDMA Event/Algorithm handler reset control</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SMARTDMA_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SMARTDMA_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PRSTCTL1</name>
+ <description>Peripheral Reset Control Register 1</description>
+ <addressOffset>0x14</addressOffset>
+ <size>32</size>
+ <access>read-write</access>
+ <resetValue>0x101800C</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>SDIO0</name>
+ <description>SDIO0 reset control</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SDIO0_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SDIO0_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SDIO1</name>
+ <description>SDIO1 reset control</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SDIO1_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SDIO1_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ACMP0</name>
+ <description>Analog comparator reset control</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ACMP0_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ACMP0_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ADC0</name>
+ <description>Analog-to-Digital converter reset control</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ADC0_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ADC0_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SHSGPIO0</name>
+ <description>Secure GPIO 0 reset control</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SHSGPIO0_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SHSGPIO0_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PRSTCTL2</name>
+ <description>Peripheral Reset Control Register 2</description>
+ <addressOffset>0x18</addressOffset>
+ <size>32</size>
+ <access>read-write</access>
+ <resetValue>0x1C000001</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>UTICK0</name>
+ <description>Micro-tick timer reset control</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>UTICK0_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>UTICK0_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>WWDT0</name>
+ <description>Watchdog timer reset control</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>WWDT0_CLR</name>
+ <description>Clear Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>WWDT0_SET</name>
+ <description>Set Reset</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PRSTCTL0_SET</name>
+ <description>Peripheral Reset Control Register 0 SET</description>
+ <addressOffset>0x40</addressOffset>
+ <size>32</size>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>DSP</name>
+ <description>Fusion_ DSP reset set</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>DSP_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DSP_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>AXI_SWITCH</name>
+ <description>AXI SWITCH reset set</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>AXI_SWITCH_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AXI_SWITCH_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>POWERQUAD</name>
+ <description>POWERQUAD reset set</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>POWERQUAD_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>POWERQUAD_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CASPER</name>
+ <description>CASPER reset set</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>CASPER_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CASPER_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>HASHCRYPT</name>
+ <description>HASHCRYPT reset set</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>HASHCRYPT_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>HASHCRYPT_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PUF</name>
+ <description>PUF reset set</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>PUF_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PUF_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RNG</name>
+ <description>RNG reset set</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>RNG_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RNG_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>FLEXSPI0_OTFAD</name>
+ <description>FLEXSPI0 and OTFAD reset set</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>FLEXSPI0_OTFAD_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FLEXSPI0_OTFAD_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>FLEXSPI1</name>
+ <description>FLEXSPI1 reset set</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>FLEXSPI1_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FLEXSPI1_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>USBHS_PHY</name>
+ <description>USB PHY reset set</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>USBHS_PHY_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USBHS_PHY_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>USBHS_DEVICE</name>
+ <description>USB Device reset set</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>USBHS_DEVICE_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USBHS_DEVICE_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>USBHS_HOST</name>
+ <description>USB HOST reset set</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>USBHS_HOST_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USBHS_HOST_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>USBHS_SRAM</name>
+ <description>USBHS SRAM reset set</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>USBHS_SRAM_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USBHS_SRAM_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SCT</name>
+ <description>SCTimer reset set</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SCT_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SCT_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>GPU</name>
+ <description>GPU reset set</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>GPU_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>GPU_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DISPLAY_CONTROLLER</name>
+ <description>LCDIF DISPLAY CONTROLLER reset set</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>DISPLAY_CONTROLLER_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISPLAY_CONTROLLER_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MIPI_DSI_CONTROLLER</name>
+ <description>MIPI DSI controller reset set</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>MIPI_DSI_CONTROLLER_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MIPI_DSI_CONTROLLER_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MIPI_DSI_PHY</name>
+ <description>MIPI DSI PHY reset set</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>MIPI_DSI_PHY_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MIPI_DSI_PHY_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SMARTDMA</name>
+ <description>SMARTDMA Event/Algorithm handler reset set</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SMARTDMA_CLR</name>
+ <description>No Effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SMARTDMA_SET</name>
+ <description>Sets the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PRSTCTL1_SET</name>
+ <description>Peripheral Reset Control Register 1 SET</description>
+ <addressOffset>0x44</addressOffset>
+ <size>32</size>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>SDIO0</name>
+ <description>SDIO0 reset set</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SDIO0_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SDIO0_SET</name>
+ <description>Sets the PRSTCTL1 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SDIO1</name>
+ <description>SDIO1 reset set</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SDIO1_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SDIO1_SET</name>
+ <description>Sets the PRSTCTL1 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ACMP0</name>
+ <description>ACMP0 reset set</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ACMP0_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ACMP0_SET</name>
+ <description>Sets the PRSTCTL1 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ADC0</name>
+ <description>ADC0 reset set</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ADC0_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ADC0_SET</name>
+ <description>Sets the PRSTCTL1 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SHSGPIO0</name>
+ <description>SHSGPIO0 reset set</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SHSGPIO0_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SHSGPIO0_SET</name>
+ <description>Sets the PRSTCTL1 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PRSTCTL2_SET</name>
+ <description>Peripheral Reset Control Register 2 SET</description>
+ <addressOffset>0x48</addressOffset>
+ <size>32</size>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>UTICK0</name>
+ <description>Micro-tick timer 0 reset set</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>UTICK0_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>UTICK0_SET</name>
+ <description>Sets the PRSTCTL2 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>WWDT0</name>
+ <description>WWDT0 reset set</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>WWDT0_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>WWDT0_SET</name>
+ <description>Sets the PRSTCTL2 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PRSTCTL0_CLR</name>
+ <description>Peripheral Reset Control Register 0 CLR</description>
+ <addressOffset>0x70</addressOffset>
+ <size>32</size>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>DSP</name>
+ <description>Fusion_ F1 DSP reset clear</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>DSP_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DSP_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>AXI_SWITCH</name>
+ <description>AXI SWITCH reset clear</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>AXI_SWITCH_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AXI_SWITCH_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>POWERQUAD</name>
+ <description>POWERQUAD reset clear</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>POWERQUAD_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>POWERQUAD_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CASPER</name>
+ <description>CASPER reset clear</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>CASPER_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CASPER_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>HASHCRYPT</name>
+ <description>HASHCRYPT reset clear</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>HASHCRYPT_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>HASHCRYPT_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PUF</name>
+ <description>PUF reset clear</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>PUF_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PUF_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RNG</name>
+ <description>RNG reset clear</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>RNG_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RNG_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>FLEXSPI0_OTFAD</name>
+ <description>FLEXSPI0 and OTFAD reset clear</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>FLEXSPI0_OTFAD_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FLEXSPI0_OTFAD_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>FLEXSPI1</name>
+ <description>FLEXSPI1 reset clear</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>FLEXSPI1_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FLEXSPI1_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>USBHS_PHY</name>
+ <description>USB PHY reset clear</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>USBHS_PHY_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USBHS_PHY_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>USBHS_DEVICE</name>
+ <description>USB DEVICE reset clear</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>USBHS_DEVICE_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USBHS_DEVICE_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>USBHS_HOST</name>
+ <description>USB HOST reset clear</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>USBHS_HOST_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USBHS_HOST_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>USBHS_SRAM</name>
+ <description>USBHS SRAM reset clear</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>USBHS_SRAM_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USBHS_SRAM_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SCT</name>
+ <description>SCT reset clear</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SCT_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SCT_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>GPU</name>
+ <description>GPU reset clear</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>GPU_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>GPU_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DISPLAY_CONTROLLER</name>
+ <description>LCDIF DISPLAY CONTROLLER reset clear</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>DISPLAY_CONTROLLER_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISPLAY_CONTROLLER_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MIPI_DSI_CONTROLLER</name>
+ <description>MIPI DSI controller reset clear</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>MIPI_DSI_CONTROLLER_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MIPI_DSI_CONTROLLER_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MIPI_DSI_PHY</name>
+ <description>MIPI DSI PHY reset clear</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>MIPI_DSI_PHY_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MIPI_DSI_PHY_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SMARTDMA</name>
+ <description>SMARTDMA Event/Algorithm handler reset clear</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SMARTDMA_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SMARTDMA_SET</name>
+ <description>Clears the PRSTCTL0 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PRSTCTL1_CLR</name>
+ <description>Peripheral Reset Control Register 1 CLR</description>
+ <addressOffset>0x74</addressOffset>
+ <size>32</size>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>SDIO0</name>
+ <description>SDIO0 reset clear</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SDIO0_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SDIO0_SET</name>
+ <description>Clears the PRSTCTL1 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SDIO1</name>
+ <description>SDIO1 reset clear</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SDIO1_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SDIO1_SET</name>
+ <description>Clears the PRSTCTL1 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ACMP0</name>
+ <description>ACMP0 reset clear</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ACMP0_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ACMP0_SET</name>
+ <description>Clears the PRSTCTL1 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ADC0</name>
+ <description>ADC0 reset clear</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ADC0_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ADC0_SET</name>
+ <description>Clears the PRSTCTL1 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SHSGPIO0</name>
+ <description>Secure HSGPIO0 reset clear</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SHSGPIO0_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SHSGPIO0_SET</name>
+ <description>Clears the PRSTCTL1 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PRSTCTL2_CLR</name>
+ <description>Peripheral Reset Control Register 2 CLR</description>
+ <addressOffset>0x78</addressOffset>
+ <size>32</size>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>UTICK0</name>
+ <description>Micro-tick timer 0 reset clear</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>UTICK0_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>UTICK0_SET</name>
+ <description>Clears the PRSTCTL2 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>WWDT0</name>
+ <description>WWDT0 reset clear</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>WWDT0_CLR</name>
+ <description>No effect</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>WWDT0_SET</name>
+ <description>Clears the PRSTCTL2 Bit</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ </peripherals>
+</device>
\ No newline at end of file
--
2.46.0.rc2.264.g509ed76dc8-goog
next prev parent reply other threads:[~2024-08-05 20:17 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-05 20:16 [RFC PATCH 00/23] NXP i.MX RT595, ARM SVD and device model unit tests Octavian Purdila
2024-08-05 20:16 ` [RFC PATCH 01/23] fifo32: add peek function Octavian Purdila
2024-08-05 20:16 ` [RFC PATCH 02/23] tests/unit: add fifo test Octavian Purdila
2024-08-05 20:16 ` [RFC PATCH 03/23] scripts: add script to generate C header files from SVD XML files Octavian Purdila
2024-08-08 21:56 ` John Snow
2024-08-08 22:30 ` Octavian Purdila
2024-08-08 23:06 ` John Snow
2024-08-09 9:30 ` Philippe Mathieu-Daudé
2024-08-09 9:42 ` Paolo Bonzini
2024-08-09 9:59 ` Daniel P. Berrangé
2024-08-13 8:32 ` Philippe Mathieu-Daudé
2024-08-09 6:34 ` Paolo Bonzini
2024-08-09 19:28 ` Octavian Purdila
2024-08-12 15:27 ` Peter Maydell
2024-08-12 17:56 ` Octavian Purdila
2024-08-12 22:43 ` Richard Henderson
2024-08-13 15:47 ` Octavian Purdila
2024-08-05 20:16 ` Octavian Purdila [this message]
2024-08-06 14:06 ` [RFC PATCH 04/23] hw/arm: add SVD file for NXP i.MX RT595 Alex Bennée
2024-08-06 20:31 ` Octavian Purdila
2024-08-07 11:24 ` Philippe Mathieu-Daudé
2024-08-07 16:36 ` Octavian Purdila
2024-08-09 9:13 ` Daniel P. Berrangé
2024-08-09 22:40 ` Octavian Purdila
2024-08-05 20:17 ` [RFC PATCH 05/23] hw: add register access utility functions Octavian Purdila
2024-08-12 15:32 ` Peter Maydell
2024-08-12 21:14 ` Octavian Purdila
2024-08-12 22:35 ` Richard Henderson
2024-08-13 8:28 ` Philippe Mathieu-Daudé
2024-08-05 20:17 ` [RFC PATCH 06/23] hw/misc: add basic flexcomm device model Octavian Purdila
2024-08-05 20:17 ` [RFC PATCH 07/23] tests/unit: add system bus mock Octavian Purdila
2024-08-05 20:17 ` [RFC PATCH 08/23] test/unit: add register access macros and functions Octavian Purdila
2024-08-05 20:17 ` [RFC PATCH 09/23] test/unit: add flexcomm unit test Octavian Purdila
2024-08-05 20:17 ` [RFC PATCH 10/23] hw/char: add support for flexcomm usart Octavian Purdila
2024-08-05 20:17 ` [RFC PATCH 11/23] test/unit: add flexcomm usart unit test Octavian Purdila
2024-08-05 20:17 ` [RFC PATCH 12/23] hw/i2c: add support for flexcomm i2c Octavian Purdila
2024-08-05 20:17 ` [RFC PATCH 13/23] test/unit: add i2c-tester Octavian Purdila
2024-08-05 20:17 ` [RFC PATCH 14/23] test/unit: add unit tests for flexcomm i2c Octavian Purdila
2024-08-05 20:17 ` [RFC PATCH 15/23] hw/ssi: add support for flexcomm spi Octavian Purdila
2024-08-05 20:17 ` [RFC PATCH 16/23] test/unit: add spi-tester Octavian Purdila
2024-08-05 20:17 ` [RFC PATCH 17/23] test/unit: add unit tests for flexcomm spi Octavian Purdila
2024-08-05 20:17 ` [RFC PATCH 18/23] hw/misc: add support for RT500's clock controller Octavian Purdila
2024-08-05 20:17 ` [RFC PATCH 19/23] test/unit: add unit tests " Octavian Purdila
2024-08-05 20:17 ` [RFC PATCH 20/23] hw/ssi: add support for flexspi Octavian Purdila
2024-08-08 5:11 ` Philippe Mathieu-Daudé
2024-08-08 21:31 ` Octavian Purdila
2024-08-09 8:54 ` Philippe Mathieu-Daudé
2024-08-05 20:17 ` [RFC PATCH 21/23] hw/misc: add support for RT500 reset controller Octavian Purdila
2024-08-08 5:00 ` Philippe Mathieu-Daudé
2024-08-05 20:17 ` [RFC PATCH 22/23] hw/arm: add basic support for the RT500 SoC Octavian Purdila
2024-08-06 14:51 ` Philippe Mathieu-Daudé
2024-08-07 23:57 ` Octavian Purdila
2024-08-05 20:17 ` [RFC PATCH 23/23] hw/arm: add RT595-EVK board Octavian Purdila
2024-08-12 16:10 ` [RFC PATCH 00/23] NXP i.MX RT595, ARM SVD and device model unit tests Peter Maydell
2024-08-12 16:22 ` Daniel P. Berrangé
2024-08-12 18:39 ` Octavian Purdila
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