From: Mayuresh Chitale <mchitale@ventanamicro.com>
To: u-boot@lists.denx.de
Cc: Mayuresh Chitale <mchitale@ventanamicro.com>,
Rick Chen <rick@andestech.com>, Leo <ycliang@andestech.com>,
Tom Rini <trini@konsulko.com>,
Heinrich Schuchardt <xypron.glpk@gmx.de>,
Michal Simek <michal.simek@amd.com>,
Kongyang Liu <seashell11234455@gmail.com>,
Randolph <randolph@andestech.com>,
Yu Chien Peter Lin <peterlin@andestech.com>,
Ben Dooks <ben.dooks@codethink.co.uk>,
Samuel Holland <samuel@sholland.org>,
Dan Carpenter <dan.carpenter@linaro.org>
Subject: [PATCH v2 0/2] Risc-V cache operations
Date: Fri, 23 Aug 2024 09:41:24 +0000 [thread overview]
Message-ID: <20240823094127.207866-1-mchitale@ventanamicro.com> (raw)
This patchset adds support for using the CBO instructions to perform the
dcache flush/inval operations for the qemu-riscv board when those are
enabled. The CBO instructions are defined in the Risc-V CMO specification
which can be found at the link below:
https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.pdf
Changes in v2:
- Use cache functions in generic cache code instead of board specific code
- Print the zicbom init status in case of a failure
Mayuresh Chitale (2):
riscv: Add support for defining instructions
riscv: cache: Add CBO instructions
arch/riscv/Kconfig | 4 ++
arch/riscv/include/asm/insn-def.h | 42 ++++++++++++++
arch/riscv/lib/cache.c | 96 +++++++++++++++++++++++++++++++
3 files changed, 142 insertions(+)
create mode 100644 arch/riscv/include/asm/insn-def.h
--
2.34.1
next reply other threads:[~2024-08-23 9:41 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-23 9:41 Mayuresh Chitale [this message]
2024-08-23 9:41 ` [PATCH v2 1/2] riscv: Add support for defining instructions Mayuresh Chitale
2024-10-28 10:24 ` Leo Liang
2024-08-23 9:41 ` [PATCH v2 2/2] riscv: cache: Add CBO instructions Mayuresh Chitale
2024-10-28 10:45 ` Leo Liang
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