From: Leo Liang <ycliang@andestech.com>
To: Mayuresh Chitale <mchitale@ventanamicro.com>
Cc: <u-boot@lists.denx.de>, Rick Chen <rick@andestech.com>,
Tom Rini <trini@konsulko.com>,
Heinrich Schuchardt <xypron.glpk@gmx.de>,
Michal Simek <michal.simek@amd.com>,
Kongyang Liu <seashell11234455@gmail.com>,
Randolph <randolph@andestech.com>,
Yu Chien Peter Lin <peterlin@andestech.com>,
"Ben Dooks" <ben.dooks@codethink.co.uk>,
Samuel Holland <samuel@sholland.org>,
"Dan Carpenter" <dan.carpenter@linaro.org>
Subject: Re: [PATCH v2 2/2] riscv: cache: Add CBO instructions
Date: Mon, 28 Oct 2024 18:45:52 +0800 [thread overview]
Message-ID: <Zx9rYMT2gzohz0kZ@swlinux02> (raw)
In-Reply-To: <20240823094127.207866-3-mchitale@ventanamicro.com>
On Fri, Aug 23, 2024 at 09:41:26AM +0000, Mayuresh Chitale wrote:
> Define CBO inval and flush instructions and use those for the
> dcache inval and flush operations respectively.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> ---
> arch/riscv/Kconfig | 4 ++
> arch/riscv/lib/cache.c | 96 ++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 100 insertions(+)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
prev parent reply other threads:[~2024-10-28 10:46 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-23 9:41 [PATCH v2 0/2] Risc-V cache operations Mayuresh Chitale
2024-08-23 9:41 ` [PATCH v2 1/2] riscv: Add support for defining instructions Mayuresh Chitale
2024-10-28 10:24 ` Leo Liang
2024-08-23 9:41 ` [PATCH v2 2/2] riscv: cache: Add CBO instructions Mayuresh Chitale
2024-10-28 10:45 ` Leo Liang [this message]
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