From: Pavel Skripkin <paskripkin@gmail.com>
To: jim.shu@sifive.com
Cc: alistair.francis@wdc.com, arikalo@gmail.com, atar4qemu@gmail.com,
aurelien@aurel32.net, bmeng.cn@gmail.com, david@redhat.com,
dbarboza@ventanamicro.com, edgar.iglesias@gmail.com,
eduardo@habkost.net, gaosong@loongson.cn, iii@linux.ibm.com,
jcmvbkbc@gmail.com, jiaxun.yang@flygoat.com,
kbastian@mail.uni-paderborn.de, laurent@vivier.eu,
liwei1518@gmail.com, marcel.apfelbaum@gmail.com,
mark.cave-ayland@ilande.co.uk, mrolnik@gmail.com,
npiggin@gmail.com, palmer@dabbelt.com, pbonzini@redhat.com,
peter.maydell@linaro.org, peterx@redhat.com, philmd@linaro.org,
qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
qemu-riscv@nongnu.org, qemu-s390x@nongnu.org,
richard.henderson@linaro.org, shorne@gmail.com, thuth@redhat.com,
wangyanan55@huawei.com, ysato@users.sourceforge.jp,
zhiwei_liu@linux.alibaba.com
Subject: Re: [RFC PATCH 00/16] Implements RISC-V WorldGuard extension v0.4
Date: Sat, 7 Sep 2024 21:06:21 +0300 [thread overview]
Message-ID: <20240907180621.60916-1-paskripkin@gmail.com> (raw)
In-Reply-To: <20240612081416.29704-1-jim.shu@sifive.com>
Dear, Jim Shu
Thank you for your work!
Do you plan to work futher on this series? Seems like current version is no longer applicable to
current master.
Also, I really wonder how did you test these changes? Like is there a way I could build some binary
and run it in trusted mode? Should there be an SBI support for that?
With regards,
Pavel Skripkin
prev parent reply other threads:[~2024-09-07 20:20 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-12 8:14 [RFC PATCH 00/16] Implements RISC-V WorldGuard extension v0.4 Jim Shu
2024-06-12 8:14 ` [RFC PATCH 01/16] accel/tcg: Store section pointer in CPUTLBEntryFull Jim Shu
2024-06-13 6:22 ` LIU Zhiwei
2024-06-13 10:37 ` Jim Shu
2024-06-14 13:28 ` LIU Zhiwei
2024-06-12 8:14 ` [RFC PATCH 02/16] accel/tcg: memory access from CPU will pass access_type to IOMMU Jim Shu
2024-06-13 5:34 ` Ethan Chen via
2024-06-13 5:34 ` Ethan Chen via
2024-06-13 9:52 ` Jim Shu
2024-06-12 8:14 ` [RFC PATCH 03/16] exec: Add RISC-V WorldGuard WID to MemTxAttrs Jim Shu
2024-07-12 1:38 ` Alistair Francis
2024-06-12 8:14 ` [RFC PATCH 04/16] hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config Jim Shu
2024-07-12 1:41 ` Alistair Francis
2024-06-12 8:14 ` [RFC PATCH 05/16] target/riscv: Add CPU options of WorldGuard CPU extension Jim Shu
2024-07-12 1:42 ` Alistair Francis
2024-06-12 8:14 ` [RFC PATCH 06/16] target/riscv: Add hard-coded CPU state of WG extension Jim Shu
2024-07-12 1:44 ` Alistair Francis
2024-06-12 8:14 ` [RFC PATCH 07/16] target/riscv: Add defines for WorldGuard CSRs Jim Shu
2024-06-12 8:14 ` [RFC PATCH 08/16] target/riscv: Allow global WG config to set WG CPU callbacks Jim Shu
2024-06-12 8:14 ` [RFC PATCH 09/16] target/riscv: Implement WorldGuard CSRs Jim Shu
2024-06-12 8:14 ` [RFC PATCH 10/16] target/riscv: Add WID to MemTxAttrs of CPU memory transactions Jim Shu
2024-06-12 8:14 ` [RFC PATCH 11/16] hw/misc: riscv_worldguard: Add API to enable WG extension of CPU Jim Shu
2024-06-12 8:14 ` [RFC PATCH 12/16] hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker Jim Shu
2024-06-12 8:14 ` [RFC PATCH 13/16] hw/misc: riscv_wgchecker: Implement wgchecker slot registers Jim Shu
2024-06-12 8:14 ` [RFC PATCH 14/16] hw/misc: riscv_wgchecker: Implement correct block-access behavior Jim Shu
2024-06-12 8:14 ` [RFC PATCH 15/16] hw/misc: riscv_wgchecker: Check the slot settings in translate Jim Shu
2024-06-12 8:14 ` [RFC PATCH 16/16] hw/riscv: virt: Add WorldGuard support Jim Shu
2024-07-12 2:02 ` Alistair Francis
2024-09-07 18:06 ` Pavel Skripkin [this message]
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