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From: Ethan Chen via <qemu-riscv@nongnu.org>
To: Jim Shu <jim.shu@sifive.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Bin Meng" <bmeng.cn@gmail.com>,
	"Weiwei Li" <liwei1518@gmail.com>,
	"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
	"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Yanan Wang" <wangyanan55@huawei.com>,
	"Peter Xu" <peterx@redhat.com>,
	"David Hildenbrand" <david@redhat.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Michael Rolnik" <mrolnik@gmail.com>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Song Gao" <gaosong@loongson.cn>,
	"Laurent Vivier" <laurent@vivier.eu>,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	"Aleksandar Rikalo" <arikalo@gmail.com>,
	"Stafford Horne" <shorne@gmail.com>,
	"Nicholas Piggin" <npiggin@gmail.com>,
	"Yoshinori Sato" <ysato@users.sourceforge.jp>,
	"Ilya Leoshkevich" <iii@linux.ibm.com>,
	"Thomas Huth" <thuth@redhat.com>,
	"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
	"Artyom Tarasenko" <atar4qemu@gmail.com>,
	"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
	"Max Filippov" <jcmvbkbc@gmail.com>,
	"open list:ARM TCG CPUs" <qemu-arm@nongnu.org>,
	"open list:PowerPC TCG CPUs" <qemu-ppc@nongnu.org>,
	"open list:S390 TCG CPUs" <qemu-s390x@nongnu.org>
Subject: Re: [RFC PATCH 02/16] accel/tcg: memory access from CPU will pass access_type to IOMMU
Date: Thu, 13 Jun 2024 13:34:05 +0800	[thread overview]
Message-ID: <ZmqEzUPsJwFs7w4+@ethan84-VirtualBox> (raw)
In-Reply-To: <20240612081416.29704-3-jim.shu@sifive.com>

On Wed, Jun 12, 2024 at 04:14:02PM +0800, Jim Shu wrote:
> [EXTERNAL MAIL]
> 
> It is the preparation patch for upcoming RISC-V wgChecker device.
> 
> Since RISC-V wgChecker could permit access in RO/WO permission, the
> IOMMUMemoryRegion could return different section for read & write
> access. The memory access from CPU should also pass the access_type to
> IOMMU translate function so that IOMMU could return the correct section
> of specified access_type.
> 

Hi Jim,

Does this method take into account the situation where the CPU access type is
different from the access type when creating iotlb? I think the section
might be wrong in this situation.

Thanks,
Ethan
> 
> 


WARNING: multiple messages have this Message-ID (diff)
From: Ethan Chen via <qemu-devel@nongnu.org>
To: Jim Shu <jim.shu@sifive.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Bin Meng" <bmeng.cn@gmail.com>,
	"Weiwei Li" <liwei1518@gmail.com>,
	"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
	"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Yanan Wang" <wangyanan55@huawei.com>,
	"Peter Xu" <peterx@redhat.com>,
	"David Hildenbrand" <david@redhat.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Michael Rolnik" <mrolnik@gmail.com>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Song Gao" <gaosong@loongson.cn>,
	"Laurent Vivier" <laurent@vivier.eu>,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	"Aleksandar Rikalo" <arikalo@gmail.com>,
	"Stafford Horne" <shorne@gmail.com>,
	"Nicholas Piggin" <npiggin@gmail.com>,
	"Yoshinori Sato" <ysato@users.sourceforge.jp>,
	"Ilya Leoshkevich" <iii@linux.ibm.com>,
	"Thomas Huth" <thuth@redhat.com>,
	"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
	"Artyom Tarasenko" <atar4qemu@gmail.com>,
	"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
	"Max Filippov" <jcmvbkbc@gmail.com>,
	"open list:ARM TCG CPUs" <qemu-arm@nongnu.org>,
	"open list:PowerPC TCG CPUs" <qemu-ppc@nongnu.org>,
	"open list:S390 TCG CPUs" <qemu-s390x@nongnu.org>
Subject: Re: [RFC PATCH 02/16] accel/tcg: memory access from CPU will pass access_type to IOMMU
Date: Thu, 13 Jun 2024 13:34:05 +0800	[thread overview]
Message-ID: <ZmqEzUPsJwFs7w4+@ethan84-VirtualBox> (raw)
In-Reply-To: <20240612081416.29704-3-jim.shu@sifive.com>

On Wed, Jun 12, 2024 at 04:14:02PM +0800, Jim Shu wrote:
> [EXTERNAL MAIL]
> 
> It is the preparation patch for upcoming RISC-V wgChecker device.
> 
> Since RISC-V wgChecker could permit access in RO/WO permission, the
> IOMMUMemoryRegion could return different section for read & write
> access. The memory access from CPU should also pass the access_type to
> IOMMU translate function so that IOMMU could return the correct section
> of specified access_type.
> 

Hi Jim,

Does this method take into account the situation where the CPU access type is
different from the access type when creating iotlb? I think the section
might be wrong in this situation.

Thanks,
Ethan
> 
> 

  reply	other threads:[~2024-06-13  5:40 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-12  8:14 [RFC PATCH 00/16] Implements RISC-V WorldGuard extension v0.4 Jim Shu
2024-06-12  8:14 ` [RFC PATCH 01/16] accel/tcg: Store section pointer in CPUTLBEntryFull Jim Shu
2024-06-13  6:22   ` LIU Zhiwei
2024-06-13 10:37     ` Jim Shu
2024-06-14 13:28       ` LIU Zhiwei
2024-06-12  8:14 ` [RFC PATCH 02/16] accel/tcg: memory access from CPU will pass access_type to IOMMU Jim Shu
2024-06-13  5:34   ` Ethan Chen via [this message]
2024-06-13  5:34     ` Ethan Chen via
2024-06-13  9:52     ` Jim Shu
2024-06-12  8:14 ` [RFC PATCH 03/16] exec: Add RISC-V WorldGuard WID to MemTxAttrs Jim Shu
2024-07-12  1:38   ` Alistair Francis
2024-06-12  8:14 ` [RFC PATCH 04/16] hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config Jim Shu
2024-07-12  1:41   ` Alistair Francis
2024-06-12  8:14 ` [RFC PATCH 05/16] target/riscv: Add CPU options of WorldGuard CPU extension Jim Shu
2024-07-12  1:42   ` Alistair Francis
2024-06-12  8:14 ` [RFC PATCH 06/16] target/riscv: Add hard-coded CPU state of WG extension Jim Shu
2024-07-12  1:44   ` Alistair Francis
2024-06-12  8:14 ` [RFC PATCH 07/16] target/riscv: Add defines for WorldGuard CSRs Jim Shu
2024-06-12  8:14 ` [RFC PATCH 08/16] target/riscv: Allow global WG config to set WG CPU callbacks Jim Shu
2024-06-12  8:14 ` [RFC PATCH 09/16] target/riscv: Implement WorldGuard CSRs Jim Shu
2024-06-12  8:14 ` [RFC PATCH 10/16] target/riscv: Add WID to MemTxAttrs of CPU memory transactions Jim Shu
2024-06-12  8:14 ` [RFC PATCH 11/16] hw/misc: riscv_worldguard: Add API to enable WG extension of CPU Jim Shu
2024-06-12  8:14 ` [RFC PATCH 12/16] hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker Jim Shu
2024-06-12  8:14 ` [RFC PATCH 13/16] hw/misc: riscv_wgchecker: Implement wgchecker slot registers Jim Shu
2024-06-12  8:14 ` [RFC PATCH 14/16] hw/misc: riscv_wgchecker: Implement correct block-access behavior Jim Shu
2024-06-12  8:14 ` [RFC PATCH 15/16] hw/misc: riscv_wgchecker: Check the slot settings in translate Jim Shu
2024-06-12  8:14 ` [RFC PATCH 16/16] hw/riscv: virt: Add WorldGuard support Jim Shu
2024-07-12  2:02   ` Alistair Francis
2024-09-07 18:06 ` [RFC PATCH 00/16] Implements RISC-V WorldGuard extension v0.4 Pavel Skripkin

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