Re: [PATCH 19/21] arm64: dts: adi: sc598: add device tree

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* Re: [PATCH 19/21] arm64: dts: adi: sc598: add device tree
@ 2024-09-14 14:51 kernel test robot
  0 siblings, 0 replies; 5+ messages in thread
From: kernel test robot @ 2024-09-14 14:51 UTC (permalink / raw)
  To: oe-kbuild; +Cc: lkp

:::::: 
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
:::::: 

BCC: lkp@intel.com
CC: llvm@lists.linux.dev
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20240912-test-v1-19-458fa57c8ccf@analog.com>
References: <20240912-test-v1-19-458fa57c8ccf@analog.com>
TO: Arturs Artamonovs via B4 Relay <devnull+arturs.artamonovs.analog.com@kernel.org>
TO: Catalin Marinas <catalin.marinas@arm.com>
TO: Will Deacon <will@kernel.org>
TO: Greg Malysa <greg.malysa@timesys.com>
TO: Philipp Zabel <p.zabel@pengutronix.de>
TO: Rob Herring <robh@kernel.org>
TO: Krzysztof Kozlowski <krzk@kernel.org>
TO: Conor Dooley <conor+dt@kernel.org>
TO: Utsav Agarwal <Utsav.Agarwal@analog.com>
TO: Michael Turquette <mturquette@baylibre.com>
TO: Stephen Boyd <sboyd@kernel.org>
TO: Linus Walleij <linus.walleij@linaro.org>
TO: Bartosz Golaszewski <brgl@bgdev.pl>
TO: Thomas Gleixner <tglx@linutronix.de>
TO: Andi Shyti <andi.shyti@kernel.org>
TO: "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>
TO: Jiri Slaby <jirislaby@kernel.org>
TO: Arnd Bergmann <arnd@arndb.de>
TO: Olof Johansson <olof@lixom.net>
TO: soc@kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-kernel@vger.kernel.org
CC: devicetree@vger.kernel.org
CC: linux-clk@vger.kernel.org
CC: linux-gpio@vger.kernel.org
CC: linux-i2c@vger.kernel.org
CC: linux-serial@vger.kernel.org
CC: Arturs Artamonovs <arturs.artamonovs@analog.com>
CC: adsp-linux@analog.com
CC: "Nathan Barrett-Morrison" <nathan.morrison@timesys.com>

Hi Arturs,

kernel test robot noticed the following build warnings:

[auto build test WARNING on da3ea35007d0af457a0afc87e84fddaebc4e0b63]

url:    https://github.com/intel-lab-lkp/linux/commits/Arturs-Artamonovs-via-B4-Relay/arm64-Add-ADI-ADSP-SC598-SoC/20240913-022308
base:   da3ea35007d0af457a0afc87e84fddaebc4e0b63
patch link:    https://lore.kernel.org/r/20240912-test-v1-19-458fa57c8ccf%40analog.com
patch subject: [PATCH 19/21] arm64: dts: adi: sc598: add device tree
:::::: branch date: 2 days ago
:::::: commit date: 2 days ago
config: arm64-randconfig-001-20240913 (https://download.01.org/0day-ci/archive/20240914/202409142227.G2feVa8Y-lkp@intel.com/config)
compiler: clang version 15.0.7 (https://github.com/llvm/llvm-project 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240914/202409142227.G2feVa8Y-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202409142227.G2feVa8Y-lkp@intel.com/

dtcheck warnings: (new ones prefixed by >>)
>> arch/arm64/boot/dts/adi/sc59x-64.dtsi:64.28-69.5: Warning (unit_address_vs_reg): /clocks/oscillator@1: node has a unit name, but no reg or ranges property
   arch/arm64/boot/dts/adi/sc59x-64.dtsi:71.28-76.5: Warning (unit_address_vs_reg): /clocks/oscillator@2: node has a unit name, but no reg or ranges property
>> arch/arm64/boot/dts/adi/sc59x-64.dtsi:226.30-232.5: Warning (avoid_unnecessary_addr_size): /scb-bus/pinctrl@31004600: unnecessary #address-cells/#size-cells without "ranges", "dma-ranges" or child "reg" property

vim +64 arch/arm64/boot/dts/adi/sc59x-64.dtsi

b67e4b493385a8 Arturs Artamonovs 2024-09-12   10  
b67e4b493385a8 Arturs Artamonovs 2024-09-12   11  / {
b67e4b493385a8 Arturs Artamonovs 2024-09-12   12  	model = "ADI 64-bit SC59X";
b67e4b493385a8 Arturs Artamonovs 2024-09-12   13  	compatible = "adi,sc59x-64";
b67e4b493385a8 Arturs Artamonovs 2024-09-12   14  
b67e4b493385a8 Arturs Artamonovs 2024-09-12   15  	interrupt-parent = <&gic>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   16  	#address-cells = <1>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   17  	#size-cells = <1>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   18  
b67e4b493385a8 Arturs Artamonovs 2024-09-12   19  	chosen { };
b67e4b493385a8 Arturs Artamonovs 2024-09-12   20  
b67e4b493385a8 Arturs Artamonovs 2024-09-12   21  	aliases {
b67e4b493385a8 Arturs Artamonovs 2024-09-12   22  		serial0 = &uart0;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   23  		serial2 = &uart2;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   24  		serial3 = &uart3;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   25  	};
b67e4b493385a8 Arturs Artamonovs 2024-09-12   26  
b67e4b493385a8 Arturs Artamonovs 2024-09-12   27  	cpus {
b67e4b493385a8 Arturs Artamonovs 2024-09-12   28  		#address-cells = <0x2>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   29  		#size-cells = <0x0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   30  
b67e4b493385a8 Arturs Artamonovs 2024-09-12   31  		cpu0: cpu@0 {
b67e4b493385a8 Arturs Artamonovs 2024-09-12   32  			device_type = "cpu";
b67e4b493385a8 Arturs Artamonovs 2024-09-12   33  			compatible = "arm,cortex-a55";
b67e4b493385a8 Arturs Artamonovs 2024-09-12   34  			reg = <0x0 0x0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   35  			enable-method = "spin-table";
b67e4b493385a8 Arturs Artamonovs 2024-09-12   36  			cpu-release-addr = <0x0 0xdeadbeef>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   37  			clocks = <&clk ADSP_SC598_CLK_ARM>, <&clk ADSP_SC598_CLK_DDR>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   38  		};
b67e4b493385a8 Arturs Artamonovs 2024-09-12   39  	};
b67e4b493385a8 Arturs Artamonovs 2024-09-12   40  
b67e4b493385a8 Arturs Artamonovs 2024-09-12   41  	pmu {
b67e4b493385a8 Arturs Artamonovs 2024-09-12   42  		compatible = "arm,armv8-pmuv3";
b67e4b493385a8 Arturs Artamonovs 2024-09-12   43  		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   44  		interrupt-parent = <&gic>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   45  	};
b67e4b493385a8 Arturs Artamonovs 2024-09-12   46  
b67e4b493385a8 Arturs Artamonovs 2024-09-12   47  	gic: interrupt-controller@31200000 {
b67e4b493385a8 Arturs Artamonovs 2024-09-12   48  		compatible = "arm,gic-v3";
b67e4b493385a8 Arturs Artamonovs 2024-09-12   49  		#interrupt-cells = <3>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   50  		interrupt-controller;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   51  		reg = <0x31200000 0x40000>, /* GIC Dist */
b67e4b493385a8 Arturs Artamonovs 2024-09-12   52  		      <0x31240000 0x40000>; /* GICR */
b67e4b493385a8 Arturs Artamonovs 2024-09-12   53  	};
b67e4b493385a8 Arturs Artamonovs 2024-09-12   54  
b67e4b493385a8 Arturs Artamonovs 2024-09-12   55  	timer {
b67e4b493385a8 Arturs Artamonovs 2024-09-12   56  		compatible = "arm,armv8-timer";
b67e4b493385a8 Arturs Artamonovs 2024-09-12   57  		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
b67e4b493385a8 Arturs Artamonovs 2024-09-12   58  			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
b67e4b493385a8 Arturs Artamonovs 2024-09-12   59  			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
b67e4b493385a8 Arturs Artamonovs 2024-09-12   60  			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
b67e4b493385a8 Arturs Artamonovs 2024-09-12   61  	};
b67e4b493385a8 Arturs Artamonovs 2024-09-12   62  
b67e4b493385a8 Arturs Artamonovs 2024-09-12   63  	clocks {
b67e4b493385a8 Arturs Artamonovs 2024-09-12  @64  		sys_clkin0: oscillator@1 {
b67e4b493385a8 Arturs Artamonovs 2024-09-12   65  			compatible = "fixed-clock";
b67e4b493385a8 Arturs Artamonovs 2024-09-12   66  			#clock-cells = <0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   67  			clock-frequency = <25000000>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   68  			clock-output-names = "sys_clkin0";
b67e4b493385a8 Arturs Artamonovs 2024-09-12   69  		};
b67e4b493385a8 Arturs Artamonovs 2024-09-12   70  
b67e4b493385a8 Arturs Artamonovs 2024-09-12   71  		sys_clkin1: oscillator@2 {
b67e4b493385a8 Arturs Artamonovs 2024-09-12   72  			compatible = "fixed-clock";
b67e4b493385a8 Arturs Artamonovs 2024-09-12   73  			#clock-cells = <0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   74  			clock-frequency = <25000000>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   75  			clock-output-names = "sys_clkin1";
b67e4b493385a8 Arturs Artamonovs 2024-09-12   76  		};
b67e4b493385a8 Arturs Artamonovs 2024-09-12   77  	};
b67e4b493385a8 Arturs Artamonovs 2024-09-12   78  
b67e4b493385a8 Arturs Artamonovs 2024-09-12   79  	clk: clocks@3108d000 {
b67e4b493385a8 Arturs Artamonovs 2024-09-12   80  		compatible = "adi,sc598-clocks";
b67e4b493385a8 Arturs Artamonovs 2024-09-12   81  		reg = <0x3108d000 0x1000>,
b67e4b493385a8 Arturs Artamonovs 2024-09-12   82  		      <0x3108e000 0x1000>,
b67e4b493385a8 Arturs Artamonovs 2024-09-12   83  		      <0x3108f000 0x1000>,
b67e4b493385a8 Arturs Artamonovs 2024-09-12   84  		      <0x310a9000 0x1000>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   85  		#clock-cells = <1>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   86  		clocks = <&sys_clkin0>, <&sys_clkin1>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   87  		clock-names = "sys_clkin0", "sys_clkin1";
b67e4b493385a8 Arturs Artamonovs 2024-09-12   88  		status = "okay";
b67e4b493385a8 Arturs Artamonovs 2024-09-12   89  	};
b67e4b493385a8 Arturs Artamonovs 2024-09-12   90  
b67e4b493385a8 Arturs Artamonovs 2024-09-12   91  	scb: scb-bus {
b67e4b493385a8 Arturs Artamonovs 2024-09-12   92  		compatible = "simple-bus";
b67e4b493385a8 Arturs Artamonovs 2024-09-12   93  		#address-cells = <1>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   94  		#size-cells = <1>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   95  		ranges;
b67e4b493385a8 Arturs Artamonovs 2024-09-12   96  
b67e4b493385a8 Arturs Artamonovs 2024-09-12   97  		rcu: rcu@3108c000 {
b67e4b493385a8 Arturs Artamonovs 2024-09-12   98  			compatible = "adi,reset-controller";
b67e4b493385a8 Arturs Artamonovs 2024-09-12   99  			reg = <0x3108c000 0x1000>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  100  			status = "okay";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  101  		};
b67e4b493385a8 Arturs Artamonovs 2024-09-12  102  
b67e4b493385a8 Arturs Artamonovs 2024-09-12  103  		sec: sec@31089000 {
b67e4b493385a8 Arturs Artamonovs 2024-09-12  104  			compatible = "adi,system-event-controller";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  105  			reg = <0x31089000 0x1000>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  106  			adi,rcu = <&rcu>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  107  			status = "okay";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  108  		};
b67e4b493385a8 Arturs Artamonovs 2024-09-12  109  
b67e4b493385a8 Arturs Artamonovs 2024-09-12  110  		uart0: uart@31003000 {
b67e4b493385a8 Arturs Artamonovs 2024-09-12  111  			compatible = "adi,uart";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  112  			reg = <0x31003000 0x40>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  113  			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  114  			clock-names = "sclk0";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  115  			interrupt-parent = <&gic>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  116  			interrupt-names = "tx", "rx", "status";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  117  			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
b67e4b493385a8 Arturs Artamonovs 2024-09-12  118  				     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
b67e4b493385a8 Arturs Artamonovs 2024-09-12  119  				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  120  			adi,use-edbo;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  121  			status = "disabled";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  122  		};
b67e4b493385a8 Arturs Artamonovs 2024-09-12  123  
b67e4b493385a8 Arturs Artamonovs 2024-09-12  124  		uart1: uart@31003400 {
b67e4b493385a8 Arturs Artamonovs 2024-09-12  125  			compatible = "adi,uart";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  126  			reg = <0x31003400 0x40>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  127  			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  128  			clock-names = "sclk0";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  129  			interrupt-parent = <&gic>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  130  			interrupt-names = "tx", "rx", "status";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  131  			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
b67e4b493385a8 Arturs Artamonovs 2024-09-12  132  				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
b67e4b493385a8 Arturs Artamonovs 2024-09-12  133  				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  134  			adi,use-edbo;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  135  			status = "disabled";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  136  		};
b67e4b493385a8 Arturs Artamonovs 2024-09-12  137  
b67e4b493385a8 Arturs Artamonovs 2024-09-12  138  		uart2: uart@31003800 {
b67e4b493385a8 Arturs Artamonovs 2024-09-12  139  			compatible = "adi,uart";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  140  			reg = <0x31003800 0x40>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  141  			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  142  			clock-names = "sclk0";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  143  			interrupt-parent = <&gic>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  144  			interrupt-names = "tx", "rx", "status";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  145  			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
b67e4b493385a8 Arturs Artamonovs 2024-09-12  146  				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
b67e4b493385a8 Arturs Artamonovs 2024-09-12  147  				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  148  			adi,use-edbo;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  149  			status = "disabled";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  150  		};
b67e4b493385a8 Arturs Artamonovs 2024-09-12  151  
b67e4b493385a8 Arturs Artamonovs 2024-09-12  152  		uart3: uart@31003c00 {
b67e4b493385a8 Arturs Artamonovs 2024-09-12  153  			compatible = "adi,uart";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  154  			reg = <0x31003C00 0x40>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  155  			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  156  			clock-names = "sclk0";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  157  			interrupt-parent = <&gic>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  158  			interrupt-names = "tx", "rx", "status";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  159  			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
b67e4b493385a8 Arturs Artamonovs 2024-09-12  160  				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
b67e4b493385a8 Arturs Artamonovs 2024-09-12  161  				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  162  			adi,use-edbo;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  163  			status = "disabled";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  164  		};
b67e4b493385a8 Arturs Artamonovs 2024-09-12  165  
b67e4b493385a8 Arturs Artamonovs 2024-09-12  166  		i2c0: twi@31001400 {
b67e4b493385a8 Arturs Artamonovs 2024-09-12  167  			#address-cells = <1>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  168  			#size-cells = <0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  169  			compatible = "adi,twi";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  170  			reg = <0x31001400 0xFF>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  171  			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  172  			clock-khz = <100>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  173  			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  174  			clock-names = "sclk0";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  175  			status = "disabled";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  176  		};
b67e4b493385a8 Arturs Artamonovs 2024-09-12  177  
b67e4b493385a8 Arturs Artamonovs 2024-09-12  178  		i2c1: twi@31001500 {
b67e4b493385a8 Arturs Artamonovs 2024-09-12  179  			#address-cells = <1>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  180  			#size-cells = <0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  181  			compatible = "adi,twi";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  182  			reg = <0x31001500 0xFF>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  183  			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  184  			clock-khz = <100>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  185  			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  186  			clock-names = "sclk0";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  187  			status = "disabled";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  188  		};
b67e4b493385a8 Arturs Artamonovs 2024-09-12  189  
b67e4b493385a8 Arturs Artamonovs 2024-09-12  190  		i2c3: twi@31001000 {
b67e4b493385a8 Arturs Artamonovs 2024-09-12  191  			#address-cells = <1>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  192  			#size-cells = <0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  193  			compatible = "adi,twi";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  194  			reg = <0x31001000 0xFF>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  195  			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  196  			clock-khz = <100>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  197  			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  198  			clock-names = "sclk0";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  199  			status = "disabled";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  200  		};
b67e4b493385a8 Arturs Artamonovs 2024-09-12  201  
b67e4b493385a8 Arturs Artamonovs 2024-09-12  202  		i2c4: twi@31001100 {
b67e4b493385a8 Arturs Artamonovs 2024-09-12  203  			#address-cells = <1>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  204  			#size-cells = <0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  205  			compatible = "adi,twi";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  206  			reg = <0x31001100 0xFF>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  207  			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  208  			clock-khz = <100>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  209  			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  210  			clock-names = "sclk0";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  211  			status = "disabled";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  212  		};
b67e4b493385a8 Arturs Artamonovs 2024-09-12  213  
b67e4b493385a8 Arturs Artamonovs 2024-09-12  214  		i2c5: twi@31001200 {
b67e4b493385a8 Arturs Artamonovs 2024-09-12  215  			#address-cells = <1>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  216  			#size-cells = <0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  217  			compatible = "adi,twi";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  218  			reg = <0x31001200 0xFF>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  219  			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  220  			clock-khz = <100>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  221  			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
b67e4b493385a8 Arturs Artamonovs 2024-09-12  222  			clock-names = "sclk0";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  223  			status = "disabled";
b67e4b493385a8 Arturs Artamonovs 2024-09-12  224  		};
b67e4b493385a8 Arturs Artamonovs 2024-09-12  225  
b67e4b493385a8 Arturs Artamonovs 2024-09-12 @226  		pinctrl0: pinctrl@31004600 {

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 00/21] Adding support of ADI ARMv8 ADSP-SC598 SoC.
@ 2024-09-12 18:24 Arturs Artamonovs
  2024-09-12 18:25   ` Arturs Artamonovs via B4 Relay
  0 siblings, 1 reply; 5+ messages in thread
From: Arturs Artamonovs @ 2024-09-12 18:24 UTC (permalink / raw)
  To: Catalin Marinas, Will Deacon, Greg Malysa, Philipp Zabel,
	Rob Herring, Krzysztof Kozlowski, Conor Dooley, Utsav Agarwal,
	Michael Turquette, Stephen Boyd, Linus Walleij,
	Bartosz Golaszewski, Thomas Gleixner, Andi Shyti,
	Greg Kroah-Hartman, Jiri Slaby, Arnd Bergmann, Olof Johansson,
	soc
  Cc: linux-arm-kernel, linux-kernel, devicetree, linux-clk, linux-gpio,
	linux-i2c, linux-serial, Arturs Artamonovs, adsp-linux,
	Arturs Artamonovs, Nathan Barrett-Morrison

This set of patches based on ADI fork of Linux Kerenl that support family of ADSP-SC5xx
SoC's and used by customers for some time . Patch series contains minimal set
of changes to add ADSP-SC598 support to upstream kernel. This series include
UART,I2C,IRQCHIP,RCU drivers and device-tree to be able boot on EV-SC598-SOM
board into serial shell and able to reset the board. Current SOM board
requires I2C expander to enable UART output.

UART,I2C and PINCTRL drivers are based on old Blackfin drivers with
ADSP-SC5xx related bug fixes and improvments.

Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com>
---
Arturs Artamonovs (21):
      arm64: Add ADI ADSP-SC598 SoC
      reset: Add driver for ADI ADSP-SC5xx reset controller
      dt-bindigs: arm64: adi,sc598 bindings
      dt-bindings: arm64: adi,sc598: Add ADSP-SC598 SoC bindings
      clock:Add driver for ADI ADSP-SC5xx PLL
      include: dt-binding: clock: add adi clock header file
      clock: Add driver for ADI ADSP-SC5xx clock
      dt-bindings: clock: adi,sc5xx-clocks: add bindings
      gpio: add driver for ADI ADSP-SC5xx platform
      dt-bindings: gpio: adi,adsp-port-gpio: add bindings
      irqchip: Add irqchip for ADI ADSP-SC5xx platform
      dt-bindings: irqchip: adi,adsp-pint: add binding
      pinctrl: Add drivers for ADI ADSP-SC5xx platform
      dt-bindings: pinctrl: adi,adsp-pinctrl: add bindings
      i2c: Add driver for ADI ADSP-SC5xx platforms
      dt-bindings: i2c: add i2c/twi driver documentation
      serial: adi,uart: Add driver for ADI ADSP-SC5xx
      dt-bindings: serial: adi,uart4: add adi,uart4 driver documentation
      arm64: dts: adi: sc598: add device tree
      arm64: defconfig: sc598 add minimal changes
      MAINTAINERS: add adi sc5xx maintainers

 .../devicetree/bindings/arm/analog/adi,sc5xx.yaml  |   24 +
 .../bindings/clock/adi,sc5xx-clocks.yaml           |   65 ++
 .../bindings/gpio/adi,adsp-port-gpio.yaml          |   69 ++
 Documentation/devicetree/bindings/i2c/adi,twi.yaml |   71 ++
 .../interrupt-controller/adi,adsp-pint.yaml        |   51 +
 .../bindings/pinctrl/adi,adsp-pinctrl.yaml         |   83 ++
 .../devicetree/bindings/serial/adi,uart.yaml       |   85 ++
 .../bindings/soc/adi/adi,reset-controller.yaml     |   38 +
 MAINTAINERS                                        |   22 +
 arch/arm64/Kconfig.platforms                       |   13 +
 arch/arm64/boot/dts/Makefile                       |    1 +
 arch/arm64/boot/dts/adi/Makefile                   |    2 +
 arch/arm64/boot/dts/adi/sc598-som-ezkit.dts        |   14 +
 arch/arm64/boot/dts/adi/sc598-som.dtsi             |   58 ++
 arch/arm64/boot/dts/adi/sc59x-64.dtsi              |  367 +++++++
 arch/arm64/configs/defconfig                       |    6 +
 drivers/clk/Kconfig                                |    9 +
 drivers/clk/Makefile                               |    1 +
 drivers/clk/adi/Makefile                           |    4 +
 drivers/clk/adi/clk-adi-pll.c                      |  151 +++
 drivers/clk/adi/clk-adi-sc598.c                    |  329 ++++++
 drivers/clk/adi/clk.h                              |   99 ++
 drivers/gpio/Kconfig                               |    8 +
 drivers/gpio/Makefile                              |    1 +
 drivers/gpio/gpio-adi-adsp-port.c                  |  145 +++
 drivers/i2c/busses/Kconfig                         |   17 +
 drivers/i2c/busses/Makefile                        |    1 +
 drivers/i2c/busses/i2c-adi-twi.c                   |  940 ++++++++++++++++++
 drivers/irqchip/Kconfig                            |    9 +
 drivers/irqchip/Makefile                           |    2 +
 drivers/irqchip/irq-adi-adsp.c                     |  310 ++++++
 drivers/pinctrl/Kconfig                            |   12 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-adsp.c                     |  919 +++++++++++++++++
 drivers/reset/Makefile                             |    1 +
 drivers/soc/Makefile                               |    1 +
 drivers/soc/adi/Makefile                           |    5 +
 drivers/soc/adi/system.c                           |  257 +++++
 drivers/tty/serial/Kconfig                         |   19 +-
 drivers/tty/serial/Makefile                        |    1 +
 drivers/tty/serial/adi_uart.c                      | 1045 ++++++++++++++++++++
 include/dt-bindings/clock/adi-sc5xx-clock.h        |   93 ++
 include/dt-bindings/pinctrl/adi-adsp.h             |   19 +
 include/linux/soc/adi/adsp-gpio-port.h             |   85 ++
 include/linux/soc/adi/cpu.h                        |  107 ++
 include/linux/soc/adi/rcu.h                        |   55 ++
 include/linux/soc/adi/sc59x.h                      |  147 +++
 include/linux/soc/adi/system_config.h              |   65 ++
 include/uapi/linux/serial_core.h                   |    3 +
 49 files changed, 5829 insertions(+), 1 deletion(-)
---
base-commit: da3ea35007d0af457a0afc87e84fddaebc4e0b63
change-id: 20240909-test-8ec5f76fe6d2

Best regards,
-- 
Arturs Artamonovs <arturs.artamonovs@analog.com>


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 19/21] arm64: dts: adi: sc598: add device tree
  2024-09-12 18:24 [PATCH 00/21] Adding support of ADI ARMv8 ADSP-SC598 SoC Arturs Artamonovs
@ 2024-09-12 18:25   ` Arturs Artamonovs via B4 Relay
  0 siblings, 0 replies; 5+ messages in thread
From: Arturs Artamonovs @ 2024-09-12 18:25 UTC (permalink / raw)
  To: Catalin Marinas, Will Deacon, Greg Malysa, Philipp Zabel,
	Rob Herring, Krzysztof Kozlowski, Conor Dooley, Utsav Agarwal,
	Michael Turquette, Stephen Boyd, Linus Walleij,
	Bartosz Golaszewski, Thomas Gleixner, Andi Shyti,
	Greg Kroah-Hartman, Jiri Slaby, Arnd Bergmann, Olof Johansson,
	soc
  Cc: linux-arm-kernel, linux-kernel, devicetree, linux-clk, linux-gpio,
	linux-i2c, linux-serial, Arturs Artamonovs, adsp-linux,
	Arturs Artamonovs, Nathan Barrett-Morrison

Add ADI SC598-EZKIT device tree.
Support UART console as output.

Signed-off-by: Arturs Artamonovs <Arturs.Artamonovs@analog.com>
Signed-off-by: Utsav Agarwal <Utsav.Agarwal@analog.com>
Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Co-developed-by: Greg Malysa <greg.malysa@timesys.com>
Signed-off-by: Greg Malysa <greg.malysa@timesys.com>
---
 arch/arm64/boot/dts/Makefile                |   1 +
 arch/arm64/boot/dts/adi/Makefile            |   2 +
 arch/arm64/boot/dts/adi/sc598-som-ezkit.dts |  14 ++
 arch/arm64/boot/dts/adi/sc598-som.dtsi      |  58 +++++
 arch/arm64/boot/dts/adi/sc59x-64.dtsi       | 367 ++++++++++++++++++++++++++++
 5 files changed, 442 insertions(+)

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 21cd3a87f385309c3a655a67a3bee5f0abed7545..9b3996a8e01d8e7d264c44c075d7a50ee350ba44 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 subdir-y += actions
+subdir-y += adi
 subdir-y += airoha
 subdir-y += allwinner
 subdir-y += altera
diff --git a/arch/arm64/boot/dts/adi/Makefile b/arch/arm64/boot/dts/adi/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..1bf54bc97095e1ea3577953d379746fbc0ea02a9
--- /dev/null
+++ b/arch/arm64/boot/dts/adi/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SC59X_64) += sc598-som-ezkit.dtb
diff --git a/arch/arm64/boot/dts/adi/sc598-som-ezkit.dts b/arch/arm64/boot/dts/adi/sc598-som-ezkit.dts
new file mode 100644
index 0000000000000000000000000000000000000000..a8db6d5ea764f917faa6839d3d4f0b5217b927b8
--- /dev/null
+++ b/arch/arm64/boot/dts/adi/sc598-som-ezkit.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021-2024 - Analog Devices Inc.
+ * Author: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ */
+
+/dts-v1/;
+
+#include "sc598-som.dtsi"
+
+/ {
+	model = "ADI 64-bit SC598 SOM EZ Kit";
+	compatible = "adi,sc598-som-ezkit", "adi,sc59x-64";
+};
diff --git a/arch/arm64/boot/dts/adi/sc598-som.dtsi b/arch/arm64/boot/dts/adi/sc598-som.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..3b90f367db1a24de1e1dddc4db3c219736c5b90f
--- /dev/null
+++ b/arch/arm64/boot/dts/adi/sc598-som.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021-2024 - Analog Devices Inc.
+ * Author: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/adi-adsp.h>
+#include "sc59x-64.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart1;
+		bootargs = "earlycon=adi_uart,0x31003000 console=ttySC0,115200 mem=224M";
+	};
+
+	memory@90000000 {
+		device_type = "memory";
+		reg = <0x90000000 0x0e000000>;
+	};
+
+	memory@20040000 {
+		device_type = "memory";
+		reg = <0x20040000 0x40000>;
+	};
+
+	scb: scb-bus {
+		sec: sec@31089000 {
+			adi,sharc-cores = <2>;
+		};
+	};
+
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "disabled";
+};
+
+&pinctrl0 {
+	uart0_default: uart0-default-pins {
+		pins {
+			pinmux = <ADI_ADSP_PINMUX('A', 6, ADI_ADSP_PINFUNC_ALT1)>,
+				 <ADI_ADSP_PINMUX('A', 7, ADI_ADSP_PINFUNC_ALT1)>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/adi/sc59x-64.dtsi b/arch/arm64/boot/dts/adi/sc59x-64.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..4a9aa08b4acb0936c97e683562e05da063a4e193
--- /dev/null
+++ b/arch/arm64/boot/dts/adi/sc59x-64.dtsi
@@ -0,0 +1,367 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021-2024 - Analog Devices Inc.
+ * Author: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ */
+
+#include <dt-bindings/clock/adi-sc5xx-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "ADI 64-bit SC59X";
+	compatible = "adi,sc59x-64";
+
+	interrupt-parent = <&gic>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen { };
+
+	aliases {
+		serial0 = &uart0;
+		serial2 = &uart2;
+		serial3 = &uart3;
+	};
+
+	cpus {
+		#address-cells = <0x2>;
+		#size-cells = <0x0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x0>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xdeadbeef>;
+			clocks = <&clk ADSP_SC598_CLK_ARM>, <&clk ADSP_SC598_CLK_DDR>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+	};
+
+	gic: interrupt-controller@31200000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x31200000 0x40000>, /* GIC Dist */
+		      <0x31240000 0x40000>; /* GICR */
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
+	};
+
+	clocks {
+		sys_clkin0: oscillator@1 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+			clock-output-names = "sys_clkin0";
+		};
+
+		sys_clkin1: oscillator@2 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+			clock-output-names = "sys_clkin1";
+		};
+	};
+
+	clk: clocks@3108d000 {
+		compatible = "adi,sc598-clocks";
+		reg = <0x3108d000 0x1000>,
+		      <0x3108e000 0x1000>,
+		      <0x3108f000 0x1000>,
+		      <0x310a9000 0x1000>;
+		#clock-cells = <1>;
+		clocks = <&sys_clkin0>, <&sys_clkin1>;
+		clock-names = "sys_clkin0", "sys_clkin1";
+		status = "okay";
+	};
+
+	scb: scb-bus {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		rcu: rcu@3108c000 {
+			compatible = "adi,reset-controller";
+			reg = <0x3108c000 0x1000>;
+			status = "okay";
+		};
+
+		sec: sec@31089000 {
+			compatible = "adi,system-event-controller";
+			reg = <0x31089000 0x1000>;
+			adi,rcu = <&rcu>;
+			status = "okay";
+		};
+
+		uart0: uart@31003000 {
+			compatible = "adi,uart";
+			reg = <0x31003000 0x40>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			interrupt-parent = <&gic>;
+			interrupt-names = "tx", "rx", "status";
+			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			adi,use-edbo;
+			status = "disabled";
+		};
+
+		uart1: uart@31003400 {
+			compatible = "adi,uart";
+			reg = <0x31003400 0x40>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			interrupt-parent = <&gic>;
+			interrupt-names = "tx", "rx", "status";
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			adi,use-edbo;
+			status = "disabled";
+		};
+
+		uart2: uart@31003800 {
+			compatible = "adi,uart";
+			reg = <0x31003800 0x40>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			interrupt-parent = <&gic>;
+			interrupt-names = "tx", "rx", "status";
+			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			adi,use-edbo;
+			status = "disabled";
+		};
+
+		uart3: uart@31003c00 {
+			compatible = "adi,uart";
+			reg = <0x31003C00 0x40>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			interrupt-parent = <&gic>;
+			interrupt-names = "tx", "rx", "status";
+			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			adi,use-edbo;
+			status = "disabled";
+		};
+
+		i2c0: twi@31001400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "adi,twi";
+			reg = <0x31001400 0xFF>;
+			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+			clock-khz = <100>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			status = "disabled";
+		};
+
+		i2c1: twi@31001500 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "adi,twi";
+			reg = <0x31001500 0xFF>;
+			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+			clock-khz = <100>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			status = "disabled";
+		};
+
+		i2c3: twi@31001000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "adi,twi";
+			reg = <0x31001000 0xFF>;
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			clock-khz = <100>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			status = "disabled";
+		};
+
+		i2c4: twi@31001100 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "adi,twi";
+			reg = <0x31001100 0xFF>;
+			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			clock-khz = <100>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			status = "disabled";
+		};
+
+		i2c5: twi@31001200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "adi,twi";
+			reg = <0x31001200 0xFF>;
+			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+			clock-khz = <100>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			status = "disabled";
+		};
+
+		pinctrl0: pinctrl@31004600 {
+			compatible = "adi,adsp-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x31004600 0x400>;
+			adi,port-sizes = <16 16 16 16 16 16 16 16 7>;
+		};
+
+		pint0: pint@31005000 {
+			compatible = "adi,adsp-pint";
+			reg = <0x31005000 0xFF>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pint1: pint@31005100 {
+			compatible = "adi,adsp-pint";
+			reg = <0x31005100 0xFF>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pint2: pint@31005200 {
+			compatible = "adi,adsp-pint";
+			reg = <0x31005200 0xFF>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pint3: pint@31005300 {
+			compatible = "adi,adsp-pint";
+			reg = <0x31005300 0xFF>;
+			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pint4: pint@31005400 {
+			compatible = "adi,adsp-pint";
+			reg = <0x31005400 0xFF>;
+			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pint5: pint@31005500 {
+			compatible = "adi,adsp-pint";
+			reg = <0x31005500 0xFF>;
+			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pint6: pint@31005600 {
+			compatible = "adi,adsp-pint";
+			reg = <0x31005600 0xFF>;
+			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pint7: pint@31005700 {
+			compatible = "adi,adsp-pint";
+			reg = <0x31005700 0xFF>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		gpa: gport@31004000 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004000 0x7F>;
+			gpio-ranges = <&pinctrl0 0 0 16>;
+			adi,pint = <&pint0 1>;
+			status = "okay";
+		};
+
+		gpb: gport@31004080 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004080 0x7F>;
+			gpio-ranges = <&pinctrl0 0 16 16>;
+			adi,pint = <&pint0 0>;
+			status = "okay";
+		};
+
+		gpc: gport@31004100 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004100 0x7F>;
+			gpio-ranges = <&pinctrl0 0 32 16>;
+			adi,pint = <&pint2 1>;
+			status = "okay";
+		};
+
+		gpd: gport@31004180 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004180 0x7F>;
+			gpio-ranges = <&pinctrl0 0 48 16>;
+			adi,pint = <&pint2 0>;
+		};
+
+		gpe: gport@31004200 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004200 0x7F>;
+			gpio-ranges = <&pinctrl0 0 64 16>;
+			adi,pint = <&pint4 1>;
+		};
+
+		gpf: gport@31004280 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004280 0x7F>;
+			gpio-ranges = <&pinctrl0 0 80 16>;
+			adi,pint = <&pint4 0>;
+		};
+
+		gpg: gport@31004300 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004300 0x7F>;
+			gpio-ranges = <&pinctrl0 0 96 16>;
+			adi,pint = <&pint6 1>;
+		};
+
+		gph: gport@31004380 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004380 0x7F>;
+			gpio-ranges = <&pinctrl0 0 112 16>;
+			adi,pint = <&pint6 0>;
+		};
+
+		gpi: gport@31004400 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004400 0x7F>;
+			gpio-ranges = <&pinctrl0 0 128 7>;
+			adi,pint = <&pint7 1>;
+		};
+
+	};
+};

-- 
2.25.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH 19/21] arm64: dts: adi: sc598: add device tree
@ 2024-09-12 18:25   ` Arturs Artamonovs via B4 Relay
  0 siblings, 0 replies; 5+ messages in thread
From: Arturs Artamonovs via B4 Relay @ 2024-09-12 18:25 UTC (permalink / raw)
  To: Catalin Marinas, Will Deacon, Greg Malysa, Philipp Zabel,
	Rob Herring, Krzysztof Kozlowski, Conor Dooley, Utsav Agarwal,
	Michael Turquette, Stephen Boyd, Linus Walleij,
	Bartosz Golaszewski, Thomas Gleixner, Andi Shyti,
	Greg Kroah-Hartman, Jiri Slaby, Arnd Bergmann, Olof Johansson,
	soc
  Cc: linux-arm-kernel, linux-kernel, devicetree, linux-clk, linux-gpio,
	linux-i2c, linux-serial, Arturs Artamonovs, adsp-linux,
	Arturs Artamonovs, Nathan Barrett-Morrison

From: Arturs Artamonovs <arturs.artamonovs@analog.com>

Add ADI SC598-EZKIT device tree.
Support UART console as output.

Signed-off-by: Arturs Artamonovs <Arturs.Artamonovs@analog.com>
Signed-off-by: Utsav Agarwal <Utsav.Agarwal@analog.com>
Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Co-developed-by: Greg Malysa <greg.malysa@timesys.com>
Signed-off-by: Greg Malysa <greg.malysa@timesys.com>
---
 arch/arm64/boot/dts/Makefile                |   1 +
 arch/arm64/boot/dts/adi/Makefile            |   2 +
 arch/arm64/boot/dts/adi/sc598-som-ezkit.dts |  14 ++
 arch/arm64/boot/dts/adi/sc598-som.dtsi      |  58 +++++
 arch/arm64/boot/dts/adi/sc59x-64.dtsi       | 367 ++++++++++++++++++++++++++++
 5 files changed, 442 insertions(+)

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 21cd3a87f385309c3a655a67a3bee5f0abed7545..9b3996a8e01d8e7d264c44c075d7a50ee350ba44 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 subdir-y += actions
+subdir-y += adi
 subdir-y += airoha
 subdir-y += allwinner
 subdir-y += altera
diff --git a/arch/arm64/boot/dts/adi/Makefile b/arch/arm64/boot/dts/adi/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..1bf54bc97095e1ea3577953d379746fbc0ea02a9
--- /dev/null
+++ b/arch/arm64/boot/dts/adi/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SC59X_64) += sc598-som-ezkit.dtb
diff --git a/arch/arm64/boot/dts/adi/sc598-som-ezkit.dts b/arch/arm64/boot/dts/adi/sc598-som-ezkit.dts
new file mode 100644
index 0000000000000000000000000000000000000000..a8db6d5ea764f917faa6839d3d4f0b5217b927b8
--- /dev/null
+++ b/arch/arm64/boot/dts/adi/sc598-som-ezkit.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021-2024 - Analog Devices Inc.
+ * Author: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ */
+
+/dts-v1/;
+
+#include "sc598-som.dtsi"
+
+/ {
+	model = "ADI 64-bit SC598 SOM EZ Kit";
+	compatible = "adi,sc598-som-ezkit", "adi,sc59x-64";
+};
diff --git a/arch/arm64/boot/dts/adi/sc598-som.dtsi b/arch/arm64/boot/dts/adi/sc598-som.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..3b90f367db1a24de1e1dddc4db3c219736c5b90f
--- /dev/null
+++ b/arch/arm64/boot/dts/adi/sc598-som.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021-2024 - Analog Devices Inc.
+ * Author: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/adi-adsp.h>
+#include "sc59x-64.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart1;
+		bootargs = "earlycon=adi_uart,0x31003000 console=ttySC0,115200 mem=224M";
+	};
+
+	memory@90000000 {
+		device_type = "memory";
+		reg = <0x90000000 0x0e000000>;
+	};
+
+	memory@20040000 {
+		device_type = "memory";
+		reg = <0x20040000 0x40000>;
+	};
+
+	scb: scb-bus {
+		sec: sec@31089000 {
+			adi,sharc-cores = <2>;
+		};
+	};
+
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "disabled";
+};
+
+&pinctrl0 {
+	uart0_default: uart0-default-pins {
+		pins {
+			pinmux = <ADI_ADSP_PINMUX('A', 6, ADI_ADSP_PINFUNC_ALT1)>,
+				 <ADI_ADSP_PINMUX('A', 7, ADI_ADSP_PINFUNC_ALT1)>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/adi/sc59x-64.dtsi b/arch/arm64/boot/dts/adi/sc59x-64.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..4a9aa08b4acb0936c97e683562e05da063a4e193
--- /dev/null
+++ b/arch/arm64/boot/dts/adi/sc59x-64.dtsi
@@ -0,0 +1,367 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021-2024 - Analog Devices Inc.
+ * Author: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ */
+
+#include <dt-bindings/clock/adi-sc5xx-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "ADI 64-bit SC59X";
+	compatible = "adi,sc59x-64";
+
+	interrupt-parent = <&gic>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen { };
+
+	aliases {
+		serial0 = &uart0;
+		serial2 = &uart2;
+		serial3 = &uart3;
+	};
+
+	cpus {
+		#address-cells = <0x2>;
+		#size-cells = <0x0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x0>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xdeadbeef>;
+			clocks = <&clk ADSP_SC598_CLK_ARM>, <&clk ADSP_SC598_CLK_DDR>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+	};
+
+	gic: interrupt-controller@31200000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x31200000 0x40000>, /* GIC Dist */
+		      <0x31240000 0x40000>; /* GICR */
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
+	};
+
+	clocks {
+		sys_clkin0: oscillator@1 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+			clock-output-names = "sys_clkin0";
+		};
+
+		sys_clkin1: oscillator@2 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+			clock-output-names = "sys_clkin1";
+		};
+	};
+
+	clk: clocks@3108d000 {
+		compatible = "adi,sc598-clocks";
+		reg = <0x3108d000 0x1000>,
+		      <0x3108e000 0x1000>,
+		      <0x3108f000 0x1000>,
+		      <0x310a9000 0x1000>;
+		#clock-cells = <1>;
+		clocks = <&sys_clkin0>, <&sys_clkin1>;
+		clock-names = "sys_clkin0", "sys_clkin1";
+		status = "okay";
+	};
+
+	scb: scb-bus {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		rcu: rcu@3108c000 {
+			compatible = "adi,reset-controller";
+			reg = <0x3108c000 0x1000>;
+			status = "okay";
+		};
+
+		sec: sec@31089000 {
+			compatible = "adi,system-event-controller";
+			reg = <0x31089000 0x1000>;
+			adi,rcu = <&rcu>;
+			status = "okay";
+		};
+
+		uart0: uart@31003000 {
+			compatible = "adi,uart";
+			reg = <0x31003000 0x40>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			interrupt-parent = <&gic>;
+			interrupt-names = "tx", "rx", "status";
+			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			adi,use-edbo;
+			status = "disabled";
+		};
+
+		uart1: uart@31003400 {
+			compatible = "adi,uart";
+			reg = <0x31003400 0x40>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			interrupt-parent = <&gic>;
+			interrupt-names = "tx", "rx", "status";
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			adi,use-edbo;
+			status = "disabled";
+		};
+
+		uart2: uart@31003800 {
+			compatible = "adi,uart";
+			reg = <0x31003800 0x40>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			interrupt-parent = <&gic>;
+			interrupt-names = "tx", "rx", "status";
+			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			adi,use-edbo;
+			status = "disabled";
+		};
+
+		uart3: uart@31003c00 {
+			compatible = "adi,uart";
+			reg = <0x31003C00 0x40>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			interrupt-parent = <&gic>;
+			interrupt-names = "tx", "rx", "status";
+			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			adi,use-edbo;
+			status = "disabled";
+		};
+
+		i2c0: twi@31001400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "adi,twi";
+			reg = <0x31001400 0xFF>;
+			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+			clock-khz = <100>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			status = "disabled";
+		};
+
+		i2c1: twi@31001500 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "adi,twi";
+			reg = <0x31001500 0xFF>;
+			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+			clock-khz = <100>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			status = "disabled";
+		};
+
+		i2c3: twi@31001000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "adi,twi";
+			reg = <0x31001000 0xFF>;
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			clock-khz = <100>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			status = "disabled";
+		};
+
+		i2c4: twi@31001100 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "adi,twi";
+			reg = <0x31001100 0xFF>;
+			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			clock-khz = <100>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			status = "disabled";
+		};
+
+		i2c5: twi@31001200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "adi,twi";
+			reg = <0x31001200 0xFF>;
+			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+			clock-khz = <100>;
+			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
+			clock-names = "sclk0";
+			status = "disabled";
+		};
+
+		pinctrl0: pinctrl@31004600 {
+			compatible = "adi,adsp-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x31004600 0x400>;
+			adi,port-sizes = <16 16 16 16 16 16 16 16 7>;
+		};
+
+		pint0: pint@31005000 {
+			compatible = "adi,adsp-pint";
+			reg = <0x31005000 0xFF>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pint1: pint@31005100 {
+			compatible = "adi,adsp-pint";
+			reg = <0x31005100 0xFF>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pint2: pint@31005200 {
+			compatible = "adi,adsp-pint";
+			reg = <0x31005200 0xFF>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pint3: pint@31005300 {
+			compatible = "adi,adsp-pint";
+			reg = <0x31005300 0xFF>;
+			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pint4: pint@31005400 {
+			compatible = "adi,adsp-pint";
+			reg = <0x31005400 0xFF>;
+			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pint5: pint@31005500 {
+			compatible = "adi,adsp-pint";
+			reg = <0x31005500 0xFF>;
+			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pint6: pint@31005600 {
+			compatible = "adi,adsp-pint";
+			reg = <0x31005600 0xFF>;
+			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pint7: pint@31005700 {
+			compatible = "adi,adsp-pint";
+			reg = <0x31005700 0xFF>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		gpa: gport@31004000 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004000 0x7F>;
+			gpio-ranges = <&pinctrl0 0 0 16>;
+			adi,pint = <&pint0 1>;
+			status = "okay";
+		};
+
+		gpb: gport@31004080 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004080 0x7F>;
+			gpio-ranges = <&pinctrl0 0 16 16>;
+			adi,pint = <&pint0 0>;
+			status = "okay";
+		};
+
+		gpc: gport@31004100 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004100 0x7F>;
+			gpio-ranges = <&pinctrl0 0 32 16>;
+			adi,pint = <&pint2 1>;
+			status = "okay";
+		};
+
+		gpd: gport@31004180 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004180 0x7F>;
+			gpio-ranges = <&pinctrl0 0 48 16>;
+			adi,pint = <&pint2 0>;
+		};
+
+		gpe: gport@31004200 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004200 0x7F>;
+			gpio-ranges = <&pinctrl0 0 64 16>;
+			adi,pint = <&pint4 1>;
+		};
+
+		gpf: gport@31004280 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004280 0x7F>;
+			gpio-ranges = <&pinctrl0 0 80 16>;
+			adi,pint = <&pint4 0>;
+		};
+
+		gpg: gport@31004300 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004300 0x7F>;
+			gpio-ranges = <&pinctrl0 0 96 16>;
+			adi,pint = <&pint6 1>;
+		};
+
+		gph: gport@31004380 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004380 0x7F>;
+			gpio-ranges = <&pinctrl0 0 112 16>;
+			adi,pint = <&pint6 0>;
+		};
+
+		gpi: gport@31004400 {
+			compatible = "adi,adsp-port-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x31004400 0x7F>;
+			gpio-ranges = <&pinctrl0 0 128 7>;
+			adi,pint = <&pint7 1>;
+		};
+
+	};
+};

-- 
2.25.1



^ permalink raw reply related	[flat|nested] 5+ messages in thread

* Re: [PATCH 19/21] arm64: dts: adi: sc598: add device tree
  2024-09-12 18:25   ` Arturs Artamonovs via B4 Relay
  (?)
@ 2024-09-13  8:05   ` Arnd Bergmann
  -1 siblings, 0 replies; 5+ messages in thread
From: Arnd Bergmann @ 2024-09-13  8:05 UTC (permalink / raw)
  To: arturs.artamonovs, Catalin Marinas, Will Deacon, Greg Malysa,
	Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Utsav Agarwal, Michael Turquette, Stephen Boyd, Linus Walleij,
	Bartosz Golaszewski, Thomas Gleixner, Andi Shyti,
	Greg Kroah-Hartman, Jiri Slaby, Olof Johansson, soc
  Cc: linux-arm-kernel, linux-kernel, devicetree, linux-clk,
	open list:GPIO SUBSYSTEM, linux-i2c, linux-serial, adsp-linux,
	Nathan Barrett-Morrison

On Thu, Sep 12, 2024, at 18:25, Arturs Artamonovs via B4 Relay wrote:
> +/ {
> +	chosen {
> +		stdout-path = &uart1;
> +		bootargs = "earlycon=adi_uart,0x31003000 console=ttySC0,115200 
> mem=224M";
> +	};

You should not need the mem= and earlycon= arguments, as that data
is already part of the stdout-path property and the memory node.

> +	aliases {
> +		serial0 = &uart0;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +	};

The aliases are board specific, please only list the ones
that are actually enabled and wired on on a particular
board, and make the aliases match the labels on the board
rather than the internal components of hte chip.

> +	cpus {
> +		#address-cells = <0x2>;
> +		#size-cells = <0x0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a55";
> +			reg = <0x0 0x0>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0xdeadbeef>;

Is that the actual address? It looks like some placeholder
that should not have been here.

       Arnd

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH 19/21] arm64: dts: adi: sc598: add device tree
  2024-09-12 18:25   ` Arturs Artamonovs via B4 Relay
  (?)
  (?)
@ 2024-09-16  7:04   ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 5+ messages in thread
From: Krzysztof Kozlowski @ 2024-09-16  7:04 UTC (permalink / raw)
  To: arturs.artamonovs, Catalin Marinas, Will Deacon, Greg Malysa,
	Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Utsav Agarwal, Michael Turquette, Stephen Boyd, Linus Walleij,
	Bartosz Golaszewski, Thomas Gleixner, Andi Shyti,
	Greg Kroah-Hartman, Jiri Slaby, Arnd Bergmann, Olof Johansson,
	soc
  Cc: linux-arm-kernel, linux-kernel, devicetree, linux-clk, linux-gpio,
	linux-i2c, linux-serial, adsp-linux, Nathan Barrett-Morrison

On 12/09/2024 20:25, Arturs Artamonovs via B4 Relay wrote:
> From: Arturs Artamonovs <arturs.artamonovs@analog.com>
> 
> Add ADI SC598-EZKIT device tree.
> Support UART console as output.
> 
> Signed-off-by: Arturs Artamonovs <Arturs.Artamonovs@analog.com>
> Signed-off-by: Utsav Agarwal <Utsav.Agarwal@analog.com>
> Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
> Co-developed-by: Greg Malysa <greg.malysa@timesys.com>
> Signed-off-by: Greg Malysa <greg.malysa@timesys.com>
> ---
>  arch/arm64/boot/dts/Makefile                |   1 +
>  arch/arm64/boot/dts/adi/Makefile            |   2 +
>  arch/arm64/boot/dts/adi/sc598-som-ezkit.dts |  14 ++
>  arch/arm64/boot/dts/adi/sc598-som.dtsi      |  58 +++++
>  arch/arm64/boot/dts/adi/sc59x-64.dtsi       | 367 ++++++++++++++++++++++++++++
>  5 files changed, 442 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 21cd3a87f385309c3a655a67a3bee5f0abed7545..9b3996a8e01d8e7d264c44c075d7a50ee350ba44 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -1,5 +1,6 @@
>  # SPDX-License-Identifier: GPL-2.0
>  subdir-y += actions
> +subdir-y += adi
>  subdir-y += airoha
>  subdir-y += allwinner
>  subdir-y += altera
> diff --git a/arch/arm64/boot/dts/adi/Makefile b/arch/arm64/boot/dts/adi/Makefile
> new file mode 100644
> index 0000000000000000000000000000000000000000..1bf54bc97095e1ea3577953d379746fbc0ea02a9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/adi/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_SC59X_64) += sc598-som-ezkit.dtb
> diff --git a/arch/arm64/boot/dts/adi/sc598-som-ezkit.dts b/arch/arm64/boot/dts/adi/sc598-som-ezkit.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..a8db6d5ea764f917faa6839d3d4f0b5217b927b8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/adi/sc598-som-ezkit.dts
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2021-2024 - Analog Devices Inc.
> + * Author: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "sc598-som.dtsi"
> +
> +/ {
> +	model = "ADI 64-bit SC598 SOM EZ Kit";
> +	compatible = "adi,sc598-som-ezkit", "adi,sc59x-64";

Where is adi,sc598-som-ezlite?

> +};
> diff --git a/arch/arm64/boot/dts/adi/sc598-som.dtsi b/arch/arm64/boot/dts/adi/sc598-som.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..3b90f367db1a24de1e1dddc4db3c219736c5b90f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/adi/sc598-som.dtsi
> @@ -0,0 +1,58 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2021-2024 - Analog Devices Inc.
> + * Author: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/pinctrl/adi-adsp.h>
> +#include "sc59x-64.dtsi"
> +
> +/ {
> +	chosen {
> +		stdout-path = &uart1;
> +		bootargs = "earlycon=adi_uart,0x31003000 console=ttySC0,115200 mem=224M";

Drop entire bootargs. Look how other SoCs do it, if you need port speed.

> +	};
> +
> +	memory@90000000 {
> +		device_type = "memory";
> +		reg = <0x90000000 0x0e000000>;
> +	};
> +
> +	memory@20040000 {
> +		device_type = "memory";
> +		reg = <0x20040000 0x40000>;
> +	};
> +
> +	scb: scb-bus {

What is this?

> +		sec: sec@31089000 {

And this?

> +			adi,sharc-cores = <2>;
> +		};
> +	};

Drop entire node.

> +

Fix redundant blank lines.
> +};
> +
> +&uart0 {
> +	pinctrl-0 = <&uart0_default>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&i2c0 {
> +	status = "okay";
> +};
> +
> +&i2c1 {
> +	status = "disabled";
> +};
> +
> +&pinctrl0 {
> +	uart0_default: uart0-default-pins {
> +		pins {
> +			pinmux = <ADI_ADSP_PINMUX('A', 6, ADI_ADSP_PINFUNC_ALT1)>,
> +				 <ADI_ADSP_PINMUX('A', 7, ADI_ADSP_PINFUNC_ALT1)>;
> +		};
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/adi/sc59x-64.dtsi b/arch/arm64/boot/dts/adi/sc59x-64.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..4a9aa08b4acb0936c97e683562e05da063a4e193
> --- /dev/null
> +++ b/arch/arm64/boot/dts/adi/sc59x-64.dtsi
> @@ -0,0 +1,367 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2021-2024 - Analog Devices Inc.
> + * Author: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
> + */
> +
> +#include <dt-bindings/clock/adi-sc5xx-clock.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	model = "ADI 64-bit SC59X";
> +	compatible = "adi,sc59x-64";
> +
> +	interrupt-parent = <&gic>;
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	chosen { };

Drop

> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +	};


Drop or move to board DTS. Not a property of the SoC.


> +
> +	cpus {
> +		#address-cells = <0x2>;
> +		#size-cells = <0x0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a55";
> +			reg = <0x0 0x0>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0xdeadbeef>;
> +			clocks = <&clk ADSP_SC598_CLK_ARM>, <&clk ADSP_SC598_CLK_DDR>;
> +		};
> +	};
> +
> +	pmu {

Order nodes alphabetically. See DTS coding style.

> +		compatible = "arm,armv8-pmuv3";
> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-parent = <&gic>;
> +	};
> +
> +	gic: interrupt-controller@31200000 {


This cannot be outside of SoC. See writing-bindings and DTS coding style.

> +		compatible = "arm,gic-v3";
> +		#interrupt-cells = <3>;
> +		interrupt-controller;
> +		reg = <0x31200000 0x40000>, /* GIC Dist */
> +		      <0x31240000 0x40000>; /* GICR */
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
> +	};
> +
> +	clocks {
> +		sys_clkin0: oscillator@1 {

There is no way you tested it. It's obvious W=1 warning.

> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <25000000>;
> +			clock-output-names = "sys_clkin0";
> +		};
> +
> +		sys_clkin1: oscillator@2 {

How are these properties of the SoC? Where are they located physically?
See DTS coding style.

> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <25000000>;
> +			clock-output-names = "sys_clkin1";
> +		};
> +	};
> +
> +	clk: clocks@3108d000 {
> +		compatible = "adi,sc598-clocks";
> +		reg = <0x3108d000 0x1000>,
> +		      <0x3108e000 0x1000>,
> +		      <0x3108f000 0x1000>,
> +		      <0x310a9000 0x1000>;
> +		#clock-cells = <1>;
> +		clocks = <&sys_clkin0>, <&sys_clkin1>;
> +		clock-names = "sys_clkin0", "sys_clkin1";
> +		status = "okay";

Drop... everywhere.

> +	};
> +
> +	scb: scb-bus {

What is scb-bus?

See DTS coding style or any other SoC. This is supposed to be just sco@
with proper unit address.

> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		rcu: rcu@3108c000 {
> +			compatible = "adi,reset-controller";
> +			reg = <0x3108c000 0x1000>;
> +			status = "okay";

Oh...

> +		};
> +
> +		sec: sec@31089000 {

Random order of nodes? See DTS coding style.

> +			compatible = "adi,system-event-controller";
> +			reg = <0x31089000 0x1000>;
> +			adi,rcu = <&rcu>;
> +			status = "okay";
> +		};
> +
> +		uart0: uart@31003000 {

Never tested.

It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
> +			compatible = "adi,uart";
> +			reg = <0x31003000 0x40>;
> +			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
> +			clock-names = "sclk0";
> +			interrupt-parent = <&gic>;
> +			interrupt-names = "tx", "rx", "status";
> +			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> +			adi,use-edbo;
> +			status = "disabled";
> +		};
> +
> +		uart1: uart@31003400 {
> +			compatible = "adi,uart";
> +			reg = <0x31003400 0x40>;
> +			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
> +			clock-names = "sclk0";
> +			interrupt-parent = <&gic>;
> +			interrupt-names = "tx", "rx", "status";
> +			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> +			adi,use-edbo;
> +			status = "disabled";
> +		};
> +
> +		uart2: uart@31003800 {
> +			compatible = "adi,uart";
> +			reg = <0x31003800 0x40>;
> +			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
> +			clock-names = "sclk0";
> +			interrupt-parent = <&gic>;
> +			interrupt-names = "tx", "rx", "status";
> +			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> +			adi,use-edbo;
> +			status = "disabled";
> +		};
> +
> +		uart3: uart@31003c00 {
> +			compatible = "adi,uart";
> +			reg = <0x31003C00 0x40>;
> +			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
> +			clock-names = "sclk0";
> +			interrupt-parent = <&gic>;
> +			interrupt-names = "tx", "rx", "status";
> +			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> +			adi,use-edbo;
> +			status = "disabled";
> +		};
> +
> +		i2c0: twi@31001400 {

Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation


Completely wrong order of properties. Please follow DTS coding style.


> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "adi,twi";

You cannot have generic compatibles in the SoC.

> +			reg = <0x31001400 0xFF>;

I already commented on lower case hex.

> +			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-khz = <100>;
> +			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
> +			clock-names = "sclk0";
> +			status = "disabled";
> +		};
> +
> +		i2c1: twi@31001500 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "adi,twi";
> +			reg = <0x31001500 0xFF>;
> +			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-khz = <100>;
> +			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
> +			clock-names = "sclk0";
> +			status = "disabled";
> +		};
> +
> +		i2c3: twi@31001000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "adi,twi";
> +			reg = <0x31001000 0xFF>;
> +			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-khz = <100>;
> +			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
> +			clock-names = "sclk0";
> +			status = "disabled";
> +		};
> +
> +		i2c4: twi@31001100 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "adi,twi";
> +			reg = <0x31001100 0xFF>;
> +			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-khz = <100>;
> +			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
> +			clock-names = "sclk0";
> +			status = "disabled";
> +		};
> +
> +		i2c5: twi@31001200 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "adi,twi";
> +			reg = <0x31001200 0xFF>;
> +			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-khz = <100>;
> +			clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>;
> +			clock-names = "sclk0";
> +			status = "disabled";
> +		};
> +
> +		pinctrl0: pinctrl@31004600 {
> +			compatible = "adi,adsp-pinctrl";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x31004600 0x400>;
> +			adi,port-sizes = <16 16 16 16 16 16 16 16 7>;
> +		};
> +
> +		pint0: pint@31005000 {
> +			compatible = "adi,adsp-pint";
> +			reg = <0x31005000 0xFF>;
> +			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		pint1: pint@31005100 {
> +			compatible = "adi,adsp-pint";
> +			reg = <0x31005100 0xFF>;
> +			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		pint2: pint@31005200 {

Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation


> +			compatible = "adi,adsp-pint";
> +			reg = <0x31005200 0xFF>;
> +			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		pint3: pint@31005300 {
> +			compatible = "adi,adsp-pint";
> +			reg = <0x31005300 0xFF>;
> +			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		pint4: pint@31005400 {
> +			compatible = "adi,adsp-pint";
> +			reg = <0x31005400 0xFF>;
> +			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		pint5: pint@31005500 {
> +			compatible = "adi,adsp-pint";
> +			reg = <0x31005500 0xFF>;
> +			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		pint6: pint@31005600 {
> +			compatible = "adi,adsp-pint";
> +			reg = <0x31005600 0xFF>;
> +			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		pint7: pint@31005700 {
> +			compatible = "adi,adsp-pint";
> +			reg = <0x31005700 0xFF>;
> +			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		gpa: gport@31004000 {

Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation


> +			compatible = "adi,adsp-port-gpio";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			reg = <0x31004000 0x7F>;
> +			gpio-ranges = <&pinctrl0 0 0 16>;
> +			adi,pint = <&pint0 1>;
> +			status = "okay";
> +		};
> +
> +		gpb: gport@31004080 {
> +			compatible = "adi,adsp-port-gpio";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			reg = <0x31004080 0x7F>;
> +			gpio-ranges = <&pinctrl0 0 16 16>;
> +			adi,pint = <&pint0 0>;
> +			status = "okay";
> +		};
> +
> +		gpc: gport@31004100 {
> +			compatible = "adi,adsp-port-gpio";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			reg = <0x31004100 0x7F>;
> +			gpio-ranges = <&pinctrl0 0 32 16>;
> +			adi,pint = <&pint2 1>;
> +			status = "okay";
> +		};
> +
> +		gpd: gport@31004180 {
> +			compatible = "adi,adsp-port-gpio";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			reg = <0x31004180 0x7F>;
> +			gpio-ranges = <&pinctrl0 0 48 16>;
> +			adi,pint = <&pint2 0>;
> +		};
> +
> +		gpe: gport@31004200 {
> +			compatible = "adi,adsp-port-gpio";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			reg = <0x31004200 0x7F>;
> +			gpio-ranges = <&pinctrl0 0 64 16>;
> +			adi,pint = <&pint4 1>;
> +		};
> +
> +		gpf: gport@31004280 {
> +			compatible = "adi,adsp-port-gpio";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			reg = <0x31004280 0x7F>;
> +			gpio-ranges = <&pinctrl0 0 80 16>;
> +			adi,pint = <&pint4 0>;
> +		};
> +
> +		gpg: gport@31004300 {
> +			compatible = "adi,adsp-port-gpio";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			reg = <0x31004300 0x7F>;
> +			gpio-ranges = <&pinctrl0 0 96 16>;
> +			adi,pint = <&pint6 1>;
> +		};
> +
> +		gph: gport@31004380 {
> +			compatible = "adi,adsp-port-gpio";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			reg = <0x31004380 0x7F>;
> +			gpio-ranges = <&pinctrl0 0 112 16>;
> +			adi,pint = <&pint6 0>;
> +		};
> +
> +		gpi: gport@31004400 {
> +			compatible = "adi,adsp-port-gpio";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			reg = <0x31004400 0x7F>;
> +			gpio-ranges = <&pinctrl0 0 128 7>;
> +			adi,pint = <&pint7 1>;
> +		};
> +

All your patches have such sloppy blank lines here and there.

> +	};
> +};
> 

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2024-09-16  7:05 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-09-14 14:51 [PATCH 19/21] arm64: dts: adi: sc598: add device tree kernel test robot
  -- strict thread matches above, loose matches on Subject: below --
2024-09-12 18:24 [PATCH 00/21] Adding support of ADI ARMv8 ADSP-SC598 SoC Arturs Artamonovs
2024-09-12 18:25 ` [PATCH 19/21] arm64: dts: adi: sc598: add device tree Arturs Artamonovs
2024-09-12 18:25   ` Arturs Artamonovs via B4 Relay
2024-09-13  8:05   ` Arnd Bergmann
2024-09-16  7:04   ` Krzysztof Kozlowski

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