From: Conor Dooley <conor@kernel.org>
To: Manikandan.M@microchip.com
Cc: alexandre.belloni@bootlin.com, geert+renesas@glider.be,
dri-devel@lists.freedesktop.org, claudiu.beznea@tuxon.dev,
Laurent.pinchart@ideasonboard.com, andrzej.hajda@intel.com,
airlied@gmail.com, robh@kernel.org, rfoss@kernel.org,
mpe@ellerman.id.au, linux@armlinux.org.uk,
jernej.skrabec@gmail.com, Dharma.B@microchip.com,
devicetree@vger.kernel.org, conor+dt@kernel.org,
tzimmermann@suse.de, arnd@arndb.de, jonas@kwiboo.se,
maarten.lankhorst@linux.intel.com, mripard@kernel.org,
linux-arm-kernel@lists.infradead.org, neil.armstrong@linaro.org,
rdunlap@infradead.org, linux-kernel@vger.kernel.org,
daniel@ffwll.ch, krzk+dt@kernel.org
Subject: Re: [PATCH v3 1/4] dt-bindings: display: bridge: add sam9x75-mipi-dsi binding
Date: Wed, 18 Sep 2024 09:04:50 +0100 [thread overview]
Message-ID: <20240918-concert-liability-fab83f411cfa@squawk> (raw)
In-Reply-To: <d343d34e-f810-4375-882e-d74f104ce215@microchip.com>
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On Wed, Sep 18, 2024 at 03:00:45AM +0000, Manikandan.M@microchip.com wrote:
> On 17/09/24 6:08 pm, Conor Dooley wrote:
> > On Tue, Sep 17, 2024 at 03:16:53AM +0000,Manikandan.M@microchip.com wrote:
> >> Hi Conor,
> >>
> >> On 14/08/24 7:29 pm, Conor Dooley wrote:
> >>> On Wed, Aug 14, 2024 at 04:22:53PM +0530, Manikandan Muralidharan wrote:
> >>>> + microchip,sfr:
> >>>> + $ref: /schemas/types.yaml#/definitions/phandle
> >>>> + description:
> >>>> + phandle to Special Function Register (SFR) node.To enable the DSI/CSI
> >>>> + selection bit in SFR's ISS Configuration Register.
> >>> I'm curious - why is this phandle required? How many SFR nodes are there
> >>> on the platform?
> >> This phandle is to map the memory region of SFR node and configure the
> >> DSI bit in the SFR's ISS configuration register.
> >> currently there is only one SFR node in this platform.
> > What does "currently" mean? The platform either has one or it does not,
> > currently makes it sound like it has more than one but the dts only has
> > one.
> Apologies, I would like to clarify the statement that this platform only
> has one 32-bit special function register implemented.
In that case, you dont need a phandle at all, just look the sfr up by
its compatible.
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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Manikandan.M@microchip.com
Cc: andrzej.hajda@intel.com, neil.armstrong@linaro.org,
rfoss@kernel.org, Laurent.pinchart@ideasonboard.com,
jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com,
daniel@ffwll.ch, maarten.lankhorst@linux.intel.com,
mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, linux@armlinux.org.uk,
Nicolas.Ferre@microchip.com, alexandre.belloni@bootlin.com,
claudiu.beznea@tuxon.dev, arnd@arndb.de, geert+renesas@glider.be,
mpe@ellerman.id.au, rdunlap@infradead.org,
Dharma.B@microchip.com, dri-devel@lists.freedesktop.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 1/4] dt-bindings: display: bridge: add sam9x75-mipi-dsi binding
Date: Wed, 18 Sep 2024 09:04:50 +0100 [thread overview]
Message-ID: <20240918-concert-liability-fab83f411cfa@squawk> (raw)
In-Reply-To: <d343d34e-f810-4375-882e-d74f104ce215@microchip.com>
[-- Attachment #1: Type: text/plain, Size: 1301 bytes --]
On Wed, Sep 18, 2024 at 03:00:45AM +0000, Manikandan.M@microchip.com wrote:
> On 17/09/24 6:08 pm, Conor Dooley wrote:
> > On Tue, Sep 17, 2024 at 03:16:53AM +0000,Manikandan.M@microchip.com wrote:
> >> Hi Conor,
> >>
> >> On 14/08/24 7:29 pm, Conor Dooley wrote:
> >>> On Wed, Aug 14, 2024 at 04:22:53PM +0530, Manikandan Muralidharan wrote:
> >>>> + microchip,sfr:
> >>>> + $ref: /schemas/types.yaml#/definitions/phandle
> >>>> + description:
> >>>> + phandle to Special Function Register (SFR) node.To enable the DSI/CSI
> >>>> + selection bit in SFR's ISS Configuration Register.
> >>> I'm curious - why is this phandle required? How many SFR nodes are there
> >>> on the platform?
> >> This phandle is to map the memory region of SFR node and configure the
> >> DSI bit in the SFR's ISS configuration register.
> >> currently there is only one SFR node in this platform.
> > What does "currently" mean? The platform either has one or it does not,
> > currently makes it sound like it has more than one but the dts only has
> > one.
> Apologies, I would like to clarify the statement that this platform only
> has one 32-bit special function register implemented.
In that case, you dont need a phandle at all, just look the sfr up by
its compatible.
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next prev parent reply other threads:[~2024-09-18 8:07 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-14 10:52 [PATCH v3 0/4] MIPI DSI Controller support for SAM9X75 series Manikandan Muralidharan
2024-08-14 10:52 ` [PATCH v3 1/4] dt-bindings: display: bridge: add sam9x75-mipi-dsi binding Manikandan Muralidharan
2024-08-14 13:59 ` Conor Dooley
2024-08-14 13:59 ` Conor Dooley
2024-09-17 3:16 ` Manikandan.M
2024-09-17 12:38 ` Conor Dooley
2024-09-17 12:38 ` Conor Dooley
2024-09-18 3:00 ` Manikandan.M
2024-09-18 8:04 ` Conor Dooley [this message]
2024-09-18 8:04 ` Conor Dooley
2024-08-14 10:52 ` [PATCH v3 2/4] drm/bridge: add Microchip DSI controller support for sam9x7 SoC series Manikandan Muralidharan
2024-08-16 13:35 ` kernel test robot
2024-08-14 10:52 ` [PATCH v3 3/4] MAINTAINERS: add SAM9X7 SoC's Microchip's MIPI DSI host wrapper driver Manikandan Muralidharan
2024-08-14 10:52 ` [PATCH v3 4/4] ARM: configs: at91: Enable Microchip's MIPI DSI Host Controller support Manikandan Muralidharan
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