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From: Conor Dooley <conor@kernel.org>
To: linux-riscv@lists.infradead.org
Cc: conor@kernel.org, "Conor Dooley" <conor.dooley@microchip.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Clément Léger" <cleger@rivosinc.com>,
	"Andy Chiu" <andybnac@gmail.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [RFC v1 4/5] dt-bindings: riscv: add vector sub-extension dependencies
Date: Wed,  2 Oct 2024 17:10:57 +0100	[thread overview]
Message-ID: <20241002-eagle-fresh-4b2e259e45ee@spud> (raw)
In-Reply-To: <20241002-defeat-pavestone-73d712895f0b@spud>

From: Conor Dooley <conor.dooley@microchip.com>

Section 33.18.2. Zve*: Vector Extensions for Embedded Processors
in [1] says:
| The Zve32f and Zve64x extensions depend on the Zve32x extension. The Zve64f extension depends
| on the Zve32f and Zve64x extensions. The Zve64d extension depends on the Zve64f extension

| The Zve32x extension depends on the Zicsr extension. The Zve32f and Zve64f extensions depend
| upon the F extension

| The Zve64d extension depends upon the D extension

Apply these rules to the bindings to help prevent invalid combinations.

Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-698e64a-2024-09-09 [1]
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../devicetree/bindings/riscv/extensions.yaml | 46 +++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 779f5cfab806e..abf2579171c5b 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -605,6 +605,52 @@ properties:
           contains:
             const: zca
 
+      - if:
+          contains:
+            const: zve32x
+        then:
+          contains:
+            const: zicsr
+
+      - if:
+          contains:
+            const: zve32f
+        then:
+          allOf:
+            - contains:
+                const: f
+            - contains:
+                const: zve32x
+
+      - if:
+          contains:
+            const: zve64x
+        then:
+          contains:
+            const: zve32x
+
+      - if:
+          contains:
+            const: zve64f
+        then:
+          allOf:
+            - contains:
+                const: f
+            - contains:
+                const: zve32f
+            - contains:
+                const: zve64x
+
+      - if:
+          contains:
+            const: zve64d
+        then:
+          allOf:
+            - contains:
+                const: d
+            - contains:
+                const: zve64f
+
 allOf:
   # Zcf extension does not exist on rv64
   - if:
-- 
2.45.2


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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: linux-riscv@lists.infradead.org
Cc: conor@kernel.org, "Conor Dooley" <conor.dooley@microchip.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Clément Léger" <cleger@rivosinc.com>,
	"Andy Chiu" <andybnac@gmail.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [RFC v1 4/5] dt-bindings: riscv: add vector sub-extension dependencies
Date: Wed,  2 Oct 2024 17:10:57 +0100	[thread overview]
Message-ID: <20241002-eagle-fresh-4b2e259e45ee@spud> (raw)
In-Reply-To: <20241002-defeat-pavestone-73d712895f0b@spud>

From: Conor Dooley <conor.dooley@microchip.com>

Section 33.18.2. Zve*: Vector Extensions for Embedded Processors
in [1] says:
| The Zve32f and Zve64x extensions depend on the Zve32x extension. The Zve64f extension depends
| on the Zve32f and Zve64x extensions. The Zve64d extension depends on the Zve64f extension

| The Zve32x extension depends on the Zicsr extension. The Zve32f and Zve64f extensions depend
| upon the F extension

| The Zve64d extension depends upon the D extension

Apply these rules to the bindings to help prevent invalid combinations.

Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-698e64a-2024-09-09 [1]
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../devicetree/bindings/riscv/extensions.yaml | 46 +++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 779f5cfab806e..abf2579171c5b 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -605,6 +605,52 @@ properties:
           contains:
             const: zca
 
+      - if:
+          contains:
+            const: zve32x
+        then:
+          contains:
+            const: zicsr
+
+      - if:
+          contains:
+            const: zve32f
+        then:
+          allOf:
+            - contains:
+                const: f
+            - contains:
+                const: zve32x
+
+      - if:
+          contains:
+            const: zve64x
+        then:
+          contains:
+            const: zve32x
+
+      - if:
+          contains:
+            const: zve64f
+        then:
+          allOf:
+            - contains:
+                const: f
+            - contains:
+                const: zve32f
+            - contains:
+                const: zve64x
+
+      - if:
+          contains:
+            const: zve64d
+        then:
+          allOf:
+            - contains:
+                const: d
+            - contains:
+                const: zve64f
+
 allOf:
   # Zcf extension does not exist on rv64
   - if:
-- 
2.45.2


  parent reply	other threads:[~2024-10-02 16:12 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-02 16:10 [RFC v1 0/5] Add some validation for vector, vector crypto and fp stuff Conor Dooley
2024-10-02 16:10 ` Conor Dooley
2024-10-02 16:10 ` [RFC v1 1/5] RISC-V: add vector crypto extension validation checks Conor Dooley
2024-10-02 16:10   ` Conor Dooley
2024-10-02 16:10 ` [RFC v1 2/5] RISC-V: add f & d " Conor Dooley
2024-10-02 16:10   ` Conor Dooley
2024-10-03  7:49   ` Clément Léger
2024-10-03  7:49     ` Clément Léger
2024-10-03 10:57     ` Conor Dooley
2024-10-03 10:57       ` Conor Dooley
2024-10-02 16:10 ` [RFC v1 3/5] dt-bindings: riscv: d requires f Conor Dooley
2024-10-02 16:10   ` Conor Dooley
2024-10-03  7:46   ` Clément Léger
2024-10-03  7:46     ` Clément Léger
2024-10-03  9:50   ` Krzysztof Kozlowski
2024-10-03  9:50     ` Krzysztof Kozlowski
2024-10-02 16:10 ` Conor Dooley [this message]
2024-10-02 16:10   ` [RFC v1 4/5] dt-bindings: riscv: add vector sub-extension dependencies Conor Dooley
2024-10-03  7:52   ` Clément Léger
2024-10-03  7:52     ` Clément Léger
2024-10-03  9:52   ` Krzysztof Kozlowski
2024-10-03  9:52     ` Krzysztof Kozlowski
2024-10-02 16:10 ` [RFC v1 5/5] dt-bindings: riscv: document vector crypto requirements Conor Dooley
2024-10-02 16:10   ` Conor Dooley
2024-10-03  7:59   ` Clément Léger
2024-10-03  7:59     ` Clément Léger
2024-10-03 11:05     ` Conor Dooley
2024-10-03 11:05       ` Conor Dooley
2024-10-03 11:36       ` Clément Léger
2024-10-03 11:36         ` Clément Léger
2024-10-03  9:52   ` Krzysztof Kozlowski
2024-10-03  9:52     ` Krzysztof Kozlowski

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