Re: [PATCH v2 2/2] dt-bindings: mtd: davinci: convert to yaml

[Rob Herring <robh@kernel.org>]

On Wed, Oct 02, 2024 at 11:01:31AM +0200, Marcus Folkesson wrote:
> Convert the bindings to yaml format.
> 
> Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
> ---
>  .../devicetree/bindings/mtd/davinci-nand.txt       |  94 ------------------
>  .../devicetree/bindings/mtd/ti,davinci-nand.yaml   | 105 +++++++++++++++++++++
>  2 files changed, 105 insertions(+), 94 deletions(-)
> 

> diff --git a/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml b/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..c0e09cccea8e65a6fcb98291c0cee0db56a97def
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
> @@ -0,0 +1,105 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: TI DaVinci NAND controller
> +
> +maintainers:
> +  - Marcus Folkesson <marcus.folkesson@gmail.com>
> +
> +allOf:
> +  - $ref: nand-controller.yaml#
> +
> +properties:
> +  compatible:
> +    enum:
> +      - ti,davinci-nand
> +      - ti,keystone-nand
> +
> +  reg:
> +    maxItems: 1
> +
> +  ti,davinci-chipselect:
> +    description: |

Don't need '|' if no formatting.

> +      Number of chipselect. Indicate on the davinci_nand
> +      driver which chipselect is used for accessing
> +      the nand.

Wrap lines at 80 char.

> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1, 2, 3]
> +
> +  ti,davinci-mask-ale:
> +    description: |
> +      Mask for ALE. Needed for executing address
> +      phase. These offset will be added to the base
> +      address for the chip select space the NAND Flash
> +      device is connected to.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 0x08
> +
> +  ti,davinci-mask-cle:
> +    description: |
> +      Mask for CLE. Needed for executing command
> +      phase. These offset will be added to the base
> +      address for the chip select space the NAND Flash
> +      device is connected to.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 0x10
> +
> +  ti,davinci-mask-chipsel:
> +    description: |
> +      Mask for chipselect address. Needed to mask
> +      addresses for given chipselect.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 0
> +
> +  ti,davinci-ecc-bits:
> +    description: Used ECC bits.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [1, 4]
> +
> +  ti,davinci-ecc-mode:
> +    description: Operation mode of the NAND ECC mode.
> +    $ref: /schemas/types.yaml#/definitions/string
> +    enum: [none, soft, hw, on-die]
> +    deprecated: true
> +
> +  ti,davinci-nand-buswidth:
> +    description: Bus width to the NAND chip
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [8, 16]
> +    default: 8
> +    deprecated: true
> +
> +  ti,davinci-nand-use-bbt:
> +    type: boolean
> +    description: |
> +      Use flash based bad block table support. OOB
> +      identifier is saved in OOB area.
> +    deprecated: true
> +
> +required:
> +  - compatible
> +  - reg
> +  - ti,davinci-chipselect
> +
> +examples:
> +  - |
> +    nand_cs3@62000000 {

nand-controller@...

> +    compatible = "ti,davinci-nand";
> +    reg = <0x62000000 0x807ff
> +    0x68000000 0x8000>;
> +    ti,davinci-chipselect = <1>;
> +    ti,davinci-mask-ale = <0>;
> +    ti,davinci-mask-cle = <0>;
> +    ti,davinci-mask-chipsel = <0>;
> +    nand-ecc-mode = "hw";
> +    ti,davinci-ecc-bits = <4>;
> +    nand-on-flash-bbt;

Wrong indentation.

> +
> +        partition@180000 {
> +            label = "ubifs";
> +            reg = <0x180000 0x7e80000>;
> +        };
> +    };
> 
> -- 
> 2.46.0
> 

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