* [PATCH 8/8] ARM: dts: socfpga: add Enclustra SoM dts files
2024-10-07 13:31 [PATCH 0/8] Add Enclustra Arria10 and Cyclone5 SoMs Lothar Rubusch
@ 2024-10-07 13:31 ` Lothar Rubusch
0 siblings, 0 replies; 2+ messages in thread
From: Lothar Rubusch @ 2024-10-07 13:31 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, dinguyen, marex, s.trumtrar
Cc: l.rubusch, devicetree, linux-kernel
Add the approach to set up a combination of Enclustra's SoM on a carrier
board and corresponding boot-mode as single device-tree target.
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
arch/arm/boot/dts/intel/socfpga/Makefile | 24 +++++++++++++++++++
.../socfpga_arria10_mercury_aa1_pe1_emmc.dts | 16 +++++++++++++
.../socfpga_arria10_mercury_aa1_pe1_qspi.dts | 16 +++++++++++++
.../socfpga_arria10_mercury_aa1_pe1_sdmmc.dts | 16 +++++++++++++
.../socfpga_arria10_mercury_aa1_pe3_emmc.dts | 16 +++++++++++++
.../socfpga_arria10_mercury_aa1_pe3_qspi.dts | 16 +++++++++++++
.../socfpga_arria10_mercury_aa1_pe3_sdmmc.dts | 16 +++++++++++++
.../socfpga_arria10_mercury_aa1_st1_emmc.dts | 16 +++++++++++++
.../socfpga_arria10_mercury_aa1_st1_qspi.dts | 16 +++++++++++++
.../socfpga_arria10_mercury_aa1_st1_sdmmc.dts | 16 +++++++++++++
.../socfpga_cyclone5_mercury_sa1_pe1_emmc.dts | 16 +++++++++++++
.../socfpga_cyclone5_mercury_sa1_pe1_qspi.dts | 16 +++++++++++++
...socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts | 16 +++++++++++++
.../socfpga_cyclone5_mercury_sa1_pe3_emmc.dts | 16 +++++++++++++
.../socfpga_cyclone5_mercury_sa1_pe3_qspi.dts | 16 +++++++++++++
...socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts | 16 +++++++++++++
.../socfpga_cyclone5_mercury_sa1_st1_emmc.dts | 16 +++++++++++++
.../socfpga_cyclone5_mercury_sa1_st1_qspi.dts | 16 +++++++++++++
...socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts | 16 +++++++++++++
.../socfpga_cyclone5_mercury_sa2_pe1_qspi.dts | 16 +++++++++++++
...socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts | 16 +++++++++++++
.../socfpga_cyclone5_mercury_sa2_pe3_qspi.dts | 16 +++++++++++++
...socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts | 16 +++++++++++++
.../socfpga_cyclone5_mercury_sa2_st1_qspi.dts | 16 +++++++++++++
...socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts | 16 +++++++++++++
25 files changed, 408 insertions(+)
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts
diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile
index d95862e34..861880560 100644
--- a/arch/arm/boot/dts/intel/socfpga/Makefile
+++ b/arch/arm/boot/dts/intel/socfpga/Makefile
@@ -2,6 +2,30 @@
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_arria10_chameleonv3.dtb \
+ socfpga_arria10_mercury_aa1_pe1_emmc.dtb \
+ socfpga_arria10_mercury_aa1_pe1_qspi.dtb \
+ socfpga_arria10_mercury_aa1_pe1_sdmmc.dtb \
+ socfpga_arria10_mercury_aa1_pe3_emmc.dtb \
+ socfpga_arria10_mercury_aa1_pe3_qspi.dtb \
+ socfpga_arria10_mercury_aa1_pe3_sdmmc.dtb \
+ socfpga_arria10_mercury_aa1_st1_emmc.dtb \
+ socfpga_arria10_mercury_aa1_st1_qspi.dtb \
+ socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \
+ socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \
+ socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \
+ socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \
+ socfpga_cyclone5_mercury_sa1_pe3_emmc.dtb \
+ socfpga_cyclone5_mercury_sa1_pe3_qspi.dtb \
+ socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dtb \
+ socfpga_cyclone5_mercury_sa1_st1_emmc.dtb \
+ socfpga_cyclone5_mercury_sa1_st1_qspi.dtb \
+ socfpga_cyclone5_mercury_sa1_st1_sdmmc.dtb \
+ socfpga_cyclone5_mercury_sa2_pe1_qspi.dtb \
+ socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dtb \
+ socfpga_cyclone5_mercury_sa2_pe3_qspi.dtb \
+ socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dtb \
+ socfpga_cyclone5_mercury_sa2_st1_qspi.dtb \
+ socfpga_cyclone5_mercury_sa2_st1_sdmmc.dtb \
socfpga_arria10_socdk_nand.dtb \
socfpga_arria10_socdk_qspi.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts
new file mode 100644
index 000000000..b6cca0b5f
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_arria10_mercury_aa1.dtsi"
+#include "socfpga_enclustra_mercury_pe1.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
+
+/ {
+ model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board";
+ compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1",
+ "altr,socfpga-cyclone5", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts
new file mode 100644
index 000000000..6ad023477
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_arria10_mercury_aa1.dtsi"
+#include "socfpga_enclustra_mercury_pe1.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
+
+/ {
+ model = "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board";
+ compatible = "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1",
+ "altr,socfpga-arria10", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts
new file mode 100644
index 000000000..653c9a865
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_arria10_mercury_aa1.dtsi"
+#include "socfpga_enclustra_mercury_pe1.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
+
+/ {
+ model = "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board";
+ compatible = "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1",
+ "altr,socfpga-arria10", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts
new file mode 100644
index 000000000..ae9c7c6a2
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_arria10_mercury_aa1.dtsi"
+#include "socfpga_enclustra_mercury_pe3.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
+
+/ {
+ model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board";
+ compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1",
+ "altr,socfpga-arria10", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts
new file mode 100644
index 000000000..c3a0c30a0
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_arria10_mercury_aa1.dtsi"
+#include "socfpga_enclustra_mercury_pe3.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
+
+/ {
+ model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board";
+ compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1",
+ "altr,socfpga-arria10", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts
new file mode 100644
index 000000000..dc1e1ad20
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_arria10_mercury_aa1.dtsi"
+#include "socfpga_enclustra_mercury_pe3.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
+
+/ {
+ model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board";
+ compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1",
+ "altr,socfpga-arria10", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts
new file mode 100644
index 000000000..61d5e4c85
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_arria10_mercury_aa1.dtsi"
+#include "socfpga_enclustra_mercury_st1.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
+
+/ {
+ model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board";
+ compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1",
+ "altr,socfpga-arria10", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts
new file mode 100644
index 000000000..a3b99c9b1
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_arria10_mercury_aa1.dtsi"
+#include "socfpga_enclustra_mercury_st1.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
+
+/ {
+ model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board";
+ compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1",
+ "altr,socfpga-arria10", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts
new file mode 100644
index 000000000..5deb289e2
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_arria10_mercury_aa1.dtsi"
+#include "socfpga_enclustra_mercury_st1.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
+
+/ {
+ model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board";
+ compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1",
+ "altr,socfpga-arria10", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts
new file mode 100644
index 000000000..85d6146da
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_cyclone5_mercury_sa1.dtsi"
+#include "socfpga_enclustra_mercury_pe1.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
+
+/ {
+ model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board";
+ compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-aa1",
+ "altr,socfpga-arria10", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts
new file mode 100644
index 000000000..770ab680a
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_cyclone5_mercury_sa1.dtsi"
+#include "socfpga_enclustra_mercury_pe1.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
+
+/ {
+ model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board";
+ compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1",
+ "altr,socfpga-cyclone5", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts
new file mode 100644
index 000000000..990ca0fec
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_cyclone5_mercury_sa1.dtsi"
+#include "socfpga_enclustra_mercury_pe1.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
+
+/ {
+ model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board";
+ compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1",
+ "altr,socfpga-cyclone5", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts
new file mode 100644
index 000000000..6c8fd5b0d
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_cyclone5_mercury_sa1.dtsi"
+#include "socfpga_enclustra_mercury_pe3.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
+
+/ {
+ model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board";
+ compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1",
+ "altr,socfpga-cyclone5", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts
new file mode 100644
index 000000000..329242607
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_cyclone5_mercury_sa1.dtsi"
+#include "socfpga_enclustra_mercury_pe3.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
+
+/ {
+ model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board";
+ compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1",
+ "altr,socfpga-cyclone5", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts
new file mode 100644
index 000000000..1eb10b524
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_cyclone5_mercury_sa1.dtsi"
+#include "socfpga_enclustra_mercury_pe3.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
+
+/ {
+ model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board";
+ compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1",
+ "altr,socfpga-cyclone5", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts
new file mode 100644
index 000000000..8c97b5b3a
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_cyclone5_mercury_sa1.dtsi"
+#include "socfpga_enclustra_mercury_st1.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
+
+/ {
+ model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board";
+ compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1",
+ "altr,socfpga-cyclone5", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts
new file mode 100644
index 000000000..e6d14b22e
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_cyclone5_mercury_sa1.dtsi"
+#include "socfpga_enclustra_mercury_st1.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
+
+/ {
+ model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board";
+ compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1",
+ "altr,socfpga-cyclone5", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts
new file mode 100644
index 000000000..beaeca94d
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_cyclone5_mercury_sa1.dtsi"
+#include "socfpga_enclustra_mercury_st1.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
+
+/ {
+ model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board";
+ compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1",
+ "altr,socfpga-cyclone5", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts
new file mode 100644
index 000000000..6f79d9ed1
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_cyclone5_mercury_sa2.dtsi"
+#include "socfpga_enclustra_mercury_pe1.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
+
+/ {
+ model = "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board";
+ compatible = "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2",
+ "altr,socfpga-cyclone5", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts
new file mode 100644
index 000000000..b94bd8baf
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_cyclone5_mercury_sa2.dtsi"
+#include "socfpga_enclustra_mercury_pe1.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
+
+/ {
+ model = "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board";
+ compatible = "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2",
+ "altr,socfpga-cyclone5", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts
new file mode 100644
index 000000000..51fc4a229
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_cyclone5_mercury_sa2.dtsi"
+#include "socfpga_enclustra_mercury_pe3.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
+
+/ {
+ model = "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board";
+ compatible = "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2",
+ "altr,socfpga-cyclone5", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts
new file mode 100644
index 000000000..e4209209f
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_cyclone5_mercury_sa2.dtsi"
+#include "socfpga_enclustra_mercury_pe3.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
+
+/ {
+ model = "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board";
+ compatible = "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2",
+ "altr,socfpga-cyclone5", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts
new file mode 100644
index 000000000..ab4549a0d
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_cyclone5_mercury_sa2.dtsi"
+#include "socfpga_enclustra_mercury_st1.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
+
+/ {
+ model = "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board";
+ compatible = "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2",
+ "altr,socfpga-cyclone5", "altr,socfpga";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts
new file mode 100644
index 000000000..ebe62879c
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+/dts-v1/;
+
+#include "socfpga_cyclone5_mercury_sa2.dtsi"
+#include "socfpga_enclustra_mercury_st1.dtsi"
+#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
+
+/ {
+ model = "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board";
+ compatible = "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2",
+ "altr,socfpga-cyclone5", "altr,socfpga";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH 8/8] ARM: dts: socfpga: add Enclustra SoM dts files
@ 2024-10-08 13:52 kernel test robot
0 siblings, 0 replies; 2+ messages in thread
From: kernel test robot @ 2024-10-08 13:52 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp
::::::
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
::::::
BCC: lkp@intel.com
CC: llvm@lists.linux.dev
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20241007133115.1482619-9-l.rubusch@gmail.com>
References: <20241007133115.1482619-9-l.rubusch@gmail.com>
TO: Lothar Rubusch <l.rubusch@gmail.com>
TO: robh@kernel.org
TO: krzk+dt@kernel.org
TO: conor+dt@kernel.org
TO: dinguyen@kernel.org
TO: marex@denx.de
TO: s.trumtrar@pengutronix.de
CC: l.rubusch@gmail.com
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
Hi Lothar,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master v6.12-rc2 next-20241008]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Lothar-Rubusch/ARM-dts-socfpga-fix-dtschema-issues/20241007-213514
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20241007133115.1482619-9-l.rubusch%40gmail.com
patch subject: [PATCH 8/8] ARM: dts: socfpga: add Enclustra SoM dts files
:::::: branch date: 24 hours ago
:::::: commit date: 24 hours ago
config: arm-randconfig-001-20241008 (https://download.01.org/0day-ci/archive/20241008/202410082141.XSjVC0sV-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241008/202410082141.XSjVC0sV-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202410082141.XSjVC0sV-lkp@intel.com/
dtcheck warnings: (new ones prefixed by >>)
>> arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi:35.9-39.4: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi:90.15-96.5: Warning (simple_bus_reg): /soc/fpga-region: missing or empty reg/ranges property
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi:563.40-567.5: Warning (simple_bus_reg): /soc/stmmac-axi-config: missing or empty reg/ranges property
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi:714.18-732.5: Warning (simple_bus_reg): /soc/eccmgr: missing or empty reg/ranges property
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi:823.13-827.5: Warning (simple_bus_reg): /soc/sdramedac: missing or empty reg/ranges property
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi:934.19-938.5: Warning (simple_bus_reg): /soc/usbphy: missing or empty reg/ranges property
--
>> arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi:35.9-39.4: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi:90.15-96.5: Warning (simple_bus_reg): /soc/fpga-region: missing or empty reg/ranges property
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi:563.40-567.5: Warning (simple_bus_reg): /soc/stmmac-axi-config: missing or empty reg/ranges property
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi:714.18-732.5: Warning (simple_bus_reg): /soc/eccmgr: missing or empty reg/ranges property
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi:823.13-827.5: Warning (simple_bus_reg): /soc/sdramedac: missing or empty reg/ranges property
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi:934.19-938.5: Warning (simple_bus_reg): /soc/usbphy: missing or empty reg/ranges property
vim +35 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi
b4646a1f0f7278 Lothar Rubusch 2024-10-07 7
b4646a1f0f7278 Lothar Rubusch 2024-10-07 8 / {
b4646a1f0f7278 Lothar Rubusch 2024-10-07 9 model = "Enclustra Mercury+ SA2";
b4646a1f0f7278 Lothar Rubusch 2024-10-07 10 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
b4646a1f0f7278 Lothar Rubusch 2024-10-07 11
b4646a1f0f7278 Lothar Rubusch 2024-10-07 12 chosen {
b4646a1f0f7278 Lothar Rubusch 2024-10-07 13 stdout-path = "serial0:115200n8";
b4646a1f0f7278 Lothar Rubusch 2024-10-07 14 };
b4646a1f0f7278 Lothar Rubusch 2024-10-07 15
b4646a1f0f7278 Lothar Rubusch 2024-10-07 16 aliases {
b4646a1f0f7278 Lothar Rubusch 2024-10-07 17 ethernet0 = &gmac1;
b4646a1f0f7278 Lothar Rubusch 2024-10-07 18 };
b4646a1f0f7278 Lothar Rubusch 2024-10-07 19
b4646a1f0f7278 Lothar Rubusch 2024-10-07 20 /* Adjusted the i2c labels to use generic base-board dtsi files for
b4646a1f0f7278 Lothar Rubusch 2024-10-07 21 * Enclustra Arria10 and Cyclone5 SoMs.
b4646a1f0f7278 Lothar Rubusch 2024-10-07 22 *
b4646a1f0f7278 Lothar Rubusch 2024-10-07 23 * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in
b4646a1f0f7278 Lothar Rubusch 2024-10-07 24 * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi
b4646a1f0f7278 Lothar Rubusch 2024-10-07 25 * fragments. Thus define generic labels here to match the correct i2c
b4646a1f0f7278 Lothar Rubusch 2024-10-07 26 * bus in a generic base-board .dtsi file.
b4646a1f0f7278 Lothar Rubusch 2024-10-07 27 */
b4646a1f0f7278 Lothar Rubusch 2024-10-07 28 soc {
b4646a1f0f7278 Lothar Rubusch 2024-10-07 29 i2c_encl: i2c@ffc04000 {
b4646a1f0f7278 Lothar Rubusch 2024-10-07 30 };
b4646a1f0f7278 Lothar Rubusch 2024-10-07 31 i2c_encl_fpga: i2c@ffc05000 {
b4646a1f0f7278 Lothar Rubusch 2024-10-07 32 };
b4646a1f0f7278 Lothar Rubusch 2024-10-07 33 };
b4646a1f0f7278 Lothar Rubusch 2024-10-07 34
b4646a1f0f7278 Lothar Rubusch 2024-10-07 @35 memory {
b4646a1f0f7278 Lothar Rubusch 2024-10-07 36 name = "memory";
b4646a1f0f7278 Lothar Rubusch 2024-10-07 37 device_type = "memory";
b4646a1f0f7278 Lothar Rubusch 2024-10-07 38 reg = <0x0 0x80000000>; /* 2GB */
b4646a1f0f7278 Lothar Rubusch 2024-10-07 39 };
b4646a1f0f7278 Lothar Rubusch 2024-10-07 40 };
b4646a1f0f7278 Lothar Rubusch 2024-10-07 41
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2024-10-08 13:52 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
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2024-10-07 13:31 [PATCH 0/8] Add Enclustra Arria10 and Cyclone5 SoMs Lothar Rubusch
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