From: Rob Herring <robh@kernel.org>
To: Qiang Yu <quic_qianyu@quicinc.com>
Cc: manivannan.sadhasivam@linaro.org, vkoul@kernel.org,
kishon@kernel.org, andersson@kernel.org, konradybcio@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com,
sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com,
quic_devipriy@quicinc.com, dmitry.baryshkov@linaro.org,
kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v5 3/7] dt-bindings: PCI: qcom,pcie-x1e80100: Add 'global' interrupt
Date: Wed, 9 Oct 2024 15:25:22 -0500 [thread overview]
Message-ID: <20241009202522.GA611063-robh@kernel.org> (raw)
In-Reply-To: <20241009091540.1446-4-quic_qianyu@quicinc.com>
On Wed, Oct 09, 2024 at 02:15:36AM -0700, Qiang Yu wrote:
> Document 'global' SPI interrupt along with the existing MSI interrupts so
> that QCOM PCIe RC driver can make use of it to get events such as PCIe
> link specific events, safety events, etc.
Is it required for some reason vs. being optional? It's fine to break
the ABI because...?
Answer those questions with your commit msg.
>
> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
> ---
> .../devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Qiang Yu <quic_qianyu@quicinc.com>
Cc: manivannan.sadhasivam@linaro.org, vkoul@kernel.org,
kishon@kernel.org, andersson@kernel.org, konradybcio@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com,
sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com,
quic_devipriy@quicinc.com, dmitry.baryshkov@linaro.org,
kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v5 3/7] dt-bindings: PCI: qcom,pcie-x1e80100: Add 'global' interrupt
Date: Wed, 9 Oct 2024 15:25:22 -0500 [thread overview]
Message-ID: <20241009202522.GA611063-robh@kernel.org> (raw)
In-Reply-To: <20241009091540.1446-4-quic_qianyu@quicinc.com>
On Wed, Oct 09, 2024 at 02:15:36AM -0700, Qiang Yu wrote:
> Document 'global' SPI interrupt along with the existing MSI interrupts so
> that QCOM PCIe RC driver can make use of it to get events such as PCIe
> link specific events, safety events, etc.
Is it required for some reason vs. being optional? It's fine to break
the ABI because...?
Answer those questions with your commit msg.
>
> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
> ---
> .../devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2024-10-09 20:25 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-09 9:15 [PATCH v5 0/7] Add support for PCIe3 on x1e80100 Qiang Yu
2024-10-09 9:15 ` Qiang Yu
2024-10-09 9:15 ` [PATCH v5 1/7] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8 Qiang Yu
2024-10-09 9:15 ` Qiang Yu
2024-10-09 9:15 ` [PATCH v5 2/7] dt-bindings: PCI: qcom: Move OPP table to qcom,pcie-common.yaml Qiang Yu
2024-10-09 9:15 ` Qiang Yu
2024-10-09 9:15 ` [PATCH v5 3/7] dt-bindings: PCI: qcom,pcie-x1e80100: Add 'global' interrupt Qiang Yu
2024-10-09 9:15 ` Qiang Yu
2024-10-09 20:25 ` Rob Herring [this message]
2024-10-09 20:25 ` Rob Herring
2024-10-09 9:15 ` [PATCH v5 4/7] phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 Qiang Yu
2024-10-09 9:15 ` Qiang Yu
2024-10-09 9:15 ` [PATCH v5 5/7] clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks Qiang Yu
2024-10-09 9:15 ` Qiang Yu
2024-10-09 9:15 ` [PATCH v5 6/7] PCI: qcom: Fix the ops for X1E80100 and SC8280X family SoC Qiang Yu
2024-10-09 9:15 ` Qiang Yu
2024-10-10 13:50 ` Dmitry Baryshkov
2024-10-10 13:50 ` Dmitry Baryshkov
2024-10-09 9:15 ` [PATCH v5 7/7] arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 Qiang Yu
2024-10-09 9:15 ` Qiang Yu
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