Re: [PATCH v1 10/11] riscv: dts: microchip: fix mailbox description

From: Conor Dooley <conor@kernel.org>
To: linux-kernel@vger.kernel.org
Cc: Conor Dooley <conor.dooley@microchip.com>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	pierre-henry.moussay@microchip.com,
	valentina.fernandezalanis@microchip.com,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Jassi Brar <jassisinghbrar@gmail.com>, Lee Jones <lee@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Kevin Hilman <khilman@baylibre.com>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v1 10/11] riscv: dts: microchip: fix mailbox description
Date: Mon, 14 Oct 2024 16:41:19 +0100	[thread overview]
Message-ID: <20241014-decorator-coma-bdaca54f459b@spud> (raw)
In-Reply-To: <20241002-finch-sugar-9958077e8c2b@spud>

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On Wed, Oct 02, 2024 at 11:48:08AM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> When the binding for the mailbox on PolarFire SoC was originally
> written, and later modified, mistakes were made - and the precise
> nature of the later modification should have been a giveaway, but alas
> I was naive at the time.
> 
> A more correct modelling of the hardware is to use two syscons and have
> a single reg entry for the mailbox, containing the mailbox region. The
> two syscons contain the general control/status registers for the mailbox
> and the interrupt related registers respectively. The reason for two
> syscons is that the same mailbox is present on the non-SoC version of
> the FPGA, which has no interrupt controller, and the shared part of the
> rtl was unchanged between devices.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  arch/riscv/boot/dts/microchip/mpfs.dtsi | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> index 9883ca3554c50..f8a45e4f00a0d 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> @@ -259,6 +259,11 @@ clkcfg: clkcfg@20002000 {
>  			#reset-cells = <1>;
>  		};
>  
> +		sysreg_scb: syscon@20003000 {
> +			compatible = "microchip,mpfs-sysreg-scb", "syscon";
> +			reg = <0x0 0x20003000 0x0 0x1000>;
> +		};
> +
>  		ccc_se: clock-controller@38010000 {
>  			compatible = "microchip,mpfs-ccc";
>  			reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>,
> @@ -521,10 +526,14 @@ usb: usb@20201000 {
>  			status = "disabled";
>  		};
>  
> -		mbox: mailbox@37020000 {
> +		control_scb: syscon@37020000 {
> +			compatible = "microchip,mpfs-control-scb", "syscon", "simple-mfd";
> +			reg = <0x0 0x37020000 0x0 0x100>;

It came up today that this 0x100 isn't correct - the actual size here is
4 KiB, so there's a zero missing.

> +		};
> +
> +		mbox: mailbox@37020800 {
>  			compatible = "microchip,mpfs-mailbox";
> -			reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
> -			      <0x0 0x37020800 0x0 0x100>;
> +			reg = <0x0 0x37020800 0x0 0x100>;
>  			interrupt-parent = <&plic>;
>  			interrupts = <96>;
>  			#mbox-cells = <1>;
> -- 
> 2.45.2
> 

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