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From: Jason Gunthorpe <jgg@nvidia.com>
To: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev,
	joro@8bytes.org, robin.murphy@arm.com, vasant.hegde@amd.com,
	kevin.tian@intel.com, jon.grimm@amd.com, santosh.shukla@amd.com,
	pandoh@google.com, kumaranand@google.com
Subject: Re: [PATCH v6 4/9] iommu/amd: Introduce per-device DTE cache to store persistent bits
Date: Wed, 16 Oct 2024 10:21:04 -0300	[thread overview]
Message-ID: <20241016132104.GK3559746@nvidia.com> (raw)
In-Reply-To: <20241016051756.4317-5-suravee.suthikulpanit@amd.com>

On Wed, Oct 16, 2024 at 05:17:51AM +0000, Suravee Suthikulpanit wrote:
> diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
> index f537b264f118..3f53d3bc79cb 100644
> --- a/drivers/iommu/amd/amd_iommu_types.h
> +++ b/drivers/iommu/amd/amd_iommu_types.h
> @@ -830,6 +830,16 @@ struct devid_map {
>  /* Device may request super-user privileges */
>  #define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP   0x10
>  
> +/*
> + * Structure defining one entry in the device table
> + */
> +struct dev_table_entry {
> +	union {
> +		u64 data[4];
> +		u128 data128[2];
> +	};
> +};

It would be appropriate to put this hunk into the prior patch so your
series does not move code it just added..

>  /*
>   * This struct contains device specific data for the IOMMU
>   */
> @@ -858,6 +868,7 @@ struct iommu_dev_data {
>  	bool defer_attach;
>  
>  	struct ratelimit_state rs;        /* Ratelimit IOPF messages */
> +	struct dev_table_entry dte_cache;
>  };

I would call this initial_dte or something, it isn't a cache, it is
the recoding of the ACPI data into a DTE format.

 /* Stores INIT/EINT,NMIm SYSMGTx,LINTx values from ACPI */
 struct dev_tabl_entry initial_dte;

> @@ -1159,19 +1171,19 @@ static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
>  					   u16 devid, u32 flags, u32 ext_flags)
>  {
>  	if (flags & ACPI_DEVFLAG_INITPASS)
> -		set_dev_entry_bit(iommu, devid, DEV_ENTRY_INIT_PASS);
> +		set_dte_cache_bit(iommu, devid, DEV_ENTRY_INIT_PASS);
>  	if (flags & ACPI_DEVFLAG_EXTINT)
> -		set_dev_entry_bit(iommu, devid, DEV_ENTRY_EINT_PASS);
> +		set_dte_cache_bit(iommu, devid, DEV_ENTRY_EINT_PASS);
>  	if (flags & ACPI_DEVFLAG_NMI)
> -		set_dev_entry_bit(iommu, devid, DEV_ENTRY_NMI_PASS);
> +		set_dte_cache_bit(iommu, devid, DEV_ENTRY_NMI_PASS);
>  	if (flags & ACPI_DEVFLAG_SYSMGT1)
> -		set_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT1);
> +		set_dte_cache_bit(iommu, devid, DEV_ENTRY_SYSMGT1);
>  	if (flags & ACPI_DEVFLAG_SYSMGT2)
> -		set_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT2);
> +		set_dte_cache_bit(iommu, devid, DEV_ENTRY_SYSMGT2);
>  	if (flags & ACPI_DEVFLAG_LINT0)
> -		set_dev_entry_bit(iommu, devid, DEV_ENTRY_LINT0_PASS);
> +		set_dte_cache_bit(iommu, devid, DEV_ENTRY_LINT0_PASS);
>  	if (flags & ACPI_DEVFLAG_LINT1)
> -		set_dev_entry_bit(iommu, devid, DEV_ENTRY_LINT1_PASS);
> +		set_dte_cache_bit(iommu, devid, DEV_ENTRY_LINT1_PASS);

Doesn't this break the driver at this patch? Nothing reads from the
dte_cache at this point in the series so the real DTE never got these
bits?

Maybe just add a temporary line here to copy the entire dte_cache to
the real dte? The next patch fixes it I think?

But I like the idea, I think this is the a much more understandable
direction to go.

Jason

  reply	other threads:[~2024-10-16 13:21 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-16  5:17 [PATCH v6 0/9] iommu/amd: Use 128-bit cmpxchg operation to update DTE Suravee Suthikulpanit
2024-10-16  5:17 ` [PATCH v6 1/9] iommu/amd: Disable AMD IOMMU if CMPXCHG16B feature is not supported Suravee Suthikulpanit
2024-10-16  5:17 ` [PATCH v6 2/9] asm/rwonce: Introduce [READ|WRITE]_ONCE() support for __int128 Suravee Suthikulpanit
2024-10-16 13:08   ` Jason Gunthorpe
2024-10-16  5:17 ` [PATCH v6 3/9] iommu/amd: Introduce helper function to update 256-bit DTE Suravee Suthikulpanit
2024-10-16  5:17 ` [PATCH v6 4/9] iommu/amd: Introduce per-device DTE cache to store persistent bits Suravee Suthikulpanit
2024-10-16 13:21   ` Jason Gunthorpe [this message]
2024-10-16  5:17 ` [PATCH v6 5/9] iommu/amd: Modify set_dte_entry() to use 256-bit DTE helpers Suravee Suthikulpanit
2024-10-16 13:52   ` Jason Gunthorpe
2024-10-16 14:07   ` Jason Gunthorpe
2024-10-16 14:12   ` Jason Gunthorpe
2024-10-16  5:17 ` [PATCH v6 6/9] iommu/amd: Introduce helper function get_dte256() Suravee Suthikulpanit
2024-10-16  5:17 ` [PATCH v6 7/9] iommu/amd: Move erratum 63 logic to write_dte_lower128() Suravee Suthikulpanit
2024-10-16 13:30   ` Jason Gunthorpe
2024-10-31  8:53     ` Suthikulpanit, Suravee
2024-10-31  8:53     ` Suthikulpanit, Suravee
2024-10-16  5:17 ` [PATCH v6 8/9] iommu/amd: Modify clear_dte_entry() to avoid in-place update Suravee Suthikulpanit
2024-10-16  5:17 ` [PATCH v6 9/9] iommu/amd: Lock DTE before updating the entry with WRITE_ONCE() Suravee Suthikulpanit
2024-10-16 14:22 ` [PATCH v6 0/9] iommu/amd: Use 128-bit cmpxchg operation to update DTE Jason Gunthorpe
2024-10-31  9:15   ` Suthikulpanit, Suravee
2024-10-31 11:33     ` Jason Gunthorpe

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