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From: Conor Dooley <conor@kernel.org>
To: Xu Yilun <yilun.xu@linux.intel.com>
Cc: iansdannapel@gmail.com, mdf@kernel.org, hao.wu@intel.com,
	yilun.xu@intel.com, trix@redhat.com, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org,
	neil.armstrong@linaro.org, heiko.stuebner@cherry.de,
	rafal@milecki.pl, linus.walleij@linaro.org,
	linux-fpga@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver
Date: Fri, 18 Oct 2024 17:58:44 +0100	[thread overview]
Message-ID: <20241018-chump-juvenile-dc368d3d2f2c@spud> (raw)
In-Reply-To: <ZxG70kzjsvT3UBlQ@yilunxu-OptiPlex-7050>

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On Fri, Oct 18, 2024 at 09:37:22AM +0800, Xu Yilun wrote:
> On Fri, Sep 27, 2024 at 04:14:42PM +0200, iansdannapel@gmail.com wrote:
> > From: Ian Dannapel <iansdannapel@gmail.com>
> > 
> > Add a new driver for loading binary firmware to volatile
> > configuration RAM using "SPI passive programming" on Efinix FPGAs.
> > 
> > Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
> > ---
> >  drivers/fpga/Kconfig                    |  10 ++
> >  drivers/fpga/Makefile                   |   1 +
> >  drivers/fpga/efinix-trion-spi-passive.c | 211 ++++++++++++++++++++++++
> >  3 files changed, 222 insertions(+)
> >  create mode 100644 drivers/fpga/efinix-trion-spi-passive.c
> > 
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > index 37b35f58f0df..eb1e44c4e3e0 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -83,6 +83,16 @@ config FPGA_MGR_XILINX_SPI
> >  	  FPGA manager driver support for Xilinx FPGA configuration
> >  	  over slave serial interface.
> >  
> > +config FPGA_MGR_EFINIX_SPI
> > +	tristate "Efinix FPGA configuration over SPI passive"
> > +	depends on SPI
> > +	help
> > +	  This option enables support for the FPGA manager driver to
> > +	  configure Efinix Trion and Titanium Series FPGAs over SPI
> > +	  using passive serial mode.
> > +	  Warning: Do not activate this if there are other SPI devices
> > +	  on the same bus as it might interfere with the transmission.
> 
> Sorry, this won't work. As you can see, the conflict usage of CS causes
> several concerns. Just a text here is far from enough.
> 
> You need to actively work with SPI core/controller drivers to find a
> solution that coordinate the usage of this pin.

Why does it even impact other SPI devices on the bus? It's not /their/
CS line that is being modified here, it is the line for the FPGA's
programming interface, right?
What am I missing here that makes it any different to any other SPI
device that may need it's CS toggled?

Cheers,
Conor.

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  reply	other threads:[~2024-10-18 16:58 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-27 14:14 [PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver iansdannapel
2024-09-27 14:14 ` [PATCH 2/3] dt-bindings: fpga: Add Efinix serial SPI programming bindings iansdannapel
2024-09-27 14:26   ` Krzysztof Kozlowski
2024-09-27 15:34     ` Ian Dannapel
2024-09-28  7:31       ` Krzysztof Kozlowski
2024-09-28 12:33         ` Ian Dannapel
2024-09-28 12:53           ` Krzysztof Kozlowski
2024-09-28 14:26             ` Ian Dannapel
2024-09-29 19:49               ` Krzysztof Kozlowski
2024-09-27 14:14 ` [PATCH 3/3] dt-bindings: vendor-prefix: Add prefix for Efinix, Inc iansdannapel
2024-09-27 14:26   ` Krzysztof Kozlowski
2024-09-30  6:23   ` Alexander Dahl
2024-09-27 14:14 ` [PATCH v3 0/3] Summary of changes iansdannapel
2024-09-27 14:27   ` Krzysztof Kozlowski
2024-09-27 14:22 ` [PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver Krzysztof Kozlowski
2024-10-18  1:22   ` Xu Yilun
2024-10-18  1:37 ` Xu Yilun
2024-10-18 16:58   ` Conor Dooley [this message]
2024-10-21  2:10     ` Xu Yilun
2024-10-21 12:18       ` Conor Dooley
2024-10-21 13:23         ` Ian Dannapel
  -- strict thread matches above, loose matches on Subject: below --
2024-06-20 14:42 iansdannapel
2024-06-20 18:05 ` Marco Pagani

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