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From: kernel test robot <lkp@intel.com>
To: oe-kbuild@lists.linux.dev
Cc: lkp@intel.com
Subject: Re: [PATCH 13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table
Date: Sat, 26 Oct 2024 02:12:10 +0800	[thread overview]
Message-ID: <202410260129.jgcKTWL5-lkp@intel.com> (raw)

:::::: 
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
:::::: 

BCC: lkp@intel.com
CC: llvm@lists.linux.dev
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20241024170540.2721307-14-masterr3c0rd@epochal.quest>
References: <20241024170540.2721307-14-masterr3c0rd@epochal.quest>
TO: Cody Eksal <masterr3c0rd@epochal.quest>
TO: linux-pm@vger.kernel.org
TO: devicetree@vger.kernel.org
TO: linux-arm-kernel@lists.infradead.org
TO: linux-sunxi@lists.linux.dev
TO: linux-kernel@vger.kernel.org
TO: linux-phy@lists.infradead.org
TO: linux-usb@vger.kernel.org
TO: Rob Herring <robh@kernel.org>
TO: Krzysztof Kozlowski <krzk@kernel.org>
TO: Conor Dooley <conor+dt@kernel.org>
TO: "Chen-Yu Tsai" <wens@csie.org>
TO: Jernej Skrabec <jernej.skrabec@gmail.com>
TO: Samuel Holland <samuel@sholland.org>
CC: Cody Eksal <masterr3c0rd@epochal.quest>
CC: Andre Przywara <andre.przywara@arm.com>
CC: Parthiban <parthiban@linumiz.com>
CC: Yangtao Li <frank@allwinnertech.com>
CC: Florian Fainelli <florian.fainelli@broadcom.com>
CC: Vinod Koul <vkoul@kernel.org>
CC: Linus Walleij <linus.walleij@linaro.org>
CC: Thierry Reding <treding@nvidia.com>
CC: Maxime Ripard <mripard@kernel.org>
CC: "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>
CC: Viresh Kumar <vireshk@kernel.org>
CC: Stephen Boyd <sboyd@kernel.org>
CC: Kishon Vijay Abraham I <kishon@kernel.org>
CC: "Rafael J. Wysocki" <rafael@kernel.org>
CC: Shuosheng Huang <huangshuosheng@allwinnertech.com>

Hi Cody,

kernel test robot noticed the following build warnings:

[auto build test WARNING on c2ee9f594da826bea183ed14f2cc029c719bf4da]

url:    https://github.com/intel-lab-lkp/linux/commits/Cody-Eksal/arm64-dts-allwinner-A100-Add-PMU-mode/20241025-012103
base:   c2ee9f594da826bea183ed14f2cc029c719bf4da
patch link:    https://lore.kernel.org/r/20241024170540.2721307-14-masterr3c0rd%40epochal.quest
patch subject: [PATCH 13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table
:::::: branch date: 25 hours ago
:::::: commit date: 25 hours ago
config: arm64-randconfig-001-20241025 (https://download.01.org/0day-ci/archive/20241026/202410260129.jgcKTWL5-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241026/202410260129.jgcKTWL5-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202410260129.jgcKTWL5-lkp@intel.com/

dtcheck warnings: (new ones prefixed by >>)
   arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi:102.6-560.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name
>> arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi:11.17-18.5: Warning (unit_address_vs_reg): /cpu-opp-table/opp@408000000: node has a unit name, but no reg or ranges property
   arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi:20.17-27.5: Warning (unit_address_vs_reg): /cpu-opp-table/opp@600000000: node has a unit name, but no reg or ranges property
   arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi:29.17-36.5: Warning (unit_address_vs_reg): /cpu-opp-table/opp@816000000: node has a unit name, but no reg or ranges property
   arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi:38.18-45.5: Warning (unit_address_vs_reg): /cpu-opp-table/opp@1080000000: node has a unit name, but no reg or ranges property
   arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi:47.18-54.5: Warning (unit_address_vs_reg): /cpu-opp-table/opp@1200000000: node has a unit name, but no reg or ranges property
   arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi:56.18-63.5: Warning (unit_address_vs_reg): /cpu-opp-table/opp@1320000000: node has a unit name, but no reg or ranges property
   arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi:65.18-72.5: Warning (unit_address_vs_reg): /cpu-opp-table/opp@1464000000: node has a unit name, but no reg or ranges property

vim +11 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi

9dfdd9102dd585 Shuosheng Huang 2024-10-24   4  
9dfdd9102dd585 Shuosheng Huang 2024-10-24   5  / {
9dfdd9102dd585 Shuosheng Huang 2024-10-24   6  	cpu_opp_table: cpu-opp-table {
9dfdd9102dd585 Shuosheng Huang 2024-10-24   7  		compatible = "allwinner,sun50i-a100-operating-points";
9dfdd9102dd585 Shuosheng Huang 2024-10-24   8  		nvmem-cells = <&cpu_speed_grade>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24   9  		opp-shared;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  10  
9dfdd9102dd585 Shuosheng Huang 2024-10-24 @11  		opp@408000000 {
9dfdd9102dd585 Shuosheng Huang 2024-10-24  12  			clock-latency-ns = <244144>; /* 8 32k periods */
9dfdd9102dd585 Shuosheng Huang 2024-10-24  13  			opp-hz = /bits/ 64 <408000000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  14  
9dfdd9102dd585 Shuosheng Huang 2024-10-24  15  			opp-microvolt-speed0 = <900000 900000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  16  			opp-microvolt-speed1 = <900000 900000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  17  			opp-microvolt-speed2 = <900000 900000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  18  		};
9dfdd9102dd585 Shuosheng Huang 2024-10-24  19  
9dfdd9102dd585 Shuosheng Huang 2024-10-24  20  		opp@600000000 {
9dfdd9102dd585 Shuosheng Huang 2024-10-24  21  			clock-latency-ns = <244144>; /* 8 32k periods */
9dfdd9102dd585 Shuosheng Huang 2024-10-24  22  			opp-hz = /bits/ 64 <600000000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  23  
9dfdd9102dd585 Shuosheng Huang 2024-10-24  24  			opp-microvolt-speed0 = <900000 900000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  25  			opp-microvolt-speed1 = <900000 900000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  26  			opp-microvolt-speed2 = <900000 900000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  27  		};
9dfdd9102dd585 Shuosheng Huang 2024-10-24  28  
9dfdd9102dd585 Shuosheng Huang 2024-10-24  29  		opp@816000000 {
9dfdd9102dd585 Shuosheng Huang 2024-10-24  30  			clock-latency-ns = <244144>; /* 8 32k periods */
9dfdd9102dd585 Shuosheng Huang 2024-10-24  31  			opp-hz = /bits/ 64 <816000000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  32  
9dfdd9102dd585 Shuosheng Huang 2024-10-24  33  			opp-microvolt-speed0 = <940000 940000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  34  			opp-microvolt-speed1 = <900000 900000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  35  			opp-microvolt-speed2 = <900000 900000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  36  		};
9dfdd9102dd585 Shuosheng Huang 2024-10-24  37  
9dfdd9102dd585 Shuosheng Huang 2024-10-24  38  		opp@1080000000 {
9dfdd9102dd585 Shuosheng Huang 2024-10-24  39  			clock-latency-ns = <244144>; /* 8 32k periods */
9dfdd9102dd585 Shuosheng Huang 2024-10-24  40  			opp-hz = /bits/ 64 <1080000000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  41  
9dfdd9102dd585 Shuosheng Huang 2024-10-24  42  			opp-microvolt-speed0 = <1020000 1020000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  43  			opp-microvolt-speed1 = <980000 980000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  44  			opp-microvolt-speed2 = <950000 950000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  45  		};
9dfdd9102dd585 Shuosheng Huang 2024-10-24  46  
9dfdd9102dd585 Shuosheng Huang 2024-10-24  47  		opp@1200000000 {
9dfdd9102dd585 Shuosheng Huang 2024-10-24  48  			clock-latency-ns = <244144>; /* 8 32k periods */
9dfdd9102dd585 Shuosheng Huang 2024-10-24  49  			opp-hz = /bits/ 64 <1200000000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  50  
9dfdd9102dd585 Shuosheng Huang 2024-10-24  51  			opp-microvolt-speed0 = <1100000 1100000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  52  			opp-microvolt-speed1 = <1020000 1020000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  53  			opp-microvolt-speed2 = <1000000 1000000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  54  		};
9dfdd9102dd585 Shuosheng Huang 2024-10-24  55  
9dfdd9102dd585 Shuosheng Huang 2024-10-24  56  		opp@1320000000 {
9dfdd9102dd585 Shuosheng Huang 2024-10-24  57  			clock-latency-ns = <244144>; /* 8 32k periods */
9dfdd9102dd585 Shuosheng Huang 2024-10-24  58  			opp-hz = /bits/ 64 <1320000000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  59  
9dfdd9102dd585 Shuosheng Huang 2024-10-24  60  			opp-microvolt-speed0 = <1160000 1160000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  61  			opp-microvolt-speed1 = <1060000 1060000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  62  			opp-microvolt-speed2 = <1030000 1030000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  63  		};
9dfdd9102dd585 Shuosheng Huang 2024-10-24  64  
9dfdd9102dd585 Shuosheng Huang 2024-10-24  65  		opp@1464000000 {
9dfdd9102dd585 Shuosheng Huang 2024-10-24  66  			clock-latency-ns = <244144>; /* 8 32k periods */
9dfdd9102dd585 Shuosheng Huang 2024-10-24  67  			opp-hz = /bits/ 64 <1464000000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  68  
9dfdd9102dd585 Shuosheng Huang 2024-10-24  69  			opp-microvolt-speed0 = <1180000 1180000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  70  			opp-microvolt-speed1 = <1180000 1180000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  71  			opp-microvolt-speed2 = <1130000 1130000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24  72  		};
9dfdd9102dd585 Shuosheng Huang 2024-10-24  73  	};
9dfdd9102dd585 Shuosheng Huang 2024-10-24  74  };
9dfdd9102dd585 Shuosheng Huang 2024-10-24  75  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

             reply	other threads:[~2024-10-25 18:12 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-25 18:12 kernel test robot [this message]
  -- strict thread matches above, loose matches on Subject: below --
2024-10-24 17:05 [PATCH 00/13] sunxi: A100/A133 second stage support Cody Eksal
2024-10-24 17:05 ` [PATCH 13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table Cody Eksal
2024-10-24 17:05   ` Cody Eksal
2024-10-25 12:27   ` Andre Przywara
2024-10-25 12:27     ` Andre Przywara
2024-10-28 16:42     ` Cody Eksal
2024-10-28 16:42       ` Cody Eksal

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