* Re: [PATCH 13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table
@ 2024-10-25 18:12 kernel test robot
0 siblings, 0 replies; 7+ messages in thread
From: kernel test robot @ 2024-10-25 18:12 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp
::::::
:::::: Manual check reason: "dtcheck: binding changes may go via different trees"
::::::
BCC: lkp@intel.com
CC: llvm@lists.linux.dev
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20241024170540.2721307-14-masterr3c0rd@epochal.quest>
References: <20241024170540.2721307-14-masterr3c0rd@epochal.quest>
TO: Cody Eksal <masterr3c0rd@epochal.quest>
TO: linux-pm@vger.kernel.org
TO: devicetree@vger.kernel.org
TO: linux-arm-kernel@lists.infradead.org
TO: linux-sunxi@lists.linux.dev
TO: linux-kernel@vger.kernel.org
TO: linux-phy@lists.infradead.org
TO: linux-usb@vger.kernel.org
TO: Rob Herring <robh@kernel.org>
TO: Krzysztof Kozlowski <krzk@kernel.org>
TO: Conor Dooley <conor+dt@kernel.org>
TO: "Chen-Yu Tsai" <wens@csie.org>
TO: Jernej Skrabec <jernej.skrabec@gmail.com>
TO: Samuel Holland <samuel@sholland.org>
CC: Cody Eksal <masterr3c0rd@epochal.quest>
CC: Andre Przywara <andre.przywara@arm.com>
CC: Parthiban <parthiban@linumiz.com>
CC: Yangtao Li <frank@allwinnertech.com>
CC: Florian Fainelli <florian.fainelli@broadcom.com>
CC: Vinod Koul <vkoul@kernel.org>
CC: Linus Walleij <linus.walleij@linaro.org>
CC: Thierry Reding <treding@nvidia.com>
CC: Maxime Ripard <mripard@kernel.org>
CC: "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>
CC: Viresh Kumar <vireshk@kernel.org>
CC: Stephen Boyd <sboyd@kernel.org>
CC: Kishon Vijay Abraham I <kishon@kernel.org>
CC: "Rafael J. Wysocki" <rafael@kernel.org>
CC: Shuosheng Huang <huangshuosheng@allwinnertech.com>
Hi Cody,
kernel test robot noticed the following build warnings:
[auto build test WARNING on c2ee9f594da826bea183ed14f2cc029c719bf4da]
url: https://github.com/intel-lab-lkp/linux/commits/Cody-Eksal/arm64-dts-allwinner-A100-Add-PMU-mode/20241025-012103
base: c2ee9f594da826bea183ed14f2cc029c719bf4da
patch link: https://lore.kernel.org/r/20241024170540.2721307-14-masterr3c0rd%40epochal.quest
patch subject: [PATCH 13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table
:::::: branch date: 25 hours ago
:::::: commit date: 25 hours ago
config: arm64-randconfig-001-20241025 (https://download.01.org/0day-ci/archive/20241026/202410260129.jgcKTWL5-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241026/202410260129.jgcKTWL5-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202410260129.jgcKTWL5-lkp@intel.com/
dtcheck warnings: (new ones prefixed by >>)
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi:102.6-560.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name
>> arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi:11.17-18.5: Warning (unit_address_vs_reg): /cpu-opp-table/opp@408000000: node has a unit name, but no reg or ranges property
arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi:20.17-27.5: Warning (unit_address_vs_reg): /cpu-opp-table/opp@600000000: node has a unit name, but no reg or ranges property
arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi:29.17-36.5: Warning (unit_address_vs_reg): /cpu-opp-table/opp@816000000: node has a unit name, but no reg or ranges property
arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi:38.18-45.5: Warning (unit_address_vs_reg): /cpu-opp-table/opp@1080000000: node has a unit name, but no reg or ranges property
arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi:47.18-54.5: Warning (unit_address_vs_reg): /cpu-opp-table/opp@1200000000: node has a unit name, but no reg or ranges property
arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi:56.18-63.5: Warning (unit_address_vs_reg): /cpu-opp-table/opp@1320000000: node has a unit name, but no reg or ranges property
arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi:65.18-72.5: Warning (unit_address_vs_reg): /cpu-opp-table/opp@1464000000: node has a unit name, but no reg or ranges property
vim +11 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
9dfdd9102dd585 Shuosheng Huang 2024-10-24 4
9dfdd9102dd585 Shuosheng Huang 2024-10-24 5 / {
9dfdd9102dd585 Shuosheng Huang 2024-10-24 6 cpu_opp_table: cpu-opp-table {
9dfdd9102dd585 Shuosheng Huang 2024-10-24 7 compatible = "allwinner,sun50i-a100-operating-points";
9dfdd9102dd585 Shuosheng Huang 2024-10-24 8 nvmem-cells = <&cpu_speed_grade>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 9 opp-shared;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 10
9dfdd9102dd585 Shuosheng Huang 2024-10-24 @11 opp@408000000 {
9dfdd9102dd585 Shuosheng Huang 2024-10-24 12 clock-latency-ns = <244144>; /* 8 32k periods */
9dfdd9102dd585 Shuosheng Huang 2024-10-24 13 opp-hz = /bits/ 64 <408000000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 14
9dfdd9102dd585 Shuosheng Huang 2024-10-24 15 opp-microvolt-speed0 = <900000 900000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 16 opp-microvolt-speed1 = <900000 900000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 17 opp-microvolt-speed2 = <900000 900000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 18 };
9dfdd9102dd585 Shuosheng Huang 2024-10-24 19
9dfdd9102dd585 Shuosheng Huang 2024-10-24 20 opp@600000000 {
9dfdd9102dd585 Shuosheng Huang 2024-10-24 21 clock-latency-ns = <244144>; /* 8 32k periods */
9dfdd9102dd585 Shuosheng Huang 2024-10-24 22 opp-hz = /bits/ 64 <600000000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 23
9dfdd9102dd585 Shuosheng Huang 2024-10-24 24 opp-microvolt-speed0 = <900000 900000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 25 opp-microvolt-speed1 = <900000 900000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 26 opp-microvolt-speed2 = <900000 900000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 27 };
9dfdd9102dd585 Shuosheng Huang 2024-10-24 28
9dfdd9102dd585 Shuosheng Huang 2024-10-24 29 opp@816000000 {
9dfdd9102dd585 Shuosheng Huang 2024-10-24 30 clock-latency-ns = <244144>; /* 8 32k periods */
9dfdd9102dd585 Shuosheng Huang 2024-10-24 31 opp-hz = /bits/ 64 <816000000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 32
9dfdd9102dd585 Shuosheng Huang 2024-10-24 33 opp-microvolt-speed0 = <940000 940000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 34 opp-microvolt-speed1 = <900000 900000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 35 opp-microvolt-speed2 = <900000 900000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 36 };
9dfdd9102dd585 Shuosheng Huang 2024-10-24 37
9dfdd9102dd585 Shuosheng Huang 2024-10-24 38 opp@1080000000 {
9dfdd9102dd585 Shuosheng Huang 2024-10-24 39 clock-latency-ns = <244144>; /* 8 32k periods */
9dfdd9102dd585 Shuosheng Huang 2024-10-24 40 opp-hz = /bits/ 64 <1080000000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 41
9dfdd9102dd585 Shuosheng Huang 2024-10-24 42 opp-microvolt-speed0 = <1020000 1020000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 43 opp-microvolt-speed1 = <980000 980000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 44 opp-microvolt-speed2 = <950000 950000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 45 };
9dfdd9102dd585 Shuosheng Huang 2024-10-24 46
9dfdd9102dd585 Shuosheng Huang 2024-10-24 47 opp@1200000000 {
9dfdd9102dd585 Shuosheng Huang 2024-10-24 48 clock-latency-ns = <244144>; /* 8 32k periods */
9dfdd9102dd585 Shuosheng Huang 2024-10-24 49 opp-hz = /bits/ 64 <1200000000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 50
9dfdd9102dd585 Shuosheng Huang 2024-10-24 51 opp-microvolt-speed0 = <1100000 1100000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 52 opp-microvolt-speed1 = <1020000 1020000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 53 opp-microvolt-speed2 = <1000000 1000000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 54 };
9dfdd9102dd585 Shuosheng Huang 2024-10-24 55
9dfdd9102dd585 Shuosheng Huang 2024-10-24 56 opp@1320000000 {
9dfdd9102dd585 Shuosheng Huang 2024-10-24 57 clock-latency-ns = <244144>; /* 8 32k periods */
9dfdd9102dd585 Shuosheng Huang 2024-10-24 58 opp-hz = /bits/ 64 <1320000000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 59
9dfdd9102dd585 Shuosheng Huang 2024-10-24 60 opp-microvolt-speed0 = <1160000 1160000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 61 opp-microvolt-speed1 = <1060000 1060000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 62 opp-microvolt-speed2 = <1030000 1030000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 63 };
9dfdd9102dd585 Shuosheng Huang 2024-10-24 64
9dfdd9102dd585 Shuosheng Huang 2024-10-24 65 opp@1464000000 {
9dfdd9102dd585 Shuosheng Huang 2024-10-24 66 clock-latency-ns = <244144>; /* 8 32k periods */
9dfdd9102dd585 Shuosheng Huang 2024-10-24 67 opp-hz = /bits/ 64 <1464000000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 68
9dfdd9102dd585 Shuosheng Huang 2024-10-24 69 opp-microvolt-speed0 = <1180000 1180000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 70 opp-microvolt-speed1 = <1180000 1180000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 71 opp-microvolt-speed2 = <1130000 1130000 1200000>;
9dfdd9102dd585 Shuosheng Huang 2024-10-24 72 };
9dfdd9102dd585 Shuosheng Huang 2024-10-24 73 };
9dfdd9102dd585 Shuosheng Huang 2024-10-24 74 };
9dfdd9102dd585 Shuosheng Huang 2024-10-24 75
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 00/13] sunxi: A100/A133 second stage support
@ 2024-10-24 17:05 Cody Eksal
2024-10-24 17:05 ` Cody Eksal
0 siblings, 1 reply; 7+ messages in thread
From: Cody Eksal @ 2024-10-24 17:05 UTC (permalink / raw)
To: linux-pm, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-phy, linux-usb
Cc: Cody Eksal, Andre Przywara, Parthiban, Yangtao Li,
Florian Fainelli, Vinod Koul, Linus Walleij, Thierry Reding,
Krzysztof Kozlowski, Chen-Yu Tsai, Maxime Ripard,
Greg Kroah-Hartman, Yangtao Li, Viresh Kumar, Nishanth Menon,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jernej Skrabec, Samuel Holland, Kishon Vijay Abraham I,
Rafael J. Wysocki
Hello! This is my first submission, so please be gentle :)
Back in 2020, two Allwinner employees, Yangtao Li and Shuosheng Huang, each
submitted a patch series for the A100 series of SoCs; [1] intended to add
support for the watchdog, ARM PMU, DMA, USB, and (e)MMC controller, and [2]
implemented DVFS support. Some patches from the first series landed, but
the rest were seemingly abandoned.
Although references to the A100 have been removed by Allwinner, it is
believed that the A133 and A133 Plus, which are still available, are simply
better binned variants of the A100; no other differences have been noted
thus far, and the drivers for the A100 work on the A133 without any
additional modifications. There has been a resurgence of interest in the
A133; patches to allow mainline U-Boot to run on these devices are
currently in progress.
I have rebased the patches that failed to land, applying the feedback
provided by maintainers at the time. Some DT binding patches were added, as
there were a few cases where compatibles were used without being
documented. Minor reworks were necessary to apply certain patches, as the
drivers they modified have matured over time.
Patches 1 and 2 add PMU and watchdog nodes to the device tree. This is
followed by patches 3-8, which implement support for the USB host and OTG
peripherals. Patches 9 and 10 add MMC nodes, rounding out what originally
made up the first patch series; support for these already exists from
earlier patches. Patches 11-13 finish the job of the second original
series and this series, implementing OPP and enabling DVFS on these SoCs.
This series is also available on GitHub [3].
A sincere thanks to Andre for encouraging me to submit these patches,
Parthiban for testing this tree on his board, and to the linux-sunxi
community and its resources for pointing me to these abandoned series in
the first place [4].
[1] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=380887&archive=both&state=*
[2] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=396055&archive=both&state=*
[3] https://github.com/BrokenR3C0RD/linux-a100/compare/c2ee9f59..allwinner-a100
[4] https://linux-sunxi.org/Linux_mainlining_effort#Work_In_Progress
Cody Eksal (4):
dt-bindings: phy: sun50i-a64: add a100 compatible
dt-bindings: usb: Add A100 compatible string
dt-bindings: usb: sunxi-musb: Add A100 compatible string
dt-bindings: opp: h6: Add A100 operating points
Shuosheng Huang (2):
cpufreq: sun50i: add a100 cpufreq support
arm64: dts: allwinner: a100: Add CPU Operating Performance Points
table
Yangtao Li (7):
arm64: dts: allwinner: A100: Add PMU mode
arm64: dts: allwinner: a100: add watchdog node
phy: sun4i-usb: add support for A100 USB PHY
arm64: dts: allwinner: a100: add usb related nodes
arm64: allwinner: A100: enable EHCI, OHCI and USB PHY nodes in Perf1
arm64: allwinner: a100: Add MMC related nodes
arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node
.../allwinner,sun50i-h6-operating-points.yaml | 1 +
.../phy/allwinner,sun50i-a64-usb-phy.yaml | 1 +
.../usb/allwinner,sun4i-a10-musb.yaml | 1 +
.../devicetree/bindings/usb/generic-ehci.yaml | 1 +
.../devicetree/bindings/usb/generic-ohci.yaml | 1 +
.../allwinner/sun50i-a100-allwinner-perf1.dts | 59 ++++++
.../dts/allwinner/sun50i-a100-cpu-opp.dtsi | 90 ++++++++
.../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 193 +++++++++++++++++-
drivers/cpufreq/sun50i-cpufreq-nvmem.c | 28 +++
drivers/phy/allwinner/phy-sun4i-usb.c | 11 +
10 files changed, 383 insertions(+), 3 deletions(-)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
base-commit: c2ee9f594da826bea183ed14f2cc029c719bf4da
--
2.47.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table
2024-10-24 17:05 [PATCH 00/13] sunxi: A100/A133 second stage support Cody Eksal
@ 2024-10-24 17:05 ` Cody Eksal
0 siblings, 0 replies; 7+ messages in thread
From: Cody Eksal @ 2024-10-24 17:05 UTC (permalink / raw)
To: linux-pm, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-phy, linux-usb, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland
Cc: Cody Eksal, Andre Przywara, Parthiban, Yangtao Li,
Florian Fainelli, Vinod Koul, Linus Walleij, Thierry Reding,
Krzysztof Kozlowski, Maxime Ripard, Greg Kroah-Hartman,
Yangtao Li, Viresh Kumar, Nishanth Menon, Stephen Boyd,
Kishon Vijay Abraham I, Rafael J. Wysocki, Shuosheng Huang
From: Shuosheng Huang <huangshuosheng@allwinnertech.com>
Add an Operating Performance Points table for the CPU cores to
enable Dynamic Voltage & Frequency Scaling on the A100.
Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
[masterr3c0rd@epochal.quest: fix typos in -cpu-opp, use compatible]
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
.../allwinner/sun50i-a100-allwinner-perf1.dts | 5 ++
.../dts/allwinner/sun50i-a100-cpu-opp.dtsi | 90 +++++++++++++++++++
.../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 8 ++
3 files changed, 103 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
index 29e9d24da8b6..99b1b2f7b92a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "sun50i-a100.dtsi"
+#include "sun50i-a100-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
@@ -67,6 +68,10 @@ &usb_otg {
status = "okay";
};
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
&pio {
vcc-pb-supply = <®_dcdc1>;
vcc-pc-supply = <®_eldo1>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
new file mode 100644
index 000000000000..eeb8d20f3fb4
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
+// Copyright (c) 2020 ShuoSheng Huang <huangshuosheng@allwinnertech.com>
+
+/ {
+ cpu_opp_table: cpu-opp-table {
+ compatible = "allwinner,sun50i-a100-operating-points";
+ nvmem-cells = <&cpu_speed_grade>;
+ opp-shared;
+
+ opp@408000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <408000000>;
+
+ opp-microvolt-speed0 = <900000 900000 1200000>;
+ opp-microvolt-speed1 = <900000 900000 1200000>;
+ opp-microvolt-speed2 = <900000 900000 1200000>;
+ };
+
+ opp@600000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <600000000>;
+
+ opp-microvolt-speed0 = <900000 900000 1200000>;
+ opp-microvolt-speed1 = <900000 900000 1200000>;
+ opp-microvolt-speed2 = <900000 900000 1200000>;
+ };
+
+ opp@816000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <816000000>;
+
+ opp-microvolt-speed0 = <940000 940000 1200000>;
+ opp-microvolt-speed1 = <900000 900000 1200000>;
+ opp-microvolt-speed2 = <900000 900000 1200000>;
+ };
+
+ opp@1080000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1080000000>;
+
+ opp-microvolt-speed0 = <1020000 1020000 1200000>;
+ opp-microvolt-speed1 = <980000 980000 1200000>;
+ opp-microvolt-speed2 = <950000 950000 1200000>;
+ };
+
+ opp@1200000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1200000000>;
+
+ opp-microvolt-speed0 = <1100000 1100000 1200000>;
+ opp-microvolt-speed1 = <1020000 1020000 1200000>;
+ opp-microvolt-speed2 = <1000000 1000000 1200000>;
+ };
+
+ opp@1320000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1320000000>;
+
+ opp-microvolt-speed0 = <1160000 1160000 1200000>;
+ opp-microvolt-speed1 = <1060000 1060000 1200000>;
+ opp-microvolt-speed2 = <1030000 1030000 1200000>;
+ };
+
+ opp@1464000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1464000000>;
+
+ opp-microvolt-speed0 = <1180000 1180000 1200000>;
+ opp-microvolt-speed1 = <1180000 1180000 1200000>;
+ opp-microvolt-speed2 = <1130000 1130000 1200000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index 6dca766ea222..747a0292ef98 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -23,6 +23,7 @@ cpu0: cpu@0 {
device_type = "cpu";
reg = <0x0>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
};
cpu1: cpu@1 {
@@ -30,6 +31,7 @@ cpu1: cpu@1 {
device_type = "cpu";
reg = <0x1>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
};
cpu2: cpu@2 {
@@ -37,6 +39,7 @@ cpu2: cpu@2 {
device_type = "cpu";
reg = <0x2>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
};
cpu3: cpu@3 {
@@ -44,6 +47,7 @@ cpu3: cpu@3 {
device_type = "cpu";
reg = <0x3>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
};
};
@@ -142,6 +146,10 @@ efuse@3006000 {
ths_calibration: calib@14 {
reg = <0x14 8>;
};
+
+ cpu_speed_grade: cpu-speed-grade@1c {
+ reg = <0x1c 0x2>;
+ };
};
watchdog@30090a0 {
--
2.47.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table
@ 2024-10-24 17:05 ` Cody Eksal
0 siblings, 0 replies; 7+ messages in thread
From: Cody Eksal @ 2024-10-24 17:05 UTC (permalink / raw)
To: linux-pm, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-phy, linux-usb, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland
Cc: Cody Eksal, Andre Przywara, Parthiban, Yangtao Li,
Florian Fainelli, Vinod Koul, Linus Walleij, Thierry Reding,
Krzysztof Kozlowski, Maxime Ripard, Greg Kroah-Hartman,
Yangtao Li, Viresh Kumar, Nishanth Menon, Stephen Boyd,
Kishon Vijay Abraham I, Rafael J. Wysocki, Shuosheng Huang
From: Shuosheng Huang <huangshuosheng@allwinnertech.com>
Add an Operating Performance Points table for the CPU cores to
enable Dynamic Voltage & Frequency Scaling on the A100.
Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
[masterr3c0rd@epochal.quest: fix typos in -cpu-opp, use compatible]
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
.../allwinner/sun50i-a100-allwinner-perf1.dts | 5 ++
.../dts/allwinner/sun50i-a100-cpu-opp.dtsi | 90 +++++++++++++++++++
.../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 8 ++
3 files changed, 103 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
index 29e9d24da8b6..99b1b2f7b92a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "sun50i-a100.dtsi"
+#include "sun50i-a100-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
@@ -67,6 +68,10 @@ &usb_otg {
status = "okay";
};
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
&pio {
vcc-pb-supply = <®_dcdc1>;
vcc-pc-supply = <®_eldo1>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
new file mode 100644
index 000000000000..eeb8d20f3fb4
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
+// Copyright (c) 2020 ShuoSheng Huang <huangshuosheng@allwinnertech.com>
+
+/ {
+ cpu_opp_table: cpu-opp-table {
+ compatible = "allwinner,sun50i-a100-operating-points";
+ nvmem-cells = <&cpu_speed_grade>;
+ opp-shared;
+
+ opp@408000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <408000000>;
+
+ opp-microvolt-speed0 = <900000 900000 1200000>;
+ opp-microvolt-speed1 = <900000 900000 1200000>;
+ opp-microvolt-speed2 = <900000 900000 1200000>;
+ };
+
+ opp@600000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <600000000>;
+
+ opp-microvolt-speed0 = <900000 900000 1200000>;
+ opp-microvolt-speed1 = <900000 900000 1200000>;
+ opp-microvolt-speed2 = <900000 900000 1200000>;
+ };
+
+ opp@816000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <816000000>;
+
+ opp-microvolt-speed0 = <940000 940000 1200000>;
+ opp-microvolt-speed1 = <900000 900000 1200000>;
+ opp-microvolt-speed2 = <900000 900000 1200000>;
+ };
+
+ opp@1080000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1080000000>;
+
+ opp-microvolt-speed0 = <1020000 1020000 1200000>;
+ opp-microvolt-speed1 = <980000 980000 1200000>;
+ opp-microvolt-speed2 = <950000 950000 1200000>;
+ };
+
+ opp@1200000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1200000000>;
+
+ opp-microvolt-speed0 = <1100000 1100000 1200000>;
+ opp-microvolt-speed1 = <1020000 1020000 1200000>;
+ opp-microvolt-speed2 = <1000000 1000000 1200000>;
+ };
+
+ opp@1320000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1320000000>;
+
+ opp-microvolt-speed0 = <1160000 1160000 1200000>;
+ opp-microvolt-speed1 = <1060000 1060000 1200000>;
+ opp-microvolt-speed2 = <1030000 1030000 1200000>;
+ };
+
+ opp@1464000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1464000000>;
+
+ opp-microvolt-speed0 = <1180000 1180000 1200000>;
+ opp-microvolt-speed1 = <1180000 1180000 1200000>;
+ opp-microvolt-speed2 = <1130000 1130000 1200000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index 6dca766ea222..747a0292ef98 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -23,6 +23,7 @@ cpu0: cpu@0 {
device_type = "cpu";
reg = <0x0>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
};
cpu1: cpu@1 {
@@ -30,6 +31,7 @@ cpu1: cpu@1 {
device_type = "cpu";
reg = <0x1>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
};
cpu2: cpu@2 {
@@ -37,6 +39,7 @@ cpu2: cpu@2 {
device_type = "cpu";
reg = <0x2>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
};
cpu3: cpu@3 {
@@ -44,6 +47,7 @@ cpu3: cpu@3 {
device_type = "cpu";
reg = <0x3>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
};
};
@@ -142,6 +146,10 @@ efuse@3006000 {
ths_calibration: calib@14 {
reg = <0x14 8>;
};
+
+ cpu_speed_grade: cpu-speed-grade@1c {
+ reg = <0x1c 0x2>;
+ };
};
watchdog@30090a0 {
--
2.47.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH 13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table
2024-10-24 17:05 ` Cody Eksal
@ 2024-10-25 12:27 ` Andre Przywara
-1 siblings, 0 replies; 7+ messages in thread
From: Andre Przywara @ 2024-10-25 12:27 UTC (permalink / raw)
To: Cody Eksal
Cc: linux-pm, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-phy, linux-usb, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
Parthiban, Yangtao Li, Florian Fainelli, Vinod Koul,
Linus Walleij, Thierry Reding, Krzysztof Kozlowski, Maxime Ripard,
Greg Kroah-Hartman, Yangtao Li, Viresh Kumar, Nishanth Menon,
Stephen Boyd, Kishon Vijay Abraham I, Rafael J. Wysocki,
Shuosheng Huang
On Thu, 24 Oct 2024 14:05:31 -0300
Cody Eksal <masterr3c0rd@epochal.quest> wrote:
> From: Shuosheng Huang <huangshuosheng@allwinnertech.com>
>
> Add an Operating Performance Points table for the CPU cores to
> enable Dynamic Voltage & Frequency Scaling on the A100.
>
> Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> [masterr3c0rd@epochal.quest: fix typos in -cpu-opp, use compatible]
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> ---
> .../allwinner/sun50i-a100-allwinner-perf1.dts | 5 ++
> .../dts/allwinner/sun50i-a100-cpu-opp.dtsi | 90 +++++++++++++++++++
> .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 8 ++
> 3 files changed, 103 insertions(+)
> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> index 29e9d24da8b6..99b1b2f7b92a 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> @@ -6,6 +6,7 @@
> /dts-v1/;
>
> #include "sun50i-a100.dtsi"
> +#include "sun50i-a100-cpu-opp.dtsi"
>
> #include <dt-bindings/gpio/gpio.h>
>
> @@ -67,6 +68,10 @@ &usb_otg {
> status = "okay";
> };
>
> +&cpu0 {
> + cpu-supply = <®_dcdc2>;
> +};
> +
> &pio {
> vcc-pb-supply = <®_dcdc1>;
> vcc-pc-supply = <®_eldo1>;
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
> new file mode 100644
> index 000000000000..eeb8d20f3fb4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
> @@ -0,0 +1,90 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
> +// Copyright (c) 2020 ShuoSheng Huang <huangshuosheng@allwinnertech.com>
> +
> +/ {
> + cpu_opp_table: cpu-opp-table {
> + compatible = "allwinner,sun50i-a100-operating-points";
> + nvmem-cells = <&cpu_speed_grade>;
> + opp-shared;
> +
> + opp@408000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <408000000>;
> +
> + opp-microvolt-speed0 = <900000 900000 1200000>;
> + opp-microvolt-speed1 = <900000 900000 1200000>;
> + opp-microvolt-speed2 = <900000 900000 1200000>;
Is there actually an advantage when using the three cells version?
I wonder if we should go with just the target voltage (the first cell
here), as done for the H616.
Apart from that it looks fine to me.
Cheers,
Andre.
> + };
> +
> + opp@600000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <600000000>;
> +
> + opp-microvolt-speed0 = <900000 900000 1200000>;
> + opp-microvolt-speed1 = <900000 900000 1200000>;
> + opp-microvolt-speed2 = <900000 900000 1200000>;
> + };
> +
> + opp@816000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <816000000>;
> +
> + opp-microvolt-speed0 = <940000 940000 1200000>;
> + opp-microvolt-speed1 = <900000 900000 1200000>;
> + opp-microvolt-speed2 = <900000 900000 1200000>;
> + };
> +
> + opp@1080000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <1080000000>;
> +
> + opp-microvolt-speed0 = <1020000 1020000 1200000>;
> + opp-microvolt-speed1 = <980000 980000 1200000>;
> + opp-microvolt-speed2 = <950000 950000 1200000>;
> + };
> +
> + opp@1200000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <1200000000>;
> +
> + opp-microvolt-speed0 = <1100000 1100000 1200000>;
> + opp-microvolt-speed1 = <1020000 1020000 1200000>;
> + opp-microvolt-speed2 = <1000000 1000000 1200000>;
> + };
> +
> + opp@1320000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <1320000000>;
> +
> + opp-microvolt-speed0 = <1160000 1160000 1200000>;
> + opp-microvolt-speed1 = <1060000 1060000 1200000>;
> + opp-microvolt-speed2 = <1030000 1030000 1200000>;
> + };
> +
> + opp@1464000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <1464000000>;
> +
> + opp-microvolt-speed0 = <1180000 1180000 1200000>;
> + opp-microvolt-speed1 = <1180000 1180000 1200000>;
> + opp-microvolt-speed2 = <1130000 1130000 1200000>;
> + };
> + };
> +};
> +
> +&cpu0 {
> + operating-points-v2 = <&cpu_opp_table>;
> +};
> +
> +&cpu1 {
> + operating-points-v2 = <&cpu_opp_table>;
> +};
> +
> +&cpu2 {
> + operating-points-v2 = <&cpu_opp_table>;
> +};
> +
> +&cpu3 {
> + operating-points-v2 = <&cpu_opp_table>;
> +};
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> index 6dca766ea222..747a0292ef98 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> @@ -23,6 +23,7 @@ cpu0: cpu@0 {
> device_type = "cpu";
> reg = <0x0>;
> enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> };
>
> cpu1: cpu@1 {
> @@ -30,6 +31,7 @@ cpu1: cpu@1 {
> device_type = "cpu";
> reg = <0x1>;
> enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> };
>
> cpu2: cpu@2 {
> @@ -37,6 +39,7 @@ cpu2: cpu@2 {
> device_type = "cpu";
> reg = <0x2>;
> enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> };
>
> cpu3: cpu@3 {
> @@ -44,6 +47,7 @@ cpu3: cpu@3 {
> device_type = "cpu";
> reg = <0x3>;
> enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> };
> };
>
> @@ -142,6 +146,10 @@ efuse@3006000 {
> ths_calibration: calib@14 {
> reg = <0x14 8>;
> };
> +
> + cpu_speed_grade: cpu-speed-grade@1c {
> + reg = <0x1c 0x2>;
> + };
> };
>
> watchdog@30090a0 {
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table
@ 2024-10-25 12:27 ` Andre Przywara
0 siblings, 0 replies; 7+ messages in thread
From: Andre Przywara @ 2024-10-25 12:27 UTC (permalink / raw)
To: Cody Eksal
Cc: linux-pm, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-phy, linux-usb, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
Parthiban, Yangtao Li, Florian Fainelli, Vinod Koul,
Linus Walleij, Thierry Reding, Krzysztof Kozlowski, Maxime Ripard,
Greg Kroah-Hartman, Yangtao Li, Viresh Kumar, Nishanth Menon,
Stephen Boyd, Kishon Vijay Abraham I, Rafael J. Wysocki,
Shuosheng Huang
On Thu, 24 Oct 2024 14:05:31 -0300
Cody Eksal <masterr3c0rd@epochal.quest> wrote:
> From: Shuosheng Huang <huangshuosheng@allwinnertech.com>
>
> Add an Operating Performance Points table for the CPU cores to
> enable Dynamic Voltage & Frequency Scaling on the A100.
>
> Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> [masterr3c0rd@epochal.quest: fix typos in -cpu-opp, use compatible]
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> ---
> .../allwinner/sun50i-a100-allwinner-perf1.dts | 5 ++
> .../dts/allwinner/sun50i-a100-cpu-opp.dtsi | 90 +++++++++++++++++++
> .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 8 ++
> 3 files changed, 103 insertions(+)
> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> index 29e9d24da8b6..99b1b2f7b92a 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> @@ -6,6 +6,7 @@
> /dts-v1/;
>
> #include "sun50i-a100.dtsi"
> +#include "sun50i-a100-cpu-opp.dtsi"
>
> #include <dt-bindings/gpio/gpio.h>
>
> @@ -67,6 +68,10 @@ &usb_otg {
> status = "okay";
> };
>
> +&cpu0 {
> + cpu-supply = <®_dcdc2>;
> +};
> +
> &pio {
> vcc-pb-supply = <®_dcdc1>;
> vcc-pc-supply = <®_eldo1>;
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
> new file mode 100644
> index 000000000000..eeb8d20f3fb4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
> @@ -0,0 +1,90 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
> +// Copyright (c) 2020 ShuoSheng Huang <huangshuosheng@allwinnertech.com>
> +
> +/ {
> + cpu_opp_table: cpu-opp-table {
> + compatible = "allwinner,sun50i-a100-operating-points";
> + nvmem-cells = <&cpu_speed_grade>;
> + opp-shared;
> +
> + opp@408000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <408000000>;
> +
> + opp-microvolt-speed0 = <900000 900000 1200000>;
> + opp-microvolt-speed1 = <900000 900000 1200000>;
> + opp-microvolt-speed2 = <900000 900000 1200000>;
Is there actually an advantage when using the three cells version?
I wonder if we should go with just the target voltage (the first cell
here), as done for the H616.
Apart from that it looks fine to me.
Cheers,
Andre.
> + };
> +
> + opp@600000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <600000000>;
> +
> + opp-microvolt-speed0 = <900000 900000 1200000>;
> + opp-microvolt-speed1 = <900000 900000 1200000>;
> + opp-microvolt-speed2 = <900000 900000 1200000>;
> + };
> +
> + opp@816000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <816000000>;
> +
> + opp-microvolt-speed0 = <940000 940000 1200000>;
> + opp-microvolt-speed1 = <900000 900000 1200000>;
> + opp-microvolt-speed2 = <900000 900000 1200000>;
> + };
> +
> + opp@1080000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <1080000000>;
> +
> + opp-microvolt-speed0 = <1020000 1020000 1200000>;
> + opp-microvolt-speed1 = <980000 980000 1200000>;
> + opp-microvolt-speed2 = <950000 950000 1200000>;
> + };
> +
> + opp@1200000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <1200000000>;
> +
> + opp-microvolt-speed0 = <1100000 1100000 1200000>;
> + opp-microvolt-speed1 = <1020000 1020000 1200000>;
> + opp-microvolt-speed2 = <1000000 1000000 1200000>;
> + };
> +
> + opp@1320000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <1320000000>;
> +
> + opp-microvolt-speed0 = <1160000 1160000 1200000>;
> + opp-microvolt-speed1 = <1060000 1060000 1200000>;
> + opp-microvolt-speed2 = <1030000 1030000 1200000>;
> + };
> +
> + opp@1464000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <1464000000>;
> +
> + opp-microvolt-speed0 = <1180000 1180000 1200000>;
> + opp-microvolt-speed1 = <1180000 1180000 1200000>;
> + opp-microvolt-speed2 = <1130000 1130000 1200000>;
> + };
> + };
> +};
> +
> +&cpu0 {
> + operating-points-v2 = <&cpu_opp_table>;
> +};
> +
> +&cpu1 {
> + operating-points-v2 = <&cpu_opp_table>;
> +};
> +
> +&cpu2 {
> + operating-points-v2 = <&cpu_opp_table>;
> +};
> +
> +&cpu3 {
> + operating-points-v2 = <&cpu_opp_table>;
> +};
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> index 6dca766ea222..747a0292ef98 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> @@ -23,6 +23,7 @@ cpu0: cpu@0 {
> device_type = "cpu";
> reg = <0x0>;
> enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> };
>
> cpu1: cpu@1 {
> @@ -30,6 +31,7 @@ cpu1: cpu@1 {
> device_type = "cpu";
> reg = <0x1>;
> enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> };
>
> cpu2: cpu@2 {
> @@ -37,6 +39,7 @@ cpu2: cpu@2 {
> device_type = "cpu";
> reg = <0x2>;
> enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> };
>
> cpu3: cpu@3 {
> @@ -44,6 +47,7 @@ cpu3: cpu@3 {
> device_type = "cpu";
> reg = <0x3>;
> enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> };
> };
>
> @@ -142,6 +146,10 @@ efuse@3006000 {
> ths_calibration: calib@14 {
> reg = <0x14 8>;
> };
> +
> + cpu_speed_grade: cpu-speed-grade@1c {
> + reg = <0x1c 0x2>;
> + };
> };
>
> watchdog@30090a0 {
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table
2024-10-25 12:27 ` Andre Przywara
@ 2024-10-28 16:42 ` Cody Eksal
-1 siblings, 0 replies; 7+ messages in thread
From: Cody Eksal @ 2024-10-28 16:42 UTC (permalink / raw)
To: Andre Przywara
Cc: linux-pm, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-phy, linux-usb, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
Parthiban, Yangtao Li, Florian Fainelli, Vinod Koul,
Linus Walleij, Thierry Reding, Krzysztof Kozlowski, Maxime Ripard,
Greg Kroah-Hartman, Yangtao Li, Viresh Kumar, Nishanth Menon,
Stephen Boyd, Kishon Vijay Abraham I, Rafael J. Wysocki,
Shuosheng Huang
On 2024/10/25 9:27 am, Andre Przywara wrote:
> On Thu, 24 Oct 2024 14:05:31 -0300
> Cody Eksal <masterr3c0rd@epochal.quest> wrote:
>
>> From: Shuosheng Huang <huangshuosheng@allwinnertech.com>
>>
>> Add an Operating Performance Points table for the CPU cores to
>> enable Dynamic Voltage & Frequency Scaling on the A100.
>>
>> Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
>> [masterr3c0rd@epochal.quest: fix typos in -cpu-opp, use compatible]
>> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
>> ---
>> .../allwinner/sun50i-a100-allwinner-perf1.dts | 5 ++
>> .../dts/allwinner/sun50i-a100-cpu-opp.dtsi | 90
>> +++++++++++++++++++
>> .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 8 ++
>> 3 files changed, 103 insertions(+)
>> create mode 100644
>> arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>>
>> diff --git
>> a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
>> b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
>> index 29e9d24da8b6..99b1b2f7b92a 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
>> @@ -6,6 +6,7 @@
>> /dts-v1/;
>>
>> #include "sun50i-a100.dtsi"
>> +#include "sun50i-a100-cpu-opp.dtsi"
>>
>> #include <dt-bindings/gpio/gpio.h>
>>
>> @@ -67,6 +68,10 @@ &usb_otg {
>> status = "okay";
>> };
>>
>> +&cpu0 {
>> + cpu-supply = <®_dcdc2>;
>> +};
>> +
>> &pio {
>> vcc-pb-supply = <®_dcdc1>;
>> vcc-pc-supply = <®_eldo1>;
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>> b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>> new file mode 100644
>> index 000000000000..eeb8d20f3fb4
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>> @@ -0,0 +1,90 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +// Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
>> +// Copyright (c) 2020 ShuoSheng Huang
>> <huangshuosheng@allwinnertech.com>
>> +
>> +/ {
>> + cpu_opp_table: cpu-opp-table {
>> + compatible = "allwinner,sun50i-a100-operating-points";
>> + nvmem-cells = <&cpu_speed_grade>;
>> + opp-shared;
>> +
>> + opp@408000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <408000000>;
>> +
>> + opp-microvolt-speed0 = <900000 900000 1200000>;
>> + opp-microvolt-speed1 = <900000 900000 1200000>;
>> + opp-microvolt-speed2 = <900000 900000 1200000>;
>
> Is there actually an advantage when using the three cells version?
> I wonder if we should go with just the target voltage (the first cell
> here), as done for the H616.
It probably makes sense to follow precedent; I've updated V2 to make
these single-cell.
> Apart from that it looks fine to me.
I did get a comment from Rob's bot that picked up some issues with the
namings of these nodes; I've updated that as well.
Thanks!
- Cody
> Cheers,
> Andre.
>
>> + };
>> +
>> + opp@600000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <600000000>;
>> +
>> + opp-microvolt-speed0 = <900000 900000 1200000>;
>> + opp-microvolt-speed1 = <900000 900000 1200000>;
>> + opp-microvolt-speed2 = <900000 900000 1200000>;
>> + };
>> +
>> + opp@816000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <816000000>;
>> +
>> + opp-microvolt-speed0 = <940000 940000 1200000>;
>> + opp-microvolt-speed1 = <900000 900000 1200000>;
>> + opp-microvolt-speed2 = <900000 900000 1200000>;
>> + };
>> +
>> + opp@1080000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <1080000000>;
>> +
>> + opp-microvolt-speed0 = <1020000 1020000 1200000>;
>> + opp-microvolt-speed1 = <980000 980000 1200000>;
>> + opp-microvolt-speed2 = <950000 950000 1200000>;
>> + };
>> +
>> + opp@1200000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <1200000000>;
>> +
>> + opp-microvolt-speed0 = <1100000 1100000 1200000>;
>> + opp-microvolt-speed1 = <1020000 1020000 1200000>;
>> + opp-microvolt-speed2 = <1000000 1000000 1200000>;
>> + };
>> +
>> + opp@1320000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <1320000000>;
>> +
>> + opp-microvolt-speed0 = <1160000 1160000 1200000>;
>> + opp-microvolt-speed1 = <1060000 1060000 1200000>;
>> + opp-microvolt-speed2 = <1030000 1030000 1200000>;
>> + };
>> +
>> + opp@1464000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <1464000000>;
>> +
>> + opp-microvolt-speed0 = <1180000 1180000 1200000>;
>> + opp-microvolt-speed1 = <1180000 1180000 1200000>;
>> + opp-microvolt-speed2 = <1130000 1130000 1200000>;
>> + };
>> + };
>> +};
>> +
>> +&cpu0 {
>> + operating-points-v2 = <&cpu_opp_table>;
>> +};
>> +
>> +&cpu1 {
>> + operating-points-v2 = <&cpu_opp_table>;
>> +};
>> +
>> +&cpu2 {
>> + operating-points-v2 = <&cpu_opp_table>;
>> +};
>> +
>> +&cpu3 {
>> + operating-points-v2 = <&cpu_opp_table>;
>> +};
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> index 6dca766ea222..747a0292ef98 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> @@ -23,6 +23,7 @@ cpu0: cpu@0 {
>> device_type = "cpu";
>> reg = <0x0>;
>> enable-method = "psci";
>> + clocks = <&ccu CLK_CPUX>;
>> };
>>
>> cpu1: cpu@1 {
>> @@ -30,6 +31,7 @@ cpu1: cpu@1 {
>> device_type = "cpu";
>> reg = <0x1>;
>> enable-method = "psci";
>> + clocks = <&ccu CLK_CPUX>;
>> };
>>
>> cpu2: cpu@2 {
>> @@ -37,6 +39,7 @@ cpu2: cpu@2 {
>> device_type = "cpu";
>> reg = <0x2>;
>> enable-method = "psci";
>> + clocks = <&ccu CLK_CPUX>;
>> };
>>
>> cpu3: cpu@3 {
>> @@ -44,6 +47,7 @@ cpu3: cpu@3 {
>> device_type = "cpu";
>> reg = <0x3>;
>> enable-method = "psci";
>> + clocks = <&ccu CLK_CPUX>;
>> };
>> };
>>
>> @@ -142,6 +146,10 @@ efuse@3006000 {
>> ths_calibration: calib@14 {
>> reg = <0x14 8>;
>> };
>> +
>> + cpu_speed_grade: cpu-speed-grade@1c {
>> + reg = <0x1c 0x2>;
>> + };
>> };
>>
>> watchdog@30090a0 {
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table
@ 2024-10-28 16:42 ` Cody Eksal
0 siblings, 0 replies; 7+ messages in thread
From: Cody Eksal @ 2024-10-28 16:42 UTC (permalink / raw)
To: Andre Przywara
Cc: linux-pm, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-phy, linux-usb, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
Parthiban, Yangtao Li, Florian Fainelli, Vinod Koul,
Linus Walleij, Thierry Reding, Krzysztof Kozlowski, Maxime Ripard,
Greg Kroah-Hartman, Yangtao Li, Viresh Kumar, Nishanth Menon,
Stephen Boyd, Kishon Vijay Abraham I, Rafael J. Wysocki,
Shuosheng Huang
On 2024/10/25 9:27 am, Andre Przywara wrote:
> On Thu, 24 Oct 2024 14:05:31 -0300
> Cody Eksal <masterr3c0rd@epochal.quest> wrote:
>
>> From: Shuosheng Huang <huangshuosheng@allwinnertech.com>
>>
>> Add an Operating Performance Points table for the CPU cores to
>> enable Dynamic Voltage & Frequency Scaling on the A100.
>>
>> Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
>> [masterr3c0rd@epochal.quest: fix typos in -cpu-opp, use compatible]
>> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
>> ---
>> .../allwinner/sun50i-a100-allwinner-perf1.dts | 5 ++
>> .../dts/allwinner/sun50i-a100-cpu-opp.dtsi | 90
>> +++++++++++++++++++
>> .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 8 ++
>> 3 files changed, 103 insertions(+)
>> create mode 100644
>> arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>>
>> diff --git
>> a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
>> b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
>> index 29e9d24da8b6..99b1b2f7b92a 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
>> @@ -6,6 +6,7 @@
>> /dts-v1/;
>>
>> #include "sun50i-a100.dtsi"
>> +#include "sun50i-a100-cpu-opp.dtsi"
>>
>> #include <dt-bindings/gpio/gpio.h>
>>
>> @@ -67,6 +68,10 @@ &usb_otg {
>> status = "okay";
>> };
>>
>> +&cpu0 {
>> + cpu-supply = <®_dcdc2>;
>> +};
>> +
>> &pio {
>> vcc-pb-supply = <®_dcdc1>;
>> vcc-pc-supply = <®_eldo1>;
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>> b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>> new file mode 100644
>> index 000000000000..eeb8d20f3fb4
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>> @@ -0,0 +1,90 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +// Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
>> +// Copyright (c) 2020 ShuoSheng Huang
>> <huangshuosheng@allwinnertech.com>
>> +
>> +/ {
>> + cpu_opp_table: cpu-opp-table {
>> + compatible = "allwinner,sun50i-a100-operating-points";
>> + nvmem-cells = <&cpu_speed_grade>;
>> + opp-shared;
>> +
>> + opp@408000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <408000000>;
>> +
>> + opp-microvolt-speed0 = <900000 900000 1200000>;
>> + opp-microvolt-speed1 = <900000 900000 1200000>;
>> + opp-microvolt-speed2 = <900000 900000 1200000>;
>
> Is there actually an advantage when using the three cells version?
> I wonder if we should go with just the target voltage (the first cell
> here), as done for the H616.
It probably makes sense to follow precedent; I've updated V2 to make
these single-cell.
> Apart from that it looks fine to me.
I did get a comment from Rob's bot that picked up some issues with the
namings of these nodes; I've updated that as well.
Thanks!
- Cody
> Cheers,
> Andre.
>
>> + };
>> +
>> + opp@600000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <600000000>;
>> +
>> + opp-microvolt-speed0 = <900000 900000 1200000>;
>> + opp-microvolt-speed1 = <900000 900000 1200000>;
>> + opp-microvolt-speed2 = <900000 900000 1200000>;
>> + };
>> +
>> + opp@816000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <816000000>;
>> +
>> + opp-microvolt-speed0 = <940000 940000 1200000>;
>> + opp-microvolt-speed1 = <900000 900000 1200000>;
>> + opp-microvolt-speed2 = <900000 900000 1200000>;
>> + };
>> +
>> + opp@1080000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <1080000000>;
>> +
>> + opp-microvolt-speed0 = <1020000 1020000 1200000>;
>> + opp-microvolt-speed1 = <980000 980000 1200000>;
>> + opp-microvolt-speed2 = <950000 950000 1200000>;
>> + };
>> +
>> + opp@1200000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <1200000000>;
>> +
>> + opp-microvolt-speed0 = <1100000 1100000 1200000>;
>> + opp-microvolt-speed1 = <1020000 1020000 1200000>;
>> + opp-microvolt-speed2 = <1000000 1000000 1200000>;
>> + };
>> +
>> + opp@1320000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <1320000000>;
>> +
>> + opp-microvolt-speed0 = <1160000 1160000 1200000>;
>> + opp-microvolt-speed1 = <1060000 1060000 1200000>;
>> + opp-microvolt-speed2 = <1030000 1030000 1200000>;
>> + };
>> +
>> + opp@1464000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <1464000000>;
>> +
>> + opp-microvolt-speed0 = <1180000 1180000 1200000>;
>> + opp-microvolt-speed1 = <1180000 1180000 1200000>;
>> + opp-microvolt-speed2 = <1130000 1130000 1200000>;
>> + };
>> + };
>> +};
>> +
>> +&cpu0 {
>> + operating-points-v2 = <&cpu_opp_table>;
>> +};
>> +
>> +&cpu1 {
>> + operating-points-v2 = <&cpu_opp_table>;
>> +};
>> +
>> +&cpu2 {
>> + operating-points-v2 = <&cpu_opp_table>;
>> +};
>> +
>> +&cpu3 {
>> + operating-points-v2 = <&cpu_opp_table>;
>> +};
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> index 6dca766ea222..747a0292ef98 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> @@ -23,6 +23,7 @@ cpu0: cpu@0 {
>> device_type = "cpu";
>> reg = <0x0>;
>> enable-method = "psci";
>> + clocks = <&ccu CLK_CPUX>;
>> };
>>
>> cpu1: cpu@1 {
>> @@ -30,6 +31,7 @@ cpu1: cpu@1 {
>> device_type = "cpu";
>> reg = <0x1>;
>> enable-method = "psci";
>> + clocks = <&ccu CLK_CPUX>;
>> };
>>
>> cpu2: cpu@2 {
>> @@ -37,6 +39,7 @@ cpu2: cpu@2 {
>> device_type = "cpu";
>> reg = <0x2>;
>> enable-method = "psci";
>> + clocks = <&ccu CLK_CPUX>;
>> };
>>
>> cpu3: cpu@3 {
>> @@ -44,6 +47,7 @@ cpu3: cpu@3 {
>> device_type = "cpu";
>> reg = <0x3>;
>> enable-method = "psci";
>> + clocks = <&ccu CLK_CPUX>;
>> };
>> };
>>
>> @@ -142,6 +146,10 @@ efuse@3006000 {
>> ths_calibration: calib@14 {
>> reg = <0x14 8>;
>> };
>> +
>> + cpu_speed_grade: cpu-speed-grade@1c {
>> + reg = <0x1c 0x2>;
>> + };
>> };
>>
>> watchdog@30090a0 {
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2024-10-28 17:06 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2024-10-24 17:05 [PATCH 00/13] sunxi: A100/A133 second stage support Cody Eksal
2024-10-24 17:05 ` [PATCH 13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table Cody Eksal
2024-10-24 17:05 ` Cody Eksal
2024-10-25 12:27 ` Andre Przywara
2024-10-25 12:27 ` Andre Przywara
2024-10-28 16:42 ` Cody Eksal
2024-10-28 16:42 ` Cody Eksal
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