From: Hal Feng <hal.feng@starfivetech.com>
To: Leo <ycliang@andestech.com>, Tom Rini <trini@konsulko.com>,
Sumit Garg <sumit.garg@linaro.org>,
Rick Chen <rick@andestech.com>,
Heinrich Schuchardt <xypron.glpk@gmx.de>,
H Bell <dmoo_dv@protonmail.com>, E Shattow <lucent@gmail.com>,
Nam Cao <namcao@linutronix.de>, Bo Gan <ganboing@gmail.com>
Cc: Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Minda Chen <minda.chen@starfivetech.com>,
Hal Feng <hal.feng@starfivetech.com>,
u-boot@lists.denx.de
Subject: [PATCH v2 06/14] clk: starfive: jh7110: Sync clock definitions with upstream dt-bindings
Date: Mon, 28 Oct 2024 09:58:39 +0800 [thread overview]
Message-ID: <20241028015847.42344-7-hal.feng@starfivetech.com> (raw)
In-Reply-To: <20241028015847.42344-1-hal.feng@starfivetech.com>
JH7110 switch to use upstream dt-bindings, so update
the clock definitions in drivers accordingly.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
drivers/clk/starfive/clk-jh7110-pll.c | 6 ++--
drivers/clk/starfive/clk-jh7110.c | 44 +++++++++++++--------------
2 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c
index 6d2bfb3ecb..f8af17227c 100644
--- a/drivers/clk/starfive/clk-jh7110-pll.c
+++ b/drivers/clk/starfive/clk-jh7110-pll.c
@@ -374,13 +374,13 @@ static int jh7110_pll_clk_probe(struct udevice *dev)
if (sysreg == FDT_ADDR_T_NONE)
return -EINVAL;
- clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL0_OUT),
+ clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL0_OUT),
starfive_jh7110_pll("pll0_out", "oscillator", reg,
(void __iomem *)sysreg, &starfive_jh7110_pll0));
- clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL1_OUT),
+ clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL1_OUT),
starfive_jh7110_pll("pll1_out", "oscillator", reg,
(void __iomem *)sysreg, &starfive_jh7110_pll1));
- clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL2_OUT),
+ clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL2_OUT),
starfive_jh7110_pll("pll2_out", "oscillator", reg,
(void __iomem *)sysreg, &starfive_jh7110_pll2));
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c
index 191da75d7b..6387e949d5 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -495,37 +495,37 @@ static int jh7110_stgcrg_init(struct udevice *dev)
{
struct jh7110_clk_priv *priv = dev_get_priv(dev);
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APB),
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_APB),
starfive_clk_gate(priv->reg,
"usb_apb", "apb_bus",
- OFFSET(JH7110_STGCLK_USB_APB)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_UTMI_APB),
+ OFFSET(JH7110_STGCLK_USB0_APB)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_UTMI_APB),
starfive_clk_gate(priv->reg,
"usb_utmi_apb", "apb_bus",
- OFFSET(JH7110_STGCLK_USB_UTMI_APB)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_AXI),
+ OFFSET(JH7110_STGCLK_USB0_UTMI_APB)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_AXI),
starfive_clk_gate(priv->reg,
"usb_axi", "stg_axiahb",
- OFFSET(JH7110_STGCLK_USB_AXI)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_LPM),
+ OFFSET(JH7110_STGCLK_USB0_AXI)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_LPM),
starfive_clk_gate_divider(priv->reg,
"usb_lpm", "oscillator",
- OFFSET(JH7110_STGCLK_USB_LPM), 2));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_STB),
+ OFFSET(JH7110_STGCLK_USB0_LPM), 2));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_STB),
starfive_clk_gate_divider(priv->reg,
"usb_stb", "oscillator",
- OFFSET(JH7110_STGCLK_USB_STB), 3));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APP_125),
+ OFFSET(JH7110_STGCLK_USB0_STB), 3));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_APP_125),
starfive_clk_gate(priv->reg,
"usb_app_125", "usb_125m",
- OFFSET(JH7110_STGCLK_USB_APP_125)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_REFCLK),
+ OFFSET(JH7110_STGCLK_USB0_APP_125)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_REFCLK),
starfive_clk_divider(priv->reg, "usb_refclk", "oscillator",
- OFFSET(JH7110_STGCLK_USB_REFCLK), 2));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI),
+ OFFSET(JH7110_STGCLK_USB0_REFCLK), 2));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI_MST0),
starfive_clk_gate(priv->reg,
"pcie0_axi", "stg_axiahb",
- OFFSET(JH7110_STGCLK_PCIE0_AXI)));
+ OFFSET(JH7110_STGCLK_PCIE0_AXI_MST0)));
clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_APB),
starfive_clk_gate(priv->reg,
"pcie0_apb", "apb_bus",
@@ -534,10 +534,10 @@ static int jh7110_stgcrg_init(struct udevice *dev)
starfive_clk_gate(priv->reg,
"pcie0_tl", "stg_axiahb",
OFFSET(JH7110_STGCLK_PCIE0_TL)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI),
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI_MST0),
starfive_clk_gate(priv->reg,
"pcie1_axi", "stg_axiahb",
- OFFSET(JH7110_STGCLK_PCIE1_AXI)));
+ OFFSET(JH7110_STGCLK_PCIE1_AXI_MST0)));
clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_APB),
starfive_clk_gate(priv->reg,
"pcie1_apb", "apb_bus",
@@ -548,14 +548,14 @@ static int jh7110_stgcrg_init(struct udevice *dev)
OFFSET(JH7110_STGCLK_PCIE1_TL)));
/* Security clocks */
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK),
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_AHB),
starfive_clk_gate(priv->reg,
"sec_ahb", "stg_axiahb",
- OFFSET(JH7110_STGCLK_SEC_HCLK)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB),
+ OFFSET(JH7110_STGCLK_SEC_AHB)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISC_AHB),
starfive_clk_gate(priv->reg,
"sec_misc_ahb", "stg_axiahb",
- OFFSET(JH7110_STGCLK_SEC_MISCAHB)));
+ OFFSET(JH7110_STGCLK_SEC_MISC_AHB)));
return 0;
}
--
2.43.2
next prev parent reply other threads:[~2024-10-28 2:01 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-28 1:58 [PATCH v2 00/14] Support OF_UPSTREAM for StarFive JH7110 Hal Feng
2024-10-28 1:58 ` [PATCH v2 01/14] Makefile: Add OF_UPSTREAM Makefile for RISC-V Hal Feng
2024-10-28 1:58 ` [PATCH v2 02/14] dts: starfive: Switch to using upstream DT Hal Feng
2024-10-28 1:58 ` [PATCH v2 03/14] riscv: dts: jh7110: Drop redundant devicetree files Hal Feng
2024-10-28 1:58 ` [PATCH v2 04/14] dt-bindings: Remove StarFive JH7110 clock and reset definitions Hal Feng
2024-10-28 1:58 ` [PATCH v2 05/14] riscv: dts: jh7110: Make u-boot device trees adapting to upstream DT Hal Feng
2024-10-28 1:58 ` Hal Feng [this message]
2024-10-28 1:58 ` [PATCH v2 07/14] pcie: starfive: Make the driver compatible with " Hal Feng
2024-10-28 1:58 ` [PATCH v2 08/14] riscv: dts: jh7110: Move common code to the new jh7110-common-u-boot.dtsi Hal Feng
2024-10-28 1:58 ` [PATCH v2 09/14] riscv: dts: jh7110: Add u-boot device tree for JH7110 based boards Hal Feng
2024-10-28 3:34 ` E Shattow
2024-10-28 1:58 ` [PATCH v2 10/14] board: starfive: spl: Drop the unneeded DT modification code Hal Feng
2024-10-28 1:58 ` [PATCH v2 11/14] configs: visionfive2: Enable MULTI_DTB_FIT for JH7110 based board DT Hal Feng
2024-10-28 1:58 ` [PATCH v2 12/14] riscv: dts: jh7110: Support multiple DTBs in a Fit image Hal Feng
2024-10-28 1:58 ` [PATCH v2 13/14] board: starfive: spl: Fix the wrong use of CONFIG_IS_ENABLED() Hal Feng
2024-10-28 1:58 ` [PATCH v2 14/14] board: starfive: spl: Support multiple DTBs for JH7110 based boards Hal Feng
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