From: "Krzysztof Wilczyński" <kw@linux.com>
To: Conor Dooley <conor@kernel.org>
Cc: linux-pci@vger.kernel.org,
Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
Rob Herring <robh@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v5 0/2] PCI: microchip: support using either instance 1 or 2
Date: Sat, 2 Nov 2024 20:51:17 +0900 [thread overview]
Message-ID: <20241102115117.GD2260768@rocinante> (raw)
In-Reply-To: <20240814-setback-rumbling-c6393c8f1a91@spud>
Hello,
> The current driver and binding for PolarFire SoC's PCI controller assume
> that the root port instance in use is instance 1. The second reg
> property constitutes the region encompassing both "control" and "bridge"
> registers for both instances. In the driver, a fixed offset is applied to
> find the base addresses for instance 1's "control" and "bridge"
> registers. The BeagleV Fire uses root port instance 2, so something must
> be done so that software can differentiate. This series splits the
> second reg property in two, with dedicated "control" and "bridge"
> entries so that either instance can be used.
Applied to controller/microchip, thank you!
[01/02] PCI: dt-bindings: PCI: microchip,pcie-host: Fix reg properties
https://git.kernel.org/pci/pci/c/ae5ebdb405dd
[02/02] PCI: microchip: Rework reg region handing to support using either instance 1 or 2
https://git.kernel.org/pci/pci/c/e071e6bd9940
Krzysztof
WARNING: multiple messages have this Message-ID (diff)
From: "Krzysztof Wilczyński" <kw@linux.com>
To: Conor Dooley <conor@kernel.org>
Cc: linux-pci@vger.kernel.org,
Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
Rob Herring <robh@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v5 0/2] PCI: microchip: support using either instance 1 or 2
Date: Sat, 2 Nov 2024 20:51:17 +0900 [thread overview]
Message-ID: <20241102115117.GD2260768@rocinante> (raw)
In-Reply-To: <20240814-setback-rumbling-c6393c8f1a91@spud>
Hello,
> The current driver and binding for PolarFire SoC's PCI controller assume
> that the root port instance in use is instance 1. The second reg
> property constitutes the region encompassing both "control" and "bridge"
> registers for both instances. In the driver, a fixed offset is applied to
> find the base addresses for instance 1's "control" and "bridge"
> registers. The BeagleV Fire uses root port instance 2, so something must
> be done so that software can differentiate. This series splits the
> second reg property in two, with dedicated "control" and "bridge"
> entries so that either instance can be used.
Applied to controller/microchip, thank you!
[01/02] PCI: dt-bindings: PCI: microchip,pcie-host: Fix reg properties
https://git.kernel.org/pci/pci/c/ae5ebdb405dd
[02/02] PCI: microchip: Rework reg region handing to support using either instance 1 or 2
https://git.kernel.org/pci/pci/c/e071e6bd9940
Krzysztof
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next prev parent reply other threads:[~2024-11-02 11:51 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-14 8:08 [PATCH v5 0/2] PCI: microchip: support using either instance 1 or 2 Conor Dooley
2024-08-14 8:08 ` Conor Dooley
2024-08-14 8:08 ` [PATCH v5 1/2] dt-bindings: PCI: microchip,pcie-host: fix reg properties Conor Dooley
2024-08-14 8:08 ` Conor Dooley
2024-08-14 8:08 ` [PATCH v5 2/2] PCI: microchip: rework reg region handing to support using either instance 1 or 2 Conor Dooley
2024-08-14 8:08 ` Conor Dooley
2024-11-01 19:51 ` Bjorn Helgaas
2024-11-01 19:51 ` Bjorn Helgaas
2024-11-02 11:54 ` Krzysztof Wilczyński
2024-11-02 11:54 ` Krzysztof Wilczyński
2024-11-04 11:18 ` Conor Dooley
2024-11-04 11:18 ` Conor Dooley
2024-11-05 17:18 ` Bjorn Helgaas
2024-11-05 17:18 ` Bjorn Helgaas
2024-11-06 16:26 ` Conor Dooley
2024-11-06 16:26 ` Conor Dooley
2024-10-24 9:38 ` [PATCH v5 0/2] PCI: microchip: " Conor Dooley
2024-10-24 9:38 ` Conor Dooley
2024-10-24 18:46 ` Bjorn Helgaas
2024-10-24 18:46 ` Bjorn Helgaas
2024-11-02 11:51 ` Krzysztof Wilczyński [this message]
2024-11-02 11:51 ` Krzysztof Wilczyński
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