Re: [Intel-wired-lan] [PATCH v3 iwl-net 2/4] ice: Fix quad registers read on E825

[Simon Horman <horms@kernel.org>]

On Mon, Oct 28, 2024 at 09:45:41PM +0100, Grzegorz Nitka wrote:
> From: Karol Kolacinski <karol.kolacinski@intel.com>
> 
> Quad registers are read/written incorrectly. E825 devices always use
> quad 0 address and differentiate between the PHYs by changing SBQ
> destination device (phy_0 or phy_0_peer).
> 
> Add helpers for reading/writing PTP registers shared per quad and use
> correct quad address and SBQ destination device based on port.
> 
> Rename rmn_0 to phy_0 and remove rmn_1 and rmn_2 as E82X HW does not
> support it. Rename eth56g_phy_1 to phy_0_peer.
> 
> Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products")
> Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> ---
> V2 -> V3: Replaced lower/upper_32_bits calls with lower/upper_16_bits
> V1 -> V2: Fixed kdoc issues
> 
>  drivers/net/ethernet/intel/ice/ice_common.c   |   2 +-
>  .../net/ethernet/intel/ice/ice_ptp_consts.h   |  75 ++----
>  drivers/net/ethernet/intel/ice/ice_ptp_hw.c   | 237 +++++++++++-------
>  drivers/net/ethernet/intel/ice/ice_ptp_hw.h   |  37 ++-
>  drivers/net/ethernet/intel/ice/ice_sbq_cmd.h  |   7 +-
>  drivers/net/ethernet/intel/ice/ice_type.h     |   1 -
>  6 files changed, 177 insertions(+), 182 deletions(-)

This patch seems to mix bug fixes and cleanup.
Which leads to a rather large patch - larger than is desirable for stable IMHO.

Could we consider a more minimal fix for iwl-net.
And then follow-up with clean-ups for iwl?

...