From: Lu Baolu <baolu.lu@linux.intel.com>
To: Joerg Roedel <joro@8bytes.org>
Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: [PATCH 08/19] iommu/vt-d: Use PCI_DEVID() macro
Date: Mon, 4 Nov 2024 09:40:28 +0800 [thread overview]
Message-ID: <20241104014040.106100-9-baolu.lu@linux.intel.com> (raw)
In-Reply-To: <20241104014040.106100-1-baolu.lu@linux.intel.com>
From: Jinjie Ruan <ruanjinjie@huawei.com>
The macro PCI_DEVID() can be used instead of compose it manually.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/20240829021011.4135618-1-ruanjinjie@huawei.com
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
drivers/iommu/intel/iommu.c | 4 ++--
drivers/iommu/intel/irq_remapping.c | 4 ++--
drivers/iommu/intel/pasid.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 5fbf1237188c..a2212d15371d 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -1452,7 +1452,7 @@ static void copied_context_tear_down(struct intel_iommu *iommu,
if (did_old < cap_ndoms(iommu->cap)) {
iommu->flush.flush_context(iommu, did_old,
- (((u16)bus) << 8) | devfn,
+ PCI_DEVID(bus, devfn),
DMA_CCMD_MASK_NOBIT,
DMA_CCMD_DEVICE_INVL);
iommu->flush.flush_iotlb(iommu, did_old, 0, 0,
@@ -1473,7 +1473,7 @@ static void context_present_cache_flush(struct intel_iommu *iommu, u16 did,
{
if (cap_caching_mode(iommu->cap)) {
iommu->flush.flush_context(iommu, 0,
- (((u16)bus) << 8) | devfn,
+ PCI_DEVID(bus, devfn),
DMA_CCMD_MASK_NOBIT,
DMA_CCMD_DEVICE_INVL);
iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH);
diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_remapping.c
index 7a6d188e3bea..466c1412dd45 100644
--- a/drivers/iommu/intel/irq_remapping.c
+++ b/drivers/iommu/intel/irq_remapping.c
@@ -312,7 +312,7 @@ static int set_ioapic_sid(struct irte *irte, int apic)
for (i = 0; i < MAX_IO_APICS; i++) {
if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
- sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
+ sid = PCI_DEVID(ir_ioapic[i].bus, ir_ioapic[i].devfn);
break;
}
}
@@ -337,7 +337,7 @@ static int set_hpet_sid(struct irte *irte, u8 id)
for (i = 0; i < MAX_HPET_TBS; i++) {
if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
- sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
+ sid = PCI_DEVID(ir_hpet[i].bus, ir_hpet[i].devfn);
break;
}
}
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index 53157e1194f4..7ef157615e0f 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -220,7 +220,7 @@ devtlb_invalidation_with_pasid(struct intel_iommu *iommu,
if (pci_dev_is_disconnected(to_pci_dev(dev)))
return;
- sid = info->bus << 8 | info->devfn;
+ sid = PCI_DEVID(info->bus, info->devfn);
qdep = info->ats_qdep;
pfsid = info->pfsid;
--
2.43.0
next prev parent reply other threads:[~2024-11-04 1:41 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-04 1:40 [PATCH 00/19] [PULL REQUEST] Intel IOMMU updates for v6.13 Lu Baolu
2024-11-04 1:40 ` [PATCH 01/19] iommu/vt-d: Add domain_alloc_paging support Lu Baolu
2024-11-04 1:40 ` [PATCH 02/19] iommu/vt-d: Remove unused domain_alloc callback Lu Baolu
2024-11-04 1:40 ` [PATCH 03/19] iommu/vt-d: Enhance compatibility check for paging domain attach Lu Baolu
2024-11-04 1:40 ` [PATCH 04/19] iommu/vt-d: Remove domain_update_iommu_cap() Lu Baolu
2024-11-04 1:40 ` [PATCH 05/19] iommu/vt-d: Remove domain_update_iommu_superpage() Lu Baolu
2024-11-04 1:40 ` [PATCH 06/19] iommu/vt-d: Refactor first_level_by_default() Lu Baolu
2024-11-04 1:40 ` [PATCH 07/19] iommu/vt-d: Refine intel_iommu_domain_alloc_user() Lu Baolu
2024-11-04 1:40 ` Lu Baolu [this message]
2024-11-04 1:40 ` [PATCH 09/19] iommu/vt-d: Increase buffer size for device name Lu Baolu
2024-11-04 1:40 ` [PATCH 10/19] iommu/vt-d: Remove unused dmar_msi_read Lu Baolu
2024-11-04 1:40 ` [PATCH 11/19] iommu/vt-d: Drop s1_pgtbl from dmar_domain Lu Baolu
2024-11-04 1:40 ` [PATCH 12/19] iommu/vt-d: Fix checks and print in dmar_fault_dump_ptes() Lu Baolu
2024-11-04 1:40 ` [PATCH 13/19] iommu/vt-d: Fix checks and print in pgtable_walk() Lu Baolu
2024-11-04 1:40 ` [PATCH 14/19] iommu/vt-d: Separate page request queue from SVM Lu Baolu
2024-11-04 1:40 ` [PATCH 15/19] iommu/vt-d: Remove the pasid present check in prq_event_thread Lu Baolu
2024-11-04 1:40 ` [PATCH 16/19] iommu/vt-d: Move IOMMU_IOPF into INTEL_IOMMU Lu Baolu
2024-11-04 1:40 ` [PATCH 17/19] iommufd: Enable PRI when doing the iommufd_hwpt_alloc Lu Baolu
2024-11-04 1:40 ` [PATCH 18/19] iommu/vt-d: Drop pasid requirement for prq initialization Lu Baolu
2024-11-04 1:40 ` [PATCH 19/19] iommu/vt-d: Drain PRQs when domain removed from RID Lu Baolu
2024-11-05 12:33 ` [PATCH 00/19] [PULL REQUEST] Intel IOMMU updates for v6.13 Joerg Roedel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20241104014040.106100-9-baolu.lu@linux.intel.com \
--to=baolu.lu@linux.intel.com \
--cc=iommu@lists.linux.dev \
--cc=joro@8bytes.org \
--cc=linux-kernel@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.