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From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>,
	qemu-devel@nongnu.org, Chalapathi V <chalapathi.v@linux.ibm.com>,
	Harsh Prateek Bora <harshpb@linux.ibm.com>,
	Glenn Miles <milesg@linux.ibm.com>
Subject: [PATCH 3/4] target/ppc: Fix THREAD_SIBLING_FOREACH for mult-socket
Date: Mon, 25 Nov 2024 23:20:40 +1000	[thread overview]
Message-ID: <20241125132042.325734-4-npiggin@gmail.com> (raw)
In-Reply-To: <20241125132042.325734-1-npiggin@gmail.com>

From: Glenn Miles <milesg@linux.ibm.com>

The THREAD_SIBLING_FOREACH macro wasn't excluding threads from
other chips. Add chip_index field to the thread state and add
a check for the new field in the macro.

Fixes: b769d4c8f4c6 ("target/ppc: Add initial flags and helpers for SMT support")
Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
[npiggin: set chip_index for spapr too]
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 target/ppc/cpu.h        | 7 +++++--
 hw/ppc/pnv_core.c       | 2 ++
 hw/ppc/spapr_cpu_core.c | 1 +
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 0b4f1013b8..2ffac2ed03 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1253,6 +1253,7 @@ struct CPUArchState {
     /* For SMT processors */
     bool has_smt_siblings;
     int core_index;
+    int chip_index;
 
 #if !defined(CONFIG_USER_ONLY)
     /* MMU context, only relevant for full system emulation */
@@ -1412,8 +1413,10 @@ struct CPUArchState {
 
 #define THREAD_SIBLING_FOREACH(cs, cs_sibling)                  \
     CPU_FOREACH(cs_sibling)                                     \
-        if (POWERPC_CPU(cs)->env.core_index ==                  \
-            POWERPC_CPU(cs_sibling)->env.core_index)
+        if ((POWERPC_CPU(cs)->env.chip_index ==                 \
+             POWERPC_CPU(cs_sibling)->env.chip_index) &&        \
+            (POWERPC_CPU(cs)->env.core_index ==                 \
+             POWERPC_CPU(cs_sibling)->env.core_index))
 
 #define SET_FIT_PERIOD(a_, b_, c_, d_)          \
 do {                                            \
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index cbfac49862..e6b02294b1 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -322,6 +322,8 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp,
     pir_spr->default_value = pir;
     tir_spr->default_value = tir;
 
+    env->chip_index = pc->chip->chip_id;
+
     if (pc->big_core) {
         /* 2 "small cores" get the same core index for SMT operations */
         env->core_index = core_hwid >> 1;
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index ada439e831..135f86a622 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -313,6 +313,7 @@ static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
         return NULL;
     }
 
+    env->chip_index = sc->node_id;
     env->core_index = cc->core_id;
 
     cpu->node_id = sc->node_id;
-- 
2.45.2



  parent reply	other threads:[~2024-11-25 13:22 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-25 13:20 [PATCH 0/4] ppc: various fixes for 9.2 Nicholas Piggin
2024-11-25 13:20 ` [PATCH 1/4] target/ppc: Fix non-maskable interrupt while halted Nicholas Piggin
2024-11-25 16:26   ` Miles Glenn
2024-11-25 13:20 ` [PATCH 2/4] ppc/pnv: Fix direct controls quiesce Nicholas Piggin
2024-11-25 16:31   ` Miles Glenn
2024-11-25 13:20 ` Nicholas Piggin [this message]
2024-11-25 16:26   ` [PATCH 3/4] target/ppc: Fix THREAD_SIBLING_FOREACH for mult-socket Miles Glenn
2024-11-25 13:20 ` [PATCH 4/4] ppc/pnv: Add xscom- prefix to pervasive-control region name Nicholas Piggin
2024-11-25 16:28   ` Miles Glenn
2024-11-25 19:28   ` Philippe Mathieu-Daudé
2024-11-26  3:54     ` Nicholas Piggin
2024-11-26  5:19       ` Philippe Mathieu-Daudé
2024-11-26 15:43         ` Peter Xu

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