[PATCH v3 1/2] cpufreq: dt: permit defining custom .get and .target_index

[PATCH v3 1/2] cpufreq: dt: permit defining custom .get and .target_index

[Christian Marangi]

Some modern device might have CPU frequency control totally detached
from the system and entirely handled by ATF or Secure World. Such device
also tune the CPU frequency indirectly with special call, like SMCCC
calls.

In such condition, creating a special clock for the task might introduce
lots of unneeded overhead to permit usage of the generic "cpufreq-dt"
driver.

To handle this scenario, expand the "cpufreq-dt" driver to also permit
defining custom .get and .target_index function. This is already
supported for the .suspend, .resume and the .get_intermediate OPs.

With this, custom CPU Freq driver can now define custom .get and
.target_index and directly make SMCCC calls to tune the CPU frequency
while keeping full support of all the property and initialization of
"cpufreq-dt".

It's also needed to introduce a bool to permit skipping CPU clock
parsing (no_cpu_clk). This bool is applied only if a custom .get is
defined and is needed to handle case when the CPU node doesn't have a
clock defined as it's entirely handled indirectly and not exposed to the
system. This permits full init of cpufreq-dt with custom .get() and
.target_index().

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
Changes v3:
- Add this patch

 drivers/cpufreq/cpufreq-dt.c | 19 +++++++++++++++++--
 drivers/cpufreq/cpufreq-dt.h |  4 ++++
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
index 983443396f8f..ecbac6502b57 100644
--- a/drivers/cpufreq/cpufreq-dt.c
+++ b/drivers/cpufreq/cpufreq-dt.c
@@ -31,6 +31,7 @@ struct private_data {
 	struct device *cpu_dev;
 	struct cpufreq_frequency_table *freq_table;
 	bool have_static_opps;
+	bool no_cpu_clk;
 	int opp_token;
 };
 
@@ -90,7 +91,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
 {
 	struct private_data *priv;
 	struct device *cpu_dev;
-	struct clk *cpu_clk;
+	struct clk *cpu_clk = NULL;
 	unsigned int transition_latency;
 	int ret;
 
@@ -101,7 +102,13 @@ static int cpufreq_init(struct cpufreq_policy *policy)
 	}
 	cpu_dev = priv->cpu_dev;
 
-	cpu_clk = clk_get(cpu_dev, NULL);
+	/*
+	 * CPU might have special clock handling (example handled by ATF with
+	 * SMCCC calls). If instructed, skip checking for a CPU clock as it's
+	 * handled by custom .get.
+	 */
+	if (!priv->no_cpu_clk)
+		cpu_clk = clk_get(cpu_dev, NULL);
 	if (IS_ERR(cpu_clk)) {
 		ret = PTR_ERR(cpu_clk);
 		dev_err(cpu_dev, "%s: failed to get clk: %d\n", __func__, ret);
@@ -175,6 +182,7 @@ static struct cpufreq_driver dt_cpufreq_driver = {
 
 static int dt_cpufreq_early_init(struct device *dev, int cpu)
 {
+	struct cpufreq_dt_platform_data *data = dev_get_platdata(dev);
 	struct private_data *priv;
 	struct device *cpu_dev;
 	bool fallback = false;
@@ -198,6 +206,9 @@ static int dt_cpufreq_early_init(struct device *dev, int cpu)
 
 	cpumask_set_cpu(cpu, priv->cpus);
 	priv->cpu_dev = cpu_dev;
+	/* Permit CPU with no clock, if custom .get is defined */
+	if (data->get)
+		priv->no_cpu_clk = data->no_cpu_clk;
 
 	/*
 	 * OPP layer will be taking care of regulators now, but it needs to know
@@ -313,6 +324,10 @@ static int dt_cpufreq_probe(struct platform_device *pdev)
 		if (data->have_governor_per_policy)
 			dt_cpufreq_driver.flags |= CPUFREQ_HAVE_GOVERNOR_PER_POLICY;
 
+		if (data->get)
+			dt_cpufreq_driver.get = data->get;
+		if (data->target_index)
+			dt_cpufreq_driver.target_index = data->target_index;
 		dt_cpufreq_driver.resume = data->resume;
 		if (data->suspend)
 			dt_cpufreq_driver.suspend = data->suspend;
diff --git a/drivers/cpufreq/cpufreq-dt.h b/drivers/cpufreq/cpufreq-dt.h
index 28c8af7ec5ef..ba0385d75bdb 100644
--- a/drivers/cpufreq/cpufreq-dt.h
+++ b/drivers/cpufreq/cpufreq-dt.h
@@ -13,7 +13,11 @@ struct cpufreq_policy;
 
 struct cpufreq_dt_platform_data {
 	bool have_governor_per_policy;
+	bool no_cpu_clk;
 
+	unsigned int	(*get)(unsigned int cpu);
+	int		(*target_index)(struct cpufreq_policy *policy,
+					unsigned int index);
 	unsigned int	(*get_intermediate)(struct cpufreq_policy *policy,
 					    unsigned int index);
 	int		(*target_intermediate)(struct cpufreq_policy *policy,
-- 
2.45.2

[PATCH v3 2/2] cpufreq: airoha: Add EN7581 Cpufreq SMC driver

[Christian Marangi]

Add simple CPU Freq driver for Airoha EN7581 SoC that control CPU
frequency scaling with SMC APIs and register a generic "cpufreq-dt"
device.

All CPU share the same frequency and can't be controlled independently.
Current shared CPU frequency is returned by the related SMC command.

Add SoC compatible to cpufreq-dt-plat block list as a dedicated cpufreq
driver is needed with OPP v2 nodes declared in DTS.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
Changes v3:
- Adapt to new cpufreq-dt APIs
- Register cpufreq-dt instead of custom freq driver
Changes v2:
- Fix kernel bot error with missing slab.h and bitfield.h header
- Limit COMPILE_TEST to ARM64 due to smcc 1.2

 drivers/cpufreq/Kconfig.arm          |   8 +++
 drivers/cpufreq/Makefile             |   1 +
 drivers/cpufreq/airoha-cpufreq.c     | 103 +++++++++++++++++++++++++++
 drivers/cpufreq/cpufreq-dt-platdev.c |   2 +
 4 files changed, 114 insertions(+)
 create mode 100644 drivers/cpufreq/airoha-cpufreq.c

diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 5f7e13e60c80..338fc54276f2 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -15,6 +15,14 @@ config ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM
 	  To compile this driver as a module, choose M here: the
 	  module will be called sun50i-cpufreq-nvmem.
 
+config ARM_AIROHA_SOC_CPUFREQ
+	tristate "Airoha EN7581 SoC CPUFreq support"
+	depends on ARCH_AIROHA || (COMPILE_TEST && ARM64)
+	select PM_OPP
+	default ARCH_AIROHA
+	help
+	  This adds the CPUFreq driver for Airoha EN7581 SoCs.
+
 config ARM_APPLE_SOC_CPUFREQ
 	tristate "Apple Silicon SoC CPUFreq support"
 	depends on ARCH_APPLE || (COMPILE_TEST && 64BIT)
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 0f184031dd12..8e5a37a95d36 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_X86_AMD_FREQ_SENSITIVITY)	+= amd_freq_sensitivity.o
 
 ##################################################################################
 # ARM SoC drivers
+obj-$(CONFIG_ARM_AIROHA_SOC_CPUFREQ)	+= airoha-cpufreq.o
 obj-$(CONFIG_ARM_APPLE_SOC_CPUFREQ)	+= apple-soc-cpufreq.o
 obj-$(CONFIG_ARM_ARMADA_37XX_CPUFREQ)	+= armada-37xx-cpufreq.o
 obj-$(CONFIG_ARM_ARMADA_8K_CPUFREQ)	+= armada-8k-cpufreq.o
diff --git a/drivers/cpufreq/airoha-cpufreq.c b/drivers/cpufreq/airoha-cpufreq.c
new file mode 100644
index 000000000000..52d863a7363a
--- /dev/null
+++ b/drivers/cpufreq/airoha-cpufreq.c
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/arm-smccc.h>
+#include <linux/bitfield.h>
+#include <linux/cpufreq.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "cpufreq-dt.h"
+
+#define AIROHA_SIP_AVS_HANDLE			0x82000301
+#define AIROHA_AVS_OP_BASE			0xddddddd0
+#define AIROHA_AVS_OP_MASK			GENMASK(1, 0)
+#define AIROHA_AVS_OP_FREQ_DYN_ADJ		(AIROHA_AVS_OP_BASE | \
+						 FIELD_PREP(AIROHA_AVS_OP_MASK, 0x1))
+#define AIROHA_AVS_OP_GET_FREQ			(AIROHA_AVS_OP_BASE | \
+						 FIELD_PREP(AIROHA_AVS_OP_MASK, 0x2))
+
+struct airoha_cpufreq_state {
+	struct platform_device *cpufreq_dt;
+};
+
+static struct airoha_cpufreq_state *airoha_cpufreq_state;
+
+static unsigned int airoha_cpufreq_get(unsigned int cpu)
+{
+	const struct arm_smccc_1_2_regs args = {
+		.a0 = AIROHA_SIP_AVS_HANDLE,
+		.a1 = AIROHA_AVS_OP_GET_FREQ,
+	};
+	struct arm_smccc_1_2_regs res;
+
+	arm_smccc_1_2_smc(&args, &res);
+
+	return (int)(res.a0 * 1000);
+}
+
+static int airoha_cpufreq_set_target(struct cpufreq_policy *policy, unsigned int index)
+{
+	const struct arm_smccc_1_2_regs args = {
+		.a0 = AIROHA_SIP_AVS_HANDLE,
+		.a1 = AIROHA_AVS_OP_FREQ_DYN_ADJ,
+		.a3 = index,
+	};
+	struct arm_smccc_1_2_regs res;
+
+	arm_smccc_1_2_smc(&args, &res);
+
+	/* SMC signal correct apply by unsetting BIT 0 */
+	return res.a0 & BIT(0) ? -EINVAL : 0;
+}
+
+static int __init airoha_cpufreq_driver_init(void)
+{
+	struct cpufreq_dt_platform_data pdata = { };
+	struct platform_device *cpufreq_dt;
+	struct device *cpu_dev;
+	int ret;
+
+	if (!of_machine_is_compatible("airoha,en7581"))
+		return -ENODEV;
+
+	cpu_dev = get_cpu_device(0);
+	if (!cpu_dev) {
+		dev_err(cpu_dev, "Cannot get CPU\n");
+		return -ENODEV;
+	}
+
+	airoha_cpufreq_state = kzalloc(sizeof(*airoha_cpufreq_state), GFP_KERNEL);
+	if (!airoha_cpufreq_state)
+		return -ENOMEM;
+
+	pdata.no_cpu_clk = true;
+	pdata.target_index = airoha_cpufreq_set_target;
+	pdata.get = airoha_cpufreq_get;
+
+	cpufreq_dt = platform_device_register_data(NULL, "cpufreq-dt", -1, &pdata,
+						   sizeof(pdata));
+	ret = PTR_ERR_OR_ZERO(cpufreq_dt);
+	if (ret) {
+		dev_err(cpu_dev,
+			"failed to create cpufreq-dt device: %d\n", ret);
+		kfree(airoha_cpufreq_state);
+		return ret;
+	}
+
+	airoha_cpufreq_state->cpufreq_dt = cpufreq_dt;
+
+	return 0;
+}
+late_initcall(airoha_cpufreq_driver_init);
+
+static void __exit airoha_cpufreq_driver_remove(void)
+{
+	platform_device_unregister(airoha_cpufreq_state->cpufreq_dt);
+	kfree(airoha_cpufreq_state);
+}
+module_exit(airoha_cpufreq_driver_remove);
+
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("CPUfreq driver for Airoha SoCs");
+MODULE_LICENSE("GPL");
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 18942bfe9c95..5ecd8234bfac 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -103,6 +103,8 @@ static const struct of_device_id allowlist[] __initconst = {
  * platforms using "operating-points-v2" property.
  */
 static const struct of_device_id blocklist[] __initconst = {
+	{ .compatible = "airoha,en7581", },
+
 	{ .compatible = "allwinner,sun50i-h6", },
 	{ .compatible = "allwinner,sun50i-h616", },
 	{ .compatible = "allwinner,sun50i-h618", },
-- 
2.45.2