From: Sergey Senozhatsky <senozhatsky@chromium.org>
To: Zhang Rui <rui.zhang@intel.com>
Cc: hpa@zytor.com, peterz@infradead.org, thorsten.blum@toblux.com,
yuntao.wang@linux.dev, tony.luck@intel.com, len.brown@intel.com,
srinivas.pandruvada@intel.com, linux-kernel@vger.kernel.org,
stable@vger.kernel.org, tglx@linutronix.de, mingo@redhat.com,
bp@alien8.de, dave.hansen@linux.intel.com,
rafael.j.wysocki@intel.com, x86@kernel.org,
linux-pm@vger.kernel.org,
Sergey Senozhatsky <senozhatsky@chromium.org>
Subject: Re: bisected: [PATCH V4] x86/apic: Always explicitly disarm TSC-deadline timer
Date: Thu, 28 Nov 2024 20:22:46 +0900 [thread overview]
Message-ID: <20241128112246.GF10431@google.com> (raw)
In-Reply-To: <20241128111844.GE10431@google.com>
On (24/11/28 20:18), Sergey Senozhatsky wrote:
> > Disable the TSC Deadline timer in lapic_timer_shutdown() by writing to
> > MSR_IA32_TSC_DEADLINE when in TSC-deadline mode. Also avoid writing
> > to the initial-count register (APIC_TMICT) which is ignored in
> > TSC-deadline mode.
Upstream commit ffd95846c6ec6cf1f93da411ea10d504036cab42 (forgot
to mention)
next prev parent reply other threads:[~2024-11-28 11:22 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-28 11:18 bisected: [PATCH V4] x86/apic: Always explicitly disarm TSC-deadline timer Sergey Senozhatsky
2024-11-28 11:22 ` Sergey Senozhatsky [this message]
2024-11-30 11:21 ` Thomas Gleixner
2024-11-30 11:45 ` Sergey Senozhatsky
2024-12-01 11:17 ` [PATCH] modpost: Add .irqentry.text to OTHER_SECTIONS Thomas Gleixner
2024-12-02 2:02 ` Masahiro Yamada
2024-12-02 21:03 ` Thomas Gleixner
2024-12-03 15:27 ` Masahiro Yamada
2024-12-03 16:10 ` Thomas Gleixner
2024-12-02 4:10 ` Sergey Senozhatsky
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