From: Stefan Hajnoczi <stefanha@redhat.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: qemu-devel@nongnu.org, alistair23@gmail.com,
Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PULL 00/39] riscv-to-apply queue
Date: Thu, 19 Dec 2024 15:45:49 -0500 [thread overview]
Message-ID: <20241219204549.GA724589@fedora> (raw)
In-Reply-To: <20241218223010.1931245-1-alistair.francis@wdc.com>
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Hi Alistair,
Please take a look at the following CI failure:
x86_64-w64-mingw32-gcc -m64 -Ilibqemuutil.a.p -I. -I.. -Iqapi -Itrace -Iui -Iui/shader -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/glib-2.0 -I/usr/x86_64-w64-mingw32/sys-root/mingw/lib/glib-2.0/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/p11-kit-1 -fdiagnostics-color=auto -Wall -Winvalid-pch -Werror -std=gnu11 -O2 -g -fstack-protector-strong -Wempty-body -Wendif-labels -Wexpansion-to-defined -Wformat-security -Wformat-y2k -Wignored-qualifiers -Wimplicit-fallthrough=2 -Winit-self -Wmissing-format-attribute -Wmissing-prototypes -Wnested-externs -Wold-style-declaration -Wold-style-definition -Wredundant-decls -Wshadow=local -Wstrict-prototypes -Wtype-limits -Wundef -Wvla -Wwrite-strings -Wno-missing-include-dirs -Wno-psabi -Wno-shift-negative-value -iquote . -iquote /builds/qemu-project/qemu -iquote /builds/qemu-project/qemu/include -iquote /builds/qemu-project/qemu/host/include/x86_64 -iquote /builds/qemu-project/qemu/host/include/generic -iquote /builds/qemu-project/qemu/tcg/i386 -mms-bitfields -mcx16 -msse2 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -fno-strict-aliasing -fno-common -fwrapv -fno-pie -no-pie -ftrivial-auto-var-init=zero -fzero-call-used-regs=used-gpr -mms-bitfields -pthread -mms-bitfields -MD -MQ libqemuutil.a.p/meson-generated_.._trace_trace-hw_riscv.c.obj -MF libqemuutil.a.p/meson-generated_.._trace_trace-hw_riscv.c.obj.d -o libqemuutil.a.p/meson-generated_.._trace_trace-hw_riscv.c.obj -c trace/trace-hw_riscv.c
In file included from trace/trace-hw_riscv.c:5:
../hw/riscv/trace-events: In function '_nocheck__trace_riscv_iommu_sys_msi_sent':
../hw/riscv/trace-events:19:22: error: format '%lx' expects argument of type 'long unsigned int', but argument 6 has type 'uint64_t' {aka 'long long unsigned int'} [-Werror=format=]
19 | riscv_iommu_sys_msi_sent(uint32_t vector, uint64_t msi_addr, uint32_t msi_data, uint32_t result) "MSI sent to vector %u msi_addr 0x%lx msi_data 0x%x result %u"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
......
../hw/riscv/trace-events:19:22: error: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'uint64_t' {aka 'long long unsigned int'} [-Werror=format=]
19 | riscv_iommu_sys_msi_sent(uint32_t vector, uint64_t msi_addr, uint32_t msi_data, uint32_t result) "MSI sent to vector %u msi_addr 0x%lx msi_data 0x%x result %u"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~
| |
| uint64_t {aka long long unsigned int}
cc1: all warnings being treated as errors
https://gitlab.com/qemu-project/qemu/-/jobs/8691704969#L2578
Once the issue has been solved, please send a new revision of this pull
request.
Thanks,
Stefan
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next prev parent reply other threads:[~2024-12-19 20:46 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-18 22:29 [PULL 00/39] riscv-to-apply queue Alistair Francis
2024-12-18 22:29 ` [PULL 01/39] hw/riscv/riscv-iommu.c: Correct the validness check of iova Alistair Francis
2024-12-18 22:29 ` [PULL 02/39] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation Alistair Francis
2024-12-18 22:29 ` [PULL 03/39] hw/riscv/riscv-iommu.c: add riscv_iommu_instance_init() Alistair Francis
2024-12-18 22:29 ` [PULL 04/39] hw/riscv/riscv-iommu: parametrize CAP.IGS Alistair Francis
2024-12-18 22:29 ` [PULL 05/39] hw/riscv: add riscv-iommu-sys platform device Alistair Francis
2024-12-18 22:29 ` [PULL 06/39] hw/riscv/virt: Add IOMMU as platform device if the option is set Alistair Francis
2024-12-18 22:29 ` [PULL 07/39] hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support Alistair Francis
2024-12-18 22:29 ` [PULL 08/39] hw/riscv/riscv-iommu: implement reset protocol Alistair Francis
2024-12-18 22:29 ` [PULL 09/39] docs/specs: add riscv-iommu-sys information Alistair Francis
2024-12-18 22:29 ` [PULL 10/39] target/riscv: Add Tenstorrent Ascalon CPU Alistair Francis
2024-12-18 22:29 ` [PULL 11/39] hw/intc/riscv_aplic: rename is_kvm_aia() Alistair Francis
2024-12-18 22:29 ` [PULL 12/39] hw/riscv/virt.c: reduce virt_use_kvm_aia() usage Alistair Francis
2024-12-18 22:29 ` [PULL 13/39] hw/riscv/virt.c: rename helper to virt_use_kvm_aia_aplic_imsic() Alistair Francis
2024-12-18 22:29 ` [PULL 14/39] target/riscv/kvm: consider irqchip_split() in aia_create() Alistair Francis
2024-12-18 22:29 ` [PULL 15/39] hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpers Alistair Francis
2024-12-18 22:29 ` [PULL 16/39] hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic Alistair Francis
2024-12-18 22:29 ` [PULL 17/39] target/riscv/kvm: remove irqchip_split() restriction Alistair Francis
2024-12-18 22:29 ` [PULL 18/39] docs: update riscv/virt.rst with kernel-irqchip=split support Alistair Francis
2024-12-18 22:29 ` [PULL 19/39] hw/riscv: Add Microblaze V generic board Alistair Francis
2024-12-18 22:29 ` [PULL 20/39] qtest: allow SPCR acpi table changes Alistair Francis
2024-12-18 22:29 ` [PULL 21/39] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format Alistair Francis
2024-12-18 22:29 ` [PULL 22/39] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V Alistair Francis
2024-12-18 22:29 ` [PULL 23/39] MAINTAINERS: Cover RISC-V HTIF interface Alistair Francis
2024-12-18 22:29 ` [PULL 24/39] hw/char/riscv_htif: Explicit little-endian implementation Alistair Francis
2024-12-18 22:29 ` [PULL 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses Alistair Francis
2024-12-18 22:29 ` [PULL 26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system Alistair Francis
2024-12-18 22:29 ` [PULL 27/39] hw/riscv: Add a new struct RISCVBootInfo Alistair Francis
2024-12-18 22:29 ` [PULL 28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd Alistair Francis
2024-12-18 22:29 ` [PULL 29/39] target/riscv: Add svukte extension capability variable Alistair Francis
2024-12-18 22:30 ` [PULL 30/39] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled Alistair Francis
2024-12-18 22:30 ` [PULL 31/39] target/riscv: Support hstatus[HUKTE] " Alistair Francis
2024-12-18 22:30 ` [PULL 32/39] target/riscv: Check memory access to meet svukte rule Alistair Francis
2024-12-18 22:30 ` [PULL 33/39] target/riscv: Expose svukte ISA extension Alistair Francis
2024-12-18 22:30 ` [PULL 34/39] target/riscv: Check svukte is not enabled in RV32 Alistair Francis
2024-12-18 22:30 ` [PULL 35/39] target/riscv: Include missing headers in 'vector_internals.h' Alistair Francis
2024-12-18 22:30 ` [PULL 36/39] target/riscv: Include missing headers in 'internals.h' Alistair Francis
2024-12-18 22:30 ` [PULL 37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver Alistair Francis
2024-12-18 22:30 ` [PULL 38/39] target/riscv: add ssstateen Alistair Francis
2024-12-18 22:30 ` [PULL 39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU Alistair Francis
2024-12-19 20:45 ` Stefan Hajnoczi [this message]
2024-12-20 1:55 ` [PULL 00/39] riscv-to-apply queue Alistair Francis
2024-12-20 9:36 ` Daniel Henrique Barboza
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