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From: E Shattow <e@freeshell.de>
To: Emil Renner Berthing <kernel@esmil.dk>,
	Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-kernel@vger.kernel.org, E Shattow <e@freeshell.de>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org
Subject: [PATCH v1 1/5] riscv: dts: starfive: jh7110-common: replace syscrg clock assignments
Date: Thu,  2 Jan 2025 11:45:07 -0800	[thread overview]
Message-ID: <20250102194530.418127-2-e@freeshell.de> (raw)
In-Reply-To: <20250102194530.418127-1-e@freeshell.de>

Replace syscrg assignments of clocks, clock parents, and rates, for
compatibility with downstream boot loader SPL secondary program
loader.

Signed-off-by: E Shattow <e@freeshell.de>
---
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index 48fb5091b817..55c6743100a7 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -359,9 +359,15 @@ spi_dev0: spi@0 {
 };
 
 &syscrg {
-	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
-			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
-	assigned-clock-rates = <500000000>, <1500000000>;
+	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
+			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
+			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
+			  <&syscrg JH7110_SYSCLK_QSPI_REF>;
+	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
+				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
+	assigned-clock-rates = <0>, <0>, <0>, <0>;
 };
 
 &sysgpio {
-- 
2.45.2


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WARNING: multiple messages have this Message-ID (diff)
From: E Shattow <e@freeshell.de>
To: Emil Renner Berthing <kernel@esmil.dk>,
	Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-kernel@vger.kernel.org, E Shattow <e@freeshell.de>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org
Subject: [PATCH v1 1/5] riscv: dts: starfive: jh7110-common: replace syscrg clock assignments
Date: Thu,  2 Jan 2025 11:45:07 -0800	[thread overview]
Message-ID: <20250102194530.418127-2-e@freeshell.de> (raw)
In-Reply-To: <20250102194530.418127-1-e@freeshell.de>

Replace syscrg assignments of clocks, clock parents, and rates, for
compatibility with downstream boot loader SPL secondary program
loader.

Signed-off-by: E Shattow <e@freeshell.de>
---
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index 48fb5091b817..55c6743100a7 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -359,9 +359,15 @@ spi_dev0: spi@0 {
 };
 
 &syscrg {
-	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
-			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
-	assigned-clock-rates = <500000000>, <1500000000>;
+	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
+			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
+			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
+			  <&syscrg JH7110_SYSCLK_QSPI_REF>;
+	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
+				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
+	assigned-clock-rates = <0>, <0>, <0>, <0>;
 };
 
 &sysgpio {
-- 
2.45.2


  reply	other threads:[~2025-01-02 19:46 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-02 19:45 [PATCH v1 0/5] riscv: dts: starfive: jh7110-common: Sync downstream U-Boot changes E Shattow
2025-01-02 19:45 ` E Shattow
2025-01-02 19:45 ` E Shattow [this message]
2025-01-02 19:45   ` [PATCH v1 1/5] riscv: dts: starfive: jh7110-common: replace syscrg clock assignments E Shattow
2025-01-04 18:33   ` Conor Dooley
2025-01-04 18:33     ` Conor Dooley
2025-01-04 21:04     ` E Shattow
2025-01-04 21:04       ` E Shattow
2025-01-06 20:08       ` Conor Dooley
2025-01-06 20:08         ` Conor Dooley
2025-01-15  6:33         ` Hal Feng
2025-01-15  6:33           ` Hal Feng
2025-01-15  9:35           ` Conor Dooley
2025-01-15  9:35             ` Conor Dooley
2025-01-24 10:46             ` E Shattow
2025-01-24 10:46               ` E Shattow
2025-02-07  8:17               ` Hal Feng
2025-02-07  8:17                 ` Hal Feng
2025-01-02 19:45 ` [PATCH v1 2/5] riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz E Shattow
2025-01-02 19:45   ` E Shattow
2025-01-14  7:27   ` Hal Feng
2025-01-14  7:27     ` Hal Feng
2025-01-02 19:45 ` [PATCH v1 3/5] riscv: dts: starfive: jh7110-common: assign 24MHz clock-frequency to uart0 E Shattow
2025-01-02 19:45   ` E Shattow
2025-01-02 19:45 ` [PATCH v1 4/5] riscv: dts: starfive: jh7110-common: add eeprom node to i2c5 E Shattow
2025-01-02 19:45   ` E Shattow
2025-01-14  8:28   ` Hal Feng
2025-01-14  8:28     ` Hal Feng
2025-01-02 19:45 ` [PATCH v1 5/5] riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader E Shattow
2025-01-02 19:45   ` E Shattow

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