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From: E Shattow <e@freeshell.de>
To: Emil Renner Berthing <kernel@esmil.dk>,
	Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	devicetree@vger.kernel.org, E Shattow <e@freeshell.de>
Subject: [RFC PATCH v1 2/3] riscv: dts: starfive: jh7110: add DRAM memory controller node
Date: Thu,  2 Jan 2025 12:41:22 -0800	[thread overview]
Message-ID: <20250102204137.423081-3-e@freeshell.de> (raw)
In-Reply-To: <20250102204137.423081-1-e@freeshell.de>

add DRAM memory controller node (no driver), required for U-Boot to boot
successfully.

Signed-off-by: E Shattow <e@freeshell.de>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 0bc922b3ae8a..6948974400c1 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -381,6 +381,19 @@ ccache: cache-controller@2010000 {
 			cache-unified;
 		};
 
+		dmc: dmc@15700000 {
+			compatible = "starfive,jh7110-dmc";
+			reg = <0x0 0x15700000 0x0 0x10000>,
+			      <0x0 0x13000000 0x0 0x10000>;
+			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+				 <&syscrg JH7110_SYSRST_DDR_OSC>,
+				 <&syscrg JH7110_SYSRST_DDR_APB>;
+			reset-names = "axi", "osc", "apb";
+			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+			clock-names = "pll1_out";
+			clock-frequency = <2133>;
+		};
+
 		plic: interrupt-controller@c000000 {
 			compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;
-- 
2.45.2


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WARNING: multiple messages have this Message-ID (diff)
From: E Shattow <e@freeshell.de>
To: Emil Renner Berthing <kernel@esmil.dk>,
	Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	devicetree@vger.kernel.org, E Shattow <e@freeshell.de>
Subject: [RFC PATCH v1 2/3] riscv: dts: starfive: jh7110: add DRAM memory controller node
Date: Thu,  2 Jan 2025 12:41:22 -0800	[thread overview]
Message-ID: <20250102204137.423081-3-e@freeshell.de> (raw)
In-Reply-To: <20250102204137.423081-1-e@freeshell.de>

add DRAM memory controller node (no driver), required for U-Boot to boot
successfully.

Signed-off-by: E Shattow <e@freeshell.de>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 0bc922b3ae8a..6948974400c1 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -381,6 +381,19 @@ ccache: cache-controller@2010000 {
 			cache-unified;
 		};
 
+		dmc: dmc@15700000 {
+			compatible = "starfive,jh7110-dmc";
+			reg = <0x0 0x15700000 0x0 0x10000>,
+			      <0x0 0x13000000 0x0 0x10000>;
+			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+				 <&syscrg JH7110_SYSRST_DDR_OSC>,
+				 <&syscrg JH7110_SYSRST_DDR_APB>;
+			reset-names = "axi", "osc", "apb";
+			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+			clock-names = "pll1_out";
+			clock-frequency = <2133>;
+		};
+
 		plic: interrupt-controller@c000000 {
 			compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;
-- 
2.45.2


  parent reply	other threads:[~2025-01-02 20:45 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-02 20:41 [RFC PATCH v1 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 E Shattow
2025-01-02 20:41 ` E Shattow
2025-01-02 20:41 ` [RFC PATCH v1 1/3] riscv: dts: starfive: jh7110: add timer node E Shattow
2025-01-02 20:41   ` E Shattow
2025-01-13 18:39   ` Conor Dooley
2025-01-13 18:39     ` Conor Dooley
2025-01-24 11:19     ` E Shattow
2025-01-24 11:19       ` E Shattow
2025-01-24 16:40       ` Conor Dooley
2025-01-24 16:40         ` Conor Dooley
2025-01-02 20:41 ` E Shattow [this message]
2025-01-02 20:41   ` [RFC PATCH v1 2/3] riscv: dts: starfive: jh7110: add DRAM memory controller node E Shattow
2025-01-13 18:41   ` Conor Dooley
2025-01-13 18:41     ` Conor Dooley
2025-01-02 20:41 ` [RFC PATCH v1 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader E Shattow
2025-01-02 20:41   ` E Shattow
2025-01-13 18:41 ` [RFC PATCH v1 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 Conor Dooley
2025-01-13 18:41   ` Conor Dooley

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