From: Andrew Jones <ajones@ventanamicro.com>
To: Yunhui Cui <cuiyunhui@bytedance.com>
Cc: alexghiti@rivosinc.com, andybnac@gmail.com,
aou@eecs.berkeley.edu, charlie@rivosinc.com,
cleger@rivosinc.com, conor.dooley@microchip.com,
conor@kernel.org, corbet@lwn.net, evan@rivosinc.com,
jesse@rivosinc.com, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org,
linux-riscv@lists.infradead.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, samuel.holland@sifive.com,
shuah@kernel.org
Subject: Re: [PATCH v3 3/3] RISC-V: selftests: Add TEST_ZICBOM into CBO tests
Date: Mon, 13 Jan 2025 10:18:07 +0100 [thread overview]
Message-ID: <20250113-cb08bcb35bc8b6213fe89ecd@orel> (raw)
In-Reply-To: <20250113083635.73826-3-cuiyunhui@bytedance.com>
On Mon, Jan 13, 2025 at 04:36:35PM +0800, Yunhui Cui wrote:
> Add test for Zicbom and its block size into CBO tests, when
> Zicbom is present, test that cbo.clean/flush may be issued and works.
> As the software can't verify the clean/flush functions, we just judged
> that cbo.clean/flush isn't executed illegally.
>
> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> ---
> tools/testing/selftests/riscv/hwprobe/cbo.c | 49 ++++++++++++++++++---
> 1 file changed, 43 insertions(+), 6 deletions(-)
>
> diff --git a/tools/testing/selftests/riscv/hwprobe/cbo.c b/tools/testing/selftests/riscv/hwprobe/cbo.c
> index a40541bb7c7d..b63e23f95e08 100644
> --- a/tools/testing/selftests/riscv/hwprobe/cbo.c
> +++ b/tools/testing/selftests/riscv/hwprobe/cbo.c
> @@ -81,6 +81,30 @@ static bool is_power_of_2(__u64 n)
> return n != 0 && (n & (n - 1)) == 0;
> }
>
> +static void test_zicbom(void *arg)
> +{
> + struct riscv_hwprobe pair = {
> + .key = RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE,
> + };
> + cpu_set_t *cpus = (cpu_set_t *)arg;
> + __u64 block_size;
> + long rc;
> +
> + rc = riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)cpus, 0);
> + block_size = pair.value;
> + ksft_test_result(rc == 0 && pair.key == RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE &&
> + is_power_of_2(block_size), "Zicbom block size\n");
> + ksft_print_msg("Zicbom block size: %llu\n", block_size);
> +
> + illegal_insn = false;
> + cbo_clean(&mem[block_size]);
> + ksft_test_result(!illegal_insn, "cbo.clean\n");
> +
> + illegal_insn = false;
> + cbo_flush(&mem[block_size]);
> + ksft_test_result(!illegal_insn, "cbo.flush\n");
> +}
> +
> static void test_zicboz(void *arg)
> {
> struct riscv_hwprobe pair = {
> @@ -129,7 +153,7 @@ static void test_zicboz(void *arg)
> ksft_test_result_pass("cbo.zero check\n");
> }
>
> -static void check_no_zicboz_cpus(cpu_set_t *cpus)
> +static void check_no_zicbo_cpus(cpu_set_t *cpus, __u64 cbo)
> {
> struct riscv_hwprobe pair = {
> .key = RISCV_HWPROBE_KEY_IMA_EXT_0,
> @@ -137,6 +161,7 @@ static void check_no_zicboz_cpus(cpu_set_t *cpus)
> cpu_set_t one_cpu;
> int i = 0, c = 0;
> long rc;
> + char *cbostr;
>
> while (i++ < CPU_COUNT(cpus)) {
> while (!CPU_ISSET(c, cpus))
> @@ -148,10 +173,13 @@ static void check_no_zicboz_cpus(cpu_set_t *cpus)
> rc = riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)&one_cpu, 0);
> assert(rc == 0 && pair.key == RISCV_HWPROBE_KEY_IMA_EXT_0);
>
> - if (pair.value & RISCV_HWPROBE_EXT_ZICBOZ)
> - ksft_exit_fail_msg("Zicboz is only present on a subset of harts.\n"
> - "Use taskset to select a set of harts where Zicboz\n"
> - "presence (present or not) is consistent for each hart\n");
> + cbostr = cbo == RISCV_HWPROBE_EXT_ZICBOZ ? "Zicboz" : "Zicbom";
> +
> + if (pair.value & cbo)
> + ksft_exit_fail_msg("%s is only present on a subset of harts.\n"
> + "Use taskset to select a set of harts where %s\n"
> + "presence (present or not) is consistent for each hart\n",
> + cbostr, cbostr);
> ++c;
> }
> }
> @@ -159,6 +187,7 @@ static void check_no_zicboz_cpus(cpu_set_t *cpus)
> enum {
> TEST_ZICBOZ,
> TEST_NO_ZICBOZ,
> + TEST_ZICBOM,
> TEST_NO_ZICBOM,
> };
>
> @@ -169,6 +198,7 @@ static struct test_info {
> } tests[] = {
> [TEST_ZICBOZ] = { .nr_tests = 3, test_zicboz },
> [TEST_NO_ZICBOZ] = { .nr_tests = 1, test_no_zicboz },
> + [TEST_ZICBOM] = { .nr_tests = 3, test_zicbom },
> [TEST_NO_ZICBOM] = { .nr_tests = 3, test_no_zicbom },
> };
>
> @@ -206,7 +236,14 @@ int main(int argc, char **argv)
> tests[TEST_ZICBOZ].enabled = true;
> tests[TEST_NO_ZICBOZ].enabled = false;
> } else {
> - check_no_zicboz_cpus(&cpus);
> + check_no_zicbo_cpus(&cpus, RISCV_HWPROBE_EXT_ZICBOZ);
> + }
> +
> + if (pair.value & RISCV_HWPROBE_EXT_ZICBOM) {
> + tests[TEST_ZICBOM].enabled = true;
> + tests[TEST_NO_ZICBOM].enabled = false;
> + } else {
> + check_no_zicbo_cpus(&cpus, RISCV_HWPROBE_EXT_ZICBOM);
> }
>
> for (i = 0; i < ARRAY_SIZE(tests); ++i)
> --
> 2.39.2
>
The test_no_zicbom() test needs to have the illegal instruction SIGILL
test for cbo.inval moved out into its own test. So, even when we have
zicbom we still test that cbo.inval generates a SIGILL.
Thanks,
drew
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <ajones@ventanamicro.com>
To: Yunhui Cui <cuiyunhui@bytedance.com>
Cc: alexghiti@rivosinc.com, andybnac@gmail.com,
aou@eecs.berkeley.edu, charlie@rivosinc.com,
cleger@rivosinc.com, conor.dooley@microchip.com,
conor@kernel.org, corbet@lwn.net, evan@rivosinc.com,
jesse@rivosinc.com, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org,
linux-riscv@lists.infradead.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, samuel.holland@sifive.com,
shuah@kernel.org
Subject: Re: [PATCH v3 3/3] RISC-V: selftests: Add TEST_ZICBOM into CBO tests
Date: Mon, 13 Jan 2025 10:18:07 +0100 [thread overview]
Message-ID: <20250113-cb08bcb35bc8b6213fe89ecd@orel> (raw)
In-Reply-To: <20250113083635.73826-3-cuiyunhui@bytedance.com>
On Mon, Jan 13, 2025 at 04:36:35PM +0800, Yunhui Cui wrote:
> Add test for Zicbom and its block size into CBO tests, when
> Zicbom is present, test that cbo.clean/flush may be issued and works.
> As the software can't verify the clean/flush functions, we just judged
> that cbo.clean/flush isn't executed illegally.
>
> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> ---
> tools/testing/selftests/riscv/hwprobe/cbo.c | 49 ++++++++++++++++++---
> 1 file changed, 43 insertions(+), 6 deletions(-)
>
> diff --git a/tools/testing/selftests/riscv/hwprobe/cbo.c b/tools/testing/selftests/riscv/hwprobe/cbo.c
> index a40541bb7c7d..b63e23f95e08 100644
> --- a/tools/testing/selftests/riscv/hwprobe/cbo.c
> +++ b/tools/testing/selftests/riscv/hwprobe/cbo.c
> @@ -81,6 +81,30 @@ static bool is_power_of_2(__u64 n)
> return n != 0 && (n & (n - 1)) == 0;
> }
>
> +static void test_zicbom(void *arg)
> +{
> + struct riscv_hwprobe pair = {
> + .key = RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE,
> + };
> + cpu_set_t *cpus = (cpu_set_t *)arg;
> + __u64 block_size;
> + long rc;
> +
> + rc = riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)cpus, 0);
> + block_size = pair.value;
> + ksft_test_result(rc == 0 && pair.key == RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE &&
> + is_power_of_2(block_size), "Zicbom block size\n");
> + ksft_print_msg("Zicbom block size: %llu\n", block_size);
> +
> + illegal_insn = false;
> + cbo_clean(&mem[block_size]);
> + ksft_test_result(!illegal_insn, "cbo.clean\n");
> +
> + illegal_insn = false;
> + cbo_flush(&mem[block_size]);
> + ksft_test_result(!illegal_insn, "cbo.flush\n");
> +}
> +
> static void test_zicboz(void *arg)
> {
> struct riscv_hwprobe pair = {
> @@ -129,7 +153,7 @@ static void test_zicboz(void *arg)
> ksft_test_result_pass("cbo.zero check\n");
> }
>
> -static void check_no_zicboz_cpus(cpu_set_t *cpus)
> +static void check_no_zicbo_cpus(cpu_set_t *cpus, __u64 cbo)
> {
> struct riscv_hwprobe pair = {
> .key = RISCV_HWPROBE_KEY_IMA_EXT_0,
> @@ -137,6 +161,7 @@ static void check_no_zicboz_cpus(cpu_set_t *cpus)
> cpu_set_t one_cpu;
> int i = 0, c = 0;
> long rc;
> + char *cbostr;
>
> while (i++ < CPU_COUNT(cpus)) {
> while (!CPU_ISSET(c, cpus))
> @@ -148,10 +173,13 @@ static void check_no_zicboz_cpus(cpu_set_t *cpus)
> rc = riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)&one_cpu, 0);
> assert(rc == 0 && pair.key == RISCV_HWPROBE_KEY_IMA_EXT_0);
>
> - if (pair.value & RISCV_HWPROBE_EXT_ZICBOZ)
> - ksft_exit_fail_msg("Zicboz is only present on a subset of harts.\n"
> - "Use taskset to select a set of harts where Zicboz\n"
> - "presence (present or not) is consistent for each hart\n");
> + cbostr = cbo == RISCV_HWPROBE_EXT_ZICBOZ ? "Zicboz" : "Zicbom";
> +
> + if (pair.value & cbo)
> + ksft_exit_fail_msg("%s is only present on a subset of harts.\n"
> + "Use taskset to select a set of harts where %s\n"
> + "presence (present or not) is consistent for each hart\n",
> + cbostr, cbostr);
> ++c;
> }
> }
> @@ -159,6 +187,7 @@ static void check_no_zicboz_cpus(cpu_set_t *cpus)
> enum {
> TEST_ZICBOZ,
> TEST_NO_ZICBOZ,
> + TEST_ZICBOM,
> TEST_NO_ZICBOM,
> };
>
> @@ -169,6 +198,7 @@ static struct test_info {
> } tests[] = {
> [TEST_ZICBOZ] = { .nr_tests = 3, test_zicboz },
> [TEST_NO_ZICBOZ] = { .nr_tests = 1, test_no_zicboz },
> + [TEST_ZICBOM] = { .nr_tests = 3, test_zicbom },
> [TEST_NO_ZICBOM] = { .nr_tests = 3, test_no_zicbom },
> };
>
> @@ -206,7 +236,14 @@ int main(int argc, char **argv)
> tests[TEST_ZICBOZ].enabled = true;
> tests[TEST_NO_ZICBOZ].enabled = false;
> } else {
> - check_no_zicboz_cpus(&cpus);
> + check_no_zicbo_cpus(&cpus, RISCV_HWPROBE_EXT_ZICBOZ);
> + }
> +
> + if (pair.value & RISCV_HWPROBE_EXT_ZICBOM) {
> + tests[TEST_ZICBOM].enabled = true;
> + tests[TEST_NO_ZICBOM].enabled = false;
> + } else {
> + check_no_zicbo_cpus(&cpus, RISCV_HWPROBE_EXT_ZICBOM);
> }
>
> for (i = 0; i < ARRAY_SIZE(tests); ++i)
> --
> 2.39.2
>
The test_no_zicbom() test needs to have the illegal instruction SIGILL
test for cbo.inval moved out into its own test. So, even when we have
zicbom we still test that cbo.inval generates a SIGILL.
Thanks,
drew
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next prev parent reply other threads:[~2025-01-13 9:18 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-13 8:36 [PATCH v3 1/3] RISC-V: Enable cbo.clean/flush in usermode Yunhui Cui
2025-01-13 8:36 ` Yunhui Cui
2025-01-13 8:36 ` [PATCH v3 2/3] RISC-V: hwprobe: Expose Zicbom extension and its block size Yunhui Cui
2025-01-13 8:36 ` Yunhui Cui
2025-01-13 9:07 ` Andrew Jones
2025-01-13 9:07 ` Andrew Jones
2025-01-13 11:29 ` [External] " yunhui cui
2025-01-13 11:29 ` yunhui cui
2025-01-13 12:41 ` Andrew Jones
2025-01-13 12:41 ` Andrew Jones
2025-01-13 8:36 ` [PATCH v3 3/3] RISC-V: selftests: Add TEST_ZICBOM into CBO tests Yunhui Cui
2025-01-13 8:36 ` Yunhui Cui
2025-01-13 9:18 ` Andrew Jones [this message]
2025-01-13 9:18 ` Andrew Jones
2025-01-13 11:49 ` [External] " yunhui cui
2025-01-13 11:49 ` yunhui cui
2025-01-13 12:42 ` Andrew Jones
2025-01-13 12:42 ` Andrew Jones
2025-01-13 8:53 ` [PATCH v3 1/3] RISC-V: Enable cbo.clean/flush in usermode Andrew Jones
2025-01-13 8:53 ` Andrew Jones
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