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From: Thomas Zimmermann <tzimmermann@suse.de>
To: airlied@redhat.com, jfalempe@redhat.com
Cc: dri-devel@lists.freedesktop.org, Thomas Zimmermann <tzimmermann@suse.de>
Subject: [PATCH 5/8] drm/ast: Hide Gens 1 to 3 TX detection in branch
Date: Fri, 17 Jan 2025 11:29:10 +0100	[thread overview]
Message-ID: <20250117103450.28692-6-tzimmermann@suse.de> (raw)
In-Reply-To: <20250117103450.28692-1-tzimmermann@suse.de>

Gen7 only supports ASTDP. Gens 4 to 6 support various TX chips,
except ASTDP. These boards detect the TX chips by reading the SoC
scratch register as VGACRD1.

Gens 1 to 3 only support SIL164. These boards read the DVO bit from
VGACRA3. Hence move this test behind a branch, so that it does not
run on later generations.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
---
 drivers/gpu/drm/ast/ast_main.c | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
index 474eb255b325b..50b57bc15d53c 100644
--- a/drivers/gpu/drm/ast/ast_main.c
+++ b/drivers/gpu/drm/ast/ast_main.c
@@ -96,21 +96,21 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
 	/* Check 3rd Tx option (digital output afaik) */
 	ast->tx_chip = AST_TX_NONE;
 
-	/*
-	 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
-	 * enabled, in that case, assume we have a SIL164 TMDS transmitter
-	 *
-	 * Don't make that assumption if we the chip wasn't enabled and
-	 * is at power-on reset, otherwise we'll incorrectly "detect" a
-	 * SIL164 when there is none.
-	 */
-	if (!need_post) {
-		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
-		if (jreg & 0x80)
-			ast->tx_chip = AST_TX_SIL164;
-	}
-
-	if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) {
+	if (AST_GEN(ast) <= 3) {
+		/*
+		 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
+		 * enabled, in that case, assume we have a SIL164 TMDS transmitter
+		 *
+		 * Don't make that assumption if we the chip wasn't enabled and
+		 * is at power-on reset, otherwise we'll incorrectly "detect" a
+		 * SIL164 when there is none.
+		 */
+		if (!need_post) {
+			jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
+			if (jreg & 0x80)
+				ast->tx_chip = AST_TX_SIL164;
+		}
+	} else if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) {
 		/*
 		 * On AST GEN4+, look the configuration set by the SoC in
 		 * the SOC scratch register #1 bits 11:8 (interestingly marked
-- 
2.47.1


  parent reply	other threads:[~2025-01-17 10:35 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-17 10:29 [PATCH 0/8] drm/ast: Reorganize TX-chip detection and init Thomas Zimmermann
2025-01-17 10:29 ` [PATCH 1/8] drm/ast: Detect wide-screen support before creating modeset pipeline Thomas Zimmermann
2025-01-20 10:34   ` Jocelyn Falempe
2025-01-17 10:29 ` [PATCH 2/8] drm/ast: Detect DRAM before TX-chip Thomas Zimmermann
2025-01-20 10:35   ` Jocelyn Falempe
2025-01-17 10:29 ` [PATCH 3/8] drm/ast: Refactor ast_post_gpu() by Gen Thomas Zimmermann
2025-01-20 10:35   ` Jocelyn Falempe
2025-01-17 10:29 ` [PATCH 4/8] drm/ast: Initialize ASTDP in ast_post_gpu() Thomas Zimmermann
2025-01-20 10:37   ` Jocelyn Falempe
2025-01-17 10:29 ` Thomas Zimmermann [this message]
2025-01-20 10:37   ` [PATCH 5/8] drm/ast: Hide Gens 1 to 3 TX detection in branch Jocelyn Falempe
2025-01-17 10:29 ` [PATCH 6/8] drm/ast: Align Gen1 DVO detection to register manual Thomas Zimmermann
2025-01-20 10:37   ` Jocelyn Falempe
2025-01-17 10:29 ` [PATCH 7/8] drm/ast: Merge TX-chip detection code for Gen4 and later Thomas Zimmermann
2025-01-20 10:37   ` Jocelyn Falempe
2025-01-17 10:29 ` [PATCH 8/8] drm/ast: Only warn about unsupported TX chips on " Thomas Zimmermann
2025-01-20 10:37   ` Jocelyn Falempe
2025-01-21 13:21     ` Thomas Zimmermann

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