From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Hervé Poussineau" <hpoussin@reactos.org>,
"Aleksandar Rikalo" <arikalo@gmail.com>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Bernhard Beschow" <shentey@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Huacai Chen" <chenhuacai@kernel.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH 3/6] target/mips: Initialize CPU-specific timer/IRQs once in DeviceRealize
Date: Tue, 21 Jan 2025 17:18:14 +0100 [thread overview]
Message-ID: <20250121161817.33654-4-philmd@linaro.org> (raw)
In-Reply-To: <20250121161817.33654-1-philmd@linaro.org>
The MIPS timer and IRQs are tied to the CPU. Creating them outside
in board code isn't correct. Do it once in the DeviceRealize() handler.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/mips/cps.c | 4 ----
hw/mips/fuloong2e.c | 4 ----
hw/mips/jazz.c | 4 ----
hw/mips/loongson3_virt.c | 4 ----
hw/mips/malta.c | 4 ----
hw/mips/mipssim.c | 4 ----
target/mips/cpu.c | 5 +++++
7 files changed, 5 insertions(+), 24 deletions(-)
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 0d8cbdc8924..f85fb4458af 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -91,10 +91,6 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
return;
}
- /* Init internal devices */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
-
if (cpu_mips_itu_supported(env)) {
itu_present = true;
/* Attach ITC Tag to the VP */
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 160ceb769dc..9a638f596bd 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -277,10 +277,6 @@ static void mips_fuloong2e_init(MachineState *machine)
}
}
- /* Init internal devices */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
-
/* North bridge, Bonito --> IP2 */
pci_bus = bonito_init(env->irq[2]);
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index c89610639a9..ce4a702aa53 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -259,10 +259,6 @@ static void mips_jazz_init(MachineState *machine,
exit(1);
}
- /* Init CPU internal devices */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
-
/* Chipset */
rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
sysbus = SYS_BUS_DEVICE(rc4030);
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
index f3cc7a8376f..91070824bbe 100644
--- a/hw/mips/loongson3_virt.c
+++ b/hw/mips/loongson3_virt.c
@@ -568,10 +568,6 @@ static void mips_loongson3_virt_init(MachineState *machine)
/* init CPUs */
cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false);
-
- /* Init internal devices */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
qemu_register_reset(main_cpu_reset, cpu);
if (!kvm_enabled()) {
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 4e9cccaa347..ac3b16229c8 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1037,10 +1037,6 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
for (i = 0; i < ms->smp.cpus; i++) {
cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk,
TARGET_BIG_ENDIAN);
-
- /* Init internal devices */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
qemu_register_reset(main_cpu_reset, cpu);
}
diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c
index a294779a82b..d4b3b043053 100644
--- a/hw/mips/mipssim.c
+++ b/hw/mips/mipssim.c
@@ -203,10 +203,6 @@ mips_mipssim_init(MachineState *machine)
reset_info->vector = load_kernel();
}
- /* Init CPU internal devices. */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
-
/*
* Register 64 KB of ISA IO space at 0x1fd00000. But without interrupts
* (except for the hardcoded serial port interrupt) -device cannot work,
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 028a3c91afb..95df8985bc6 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -476,6 +476,11 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
fpu_init(env, env->cpu_model);
mvp_init(env);
+ /* Init internal devices */
+#ifndef CONFIG_USER_ONLY
+ cpu_mips_irq_init_cpu(cpu);
+ cpu_mips_clock_init(cpu);
+#endif
if (!clock_get(cpu->clock)) {
#ifndef CONFIG_USER_ONLY
if (!qtest_enabled()) {
--
2.47.1
next prev parent reply other threads:[~2025-01-21 16:18 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-21 16:18 [PATCH 0/6] target/mips: Convert legacy qemu_allocate_irqs() to qemu_init_irq() Philippe Mathieu-Daudé
2025-01-21 16:18 ` [PATCH 1/6] hw/pci-host/bonito: Expose output IRQ as QDev GPIO Philippe Mathieu-Daudé
2025-01-21 16:18 ` [PATCH 2/6] target/mips: Create clock *after* accelerator vCPU is realized Philippe Mathieu-Daudé
2025-01-21 16:18 ` Philippe Mathieu-Daudé [this message]
2025-01-21 23:07 ` [PATCH 3/6] target/mips: Initialize CPU-specific timer/IRQs once in DeviceRealize Richard Henderson
2025-01-21 16:18 ` [PATCH 4/6] target/mips: Pass env to cpu_mips_clock_init() Philippe Mathieu-Daudé
2025-01-21 16:18 ` [PATCH 5/6] target/mips: Move CPU timer from hw/mips/ to target/mips/system/ Philippe Mathieu-Daudé
2025-01-21 23:08 ` Richard Henderson
2025-01-21 16:18 ` [PATCH 6/6] target/mips: Allocate CPU IRQs within CPUMIPSState Philippe Mathieu-Daudé
2025-01-21 16:20 ` Philippe Mathieu-Daudé
2025-01-21 23:12 ` Richard Henderson
2025-01-21 16:42 ` [PATCH 0/6] target/mips: Convert legacy qemu_allocate_irqs() to qemu_init_irq() Philippe Mathieu-Daudé
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