Re: [PATCH 6/6] target/mips: Allocate CPU IRQs within CPUMIPSState

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

On 21/1/25 17:18, Philippe Mathieu-Daudé wrote:
> There are always 8 IRQs created with a MIPS CPU.
> Allocate their state once in CPUMIPSState, initialize
> them in place in cpu_mips_irq_init_cpu(). Update hw/ uses.
> 
> Move cpu_mips_irq_init_cpu() declaration from "cpu.h"
> to "internal.h", as it shouldn't be accessible from hw/.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/mips/cpu.h               |  4 ++--
>   target/mips/internal.h          |  2 ++
>   hw/intc/mips_gic.c              |  4 ++--
>   hw/mips/fuloong2e.c             |  4 ++--
>   hw/mips/jazz.c                  |  6 +++---
>   hw/mips/loongson3_virt.c        |  4 ++--
>   hw/mips/malta.c                 |  4 ++--
>   hw/mips/mipssim.c               |  4 ++--
>   target/mips/system/cp0_timer.c  |  4 ++--
>   target/mips/system/interrupts.c | 11 +++--------
>   10 files changed, 22 insertions(+), 25 deletions(-)
> 
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index e5767ea9cf3..25a19b61913 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -8,6 +8,7 @@
>   #endif
>   #include "fpu/softfloat-types.h"
>   #include "hw/clock.h"
> +#include "hw/irq.h"
>   #include "mips-defs.h"
>   
>   typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
> @@ -1177,7 +1178,7 @@ typedef struct CPUArchState {
>       CPUMIPSMVPContext *mvp;
>   #if !defined(CONFIG_USER_ONLY)
>       CPUMIPSTLBContext *tlb;
> -    qemu_irq irq[8];
> +    IRQState irq[8];
>       MemoryRegion *itc_tag; /* ITC Configuration Tags */


> diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
> index 9a638f596bd..ccebc56adec 100644
> --- a/hw/mips/fuloong2e.c
> +++ b/hw/mips/fuloong2e.c
> @@ -278,7 +278,7 @@ static void mips_fuloong2e_init(MachineState *machine)
>       }
>   
>       /* North bridge, Bonito --> IP2 */
> -    pci_bus = bonito_init(env->irq[2]);
> +    pci_bus = bonito_init(&env->irq[2]);

Orthogonal, but thinking of heterogeneous emulation, at some point
we'll need to expose vCPU IRQs as QDev GPIO.