* [PULL 00/36] target-arm queue
@ 2020-03-12 16:44 Peter Maydell
2020-03-12 20:32 ` Peter Maydell
0 siblings, 1 reply; 55+ messages in thread
From: Peter Maydell @ 2020-03-12 16:44 UTC (permalink / raw)
To: qemu-devel
arm queue; dunno if this will be the last before softfreeze
or not, but anyway probably the last large one. New orangepi-pc
board model is the big item here.
thanks
-- PMM
The following changes since commit 67d9ef7d541c3d21a25796c51c26da096a433565:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-docs-20200312' into staging (2020-03-12 15:20:52 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200312
for you to fetch changes up to aca53be34ac3e7cac5f39396a51a338860a5a837:
target/arm: kvm: Inject events at the last stage of sync (2020-03-12 16:31:10 +0000)
----------------------------------------------------------------
target-arm queue:
* Fix various bugs that might result in an assert() due to
incorrect hflags for M-profile CPUs
* Fix Aspeed SMC Controller user-mode select handling
* Report correct (with-tag) address in fault address register
when TBI is enabled
* cubieboard: make sure SOC object isn't leaked
* fsl-imx25: Wire up eSDHC controllers
* fsl-imx25: Wire up USB controllers
* New board model: orangepi-pc (OrangePi PC)
* ARM/KVM: if user doesn't select GIC version and the
host kernel can only provide GICv3, use that, rather
than defaulting to "fail because GICv2 isn't possible"
* kvm: Only do KVM_SET_VCPU_EVENTS at the last stage of sync
----------------------------------------------------------------
Beata Michalska (1):
target/arm: kvm: Inject events at the last stage of sync
Cédric Le Goater (2):
aspeed/smc: Add some tracing
aspeed/smc: Fix User mode select/unselect scheme
Eric Auger (6):
hw/arm/virt: Document 'max' value in gic-version property description
hw/arm/virt: Introduce VirtGICType enum type
hw/arm/virt: Introduce finalize_gic_version()
target/arm/kvm: Let kvm_arm_vgic_probe() return a bitmap
hw/arm/virt: kvm: Restructure finalize_gic_version()
hw/arm/virt: kvm: allow gicv3 by default if v2 cannot work
Guenter Roeck (2):
hw/arm/fsl-imx25: Wire up eSDHC controllers
hw/arm/fsl-imx25: Wire up USB controllers
Igor Mammedov (1):
hw/arm/cubieboard: make sure SOC object isn't leaked
Niek Linnenbank (13):
hw/arm: add Allwinner H3 System-on-Chip
hw/arm: add Xunlong Orange Pi PC machine
hw/arm/allwinner-h3: add Clock Control Unit
hw/arm/allwinner-h3: add USB host controller
hw/arm/allwinner-h3: add System Control module
hw/arm/allwinner: add CPU Configuration module
hw/arm/allwinner: add Security Identifier device
hw/arm/allwinner: add SD/MMC host controller
hw/arm/allwinner-h3: add EMAC ethernet device
hw/arm/allwinner-h3: add Boot ROM support
hw/arm/allwinner-h3: add SDRAM controller device
hw/arm/allwinner: add RTC device support
docs: add Orange Pi PC document
Peter Maydell (4):
hw/intc/armv7m_nvic: Rebuild hflags on reset
target/arm: Update hflags in trans_CPS_v7m()
target/arm: Recalculate hflags correctly after writes to CONTROL
target/arm: Fix some comment typos
Philippe Mathieu-Daudé (5):
tests/boot_linux_console: Add a quick test for the OrangePi PC board
tests/boot_linux_console: Add initrd test for the Orange Pi PC board
tests/boot_linux_console: Add a SD card test for the OrangePi PC board
tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC
tests/boot_linux_console: Test booting NetBSD via U-Boot on OrangePi PC
Richard Henderson (2):
target/arm: Check addresses for disabled regimes
target/arm: Disable clean_data_tbi for system mode
Makefile.objs | 1 +
hw/arm/Makefile.objs | 1 +
hw/misc/Makefile.objs | 5 +
hw/net/Makefile.objs | 1 +
hw/rtc/Makefile.objs | 1 +
hw/sd/Makefile.objs | 1 +
hw/usb/hcd-ehci.h | 1 +
include/hw/arm/allwinner-a10.h | 4 +
include/hw/arm/allwinner-h3.h | 161 ++++++
include/hw/arm/fsl-imx25.h | 18 +
include/hw/arm/virt.h | 12 +-
include/hw/misc/allwinner-cpucfg.h | 52 ++
include/hw/misc/allwinner-h3-ccu.h | 66 +++
include/hw/misc/allwinner-h3-dramc.h | 106 ++++
include/hw/misc/allwinner-h3-sysctrl.h | 67 +++
include/hw/misc/allwinner-sid.h | 60 +++
include/hw/net/allwinner-sun8i-emac.h | 99 ++++
include/hw/rtc/allwinner-rtc.h | 134 +++++
include/hw/sd/allwinner-sdhost.h | 135 +++++
target/arm/helper.h | 1 +
target/arm/kvm_arm.h | 3 +
hw/arm/allwinner-a10.c | 19 +
hw/arm/allwinner-h3.c | 465 ++++++++++++++++++
hw/arm/cubieboard.c | 18 +
hw/arm/fsl-imx25.c | 56 +++
hw/arm/imx25_pdk.c | 16 +
hw/arm/orangepi.c | 130 +++++
hw/arm/virt.c | 145 ++++--
hw/intc/armv7m_nvic.c | 6 +
hw/misc/allwinner-cpucfg.c | 282 +++++++++++
hw/misc/allwinner-h3-ccu.c | 242 +++++++++
hw/misc/allwinner-h3-dramc.c | 358 ++++++++++++++
hw/misc/allwinner-h3-sysctrl.c | 140 ++++++
hw/misc/allwinner-sid.c | 168 +++++++
hw/net/allwinner-sun8i-emac.c | 871 +++++++++++++++++++++++++++++++++
hw/rtc/allwinner-rtc.c | 411 ++++++++++++++++
hw/sd/allwinner-sdhost.c | 854 ++++++++++++++++++++++++++++++++
hw/ssi/aspeed_smc.c | 56 ++-
hw/usb/hcd-ehci-sysbus.c | 17 +
target/arm/helper.c | 49 +-
target/arm/kvm.c | 14 +-
target/arm/kvm32.c | 15 +-
target/arm/kvm64.c | 15 +-
target/arm/translate-a64.c | 11 +
target/arm/translate.c | 14 +-
MAINTAINERS | 9 +
default-configs/arm-softmmu.mak | 1 +
docs/system/arm/orangepi.rst | 253 ++++++++++
docs/system/target-arm.rst | 2 +
hw/arm/Kconfig | 12 +
hw/misc/trace-events | 19 +
hw/net/Kconfig | 3 +
hw/net/trace-events | 10 +
hw/rtc/trace-events | 4 +
hw/sd/trace-events | 7 +
hw/ssi/trace-events | 10 +
tests/acceptance/boot_linux_console.py | 230 +++++++++
57 files changed, 5787 insertions(+), 74 deletions(-)
create mode 100644 include/hw/arm/allwinner-h3.h
create mode 100644 include/hw/misc/allwinner-cpucfg.h
create mode 100644 include/hw/misc/allwinner-h3-ccu.h
create mode 100644 include/hw/misc/allwinner-h3-dramc.h
create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h
create mode 100644 include/hw/misc/allwinner-sid.h
create mode 100644 include/hw/net/allwinner-sun8i-emac.h
create mode 100644 include/hw/rtc/allwinner-rtc.h
create mode 100644 include/hw/sd/allwinner-sdhost.h
create mode 100644 hw/arm/allwinner-h3.c
create mode 100644 hw/arm/orangepi.c
create mode 100644 hw/misc/allwinner-cpucfg.c
create mode 100644 hw/misc/allwinner-h3-ccu.c
create mode 100644 hw/misc/allwinner-h3-dramc.c
create mode 100644 hw/misc/allwinner-h3-sysctrl.c
create mode 100644 hw/misc/allwinner-sid.c
create mode 100644 hw/net/allwinner-sun8i-emac.c
create mode 100644 hw/rtc/allwinner-rtc.c
create mode 100644 hw/sd/allwinner-sdhost.c
create mode 100644 docs/system/arm/orangepi.rst
create mode 100644 hw/ssi/trace-events
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/36] target-arm queue
2020-03-12 16:44 Peter Maydell
@ 2020-03-12 20:32 ` Peter Maydell
0 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2020-03-12 20:32 UTC (permalink / raw)
To: QEMU Developers
On Thu, 12 Mar 2020 at 16:45, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> arm queue; dunno if this will be the last before softfreeze
> or not, but anyway probably the last large one. New orangepi-pc
> board model is the big item here.
>
> thanks
> -- PMM
>
> The following changes since commit 67d9ef7d541c3d21a25796c51c26da096a433565:
>
> Merge remote-tracking branch 'remotes/pmaydell/tags/pull-docs-20200312' into staging (2020-03-12 15:20:52 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200312
>
> for you to fetch changes up to aca53be34ac3e7cac5f39396a51a338860a5a837:
>
> target/arm: kvm: Inject events at the last stage of sync (2020-03-12 16:31:10 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Fix various bugs that might result in an assert() due to
> incorrect hflags for M-profile CPUs
> * Fix Aspeed SMC Controller user-mode select handling
> * Report correct (with-tag) address in fault address register
> when TBI is enabled
> * cubieboard: make sure SOC object isn't leaked
> * fsl-imx25: Wire up eSDHC controllers
> * fsl-imx25: Wire up USB controllers
> * New board model: orangepi-pc (OrangePi PC)
> * ARM/KVM: if user doesn't select GIC version and the
> host kernel can only provide GICv3, use that, rather
> than defaulting to "fail because GICv2 isn't possible"
> * kvm: Only do KVM_SET_VCPU_EVENTS at the last stage of sync
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PULL 00/36] target-arm queue
@ 2020-09-14 14:06 Peter Maydell
0 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2020-09-14 14:06 UTC (permalink / raw)
To: qemu-devel
Nuvoton new board models, and some more minor stuff. I also put
in the deprecation patches for unicore32 and lm32.
thanks
-- PMM
The following changes since commit a68694cd1f3e5448cca814ff39b871f9ebd71ed5:
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200914' into staging (2020-09-14 12:18:58 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200914
for you to fetch changes up to dd44ae00fc5342ed99acb68ec3508f76a71d523a:
MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller (2020-09-14 14:27:08 +0100)
----------------------------------------------------------------
target-arm queue:
* hw/misc/a9scu: Do not allow invalid CPU count
* hw/misc/a9scu: Minor cleanups
* hw/timer/armv7m_systick: assert that board code set system_clock_scale
* decodetree: Improve identifier matching
* target/arm: Clean up neon fp insn size field decode
* target/arm: Remove KVM support for 32-bit Arm hosts
* hw/arm/mps2: New board models mps2-an386, mps2-an500
* Deprecate Unicore32 port
* Deprecate lm32 port
* target/arm: Count PMU events when MDCR.SPME is set
* hw/arm: versal-virt: Correct the tx/rx GEM clocks
* New Nuvoton iBMC board models npcm750-evb, quanta-gsj
* xlnx-zynqmp: implement ZynqMP CAN controllers
----------------------------------------------------------------
Aaron Lindsay (1):
target/arm: Count PMU events when MDCR.SPME is set
Edgar E. Iglesias (1):
hw/arm: versal-virt: Correct the tx/rx GEM clocks
Havard Skinnemoen (14):
hw/misc: Add NPCM7xx System Global Control Registers device model
hw/misc: Add NPCM7xx Clock Controller device model
hw/timer: Add NPCM7xx Timer device model
hw/arm: Add NPCM730 and NPCM750 SoC models
hw/arm: Add two NPCM7xx-based machines
roms: Add virtual Boot ROM for NPCM7xx SoCs
hw/arm: Load -bios image as a boot ROM for npcm7xx
hw/nvram: NPCM7xx OTP device model
hw/mem: Stubbed out NPCM7xx Memory Controller model
hw/ssi: NPCM7xx Flash Interface Unit device model
hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
hw/arm/npcm7xx: add board setup stub for CPU and UART clocks
docs/system: Add Nuvoton machine documentation
tests/acceptance: console boot tests for quanta-gsj
Peter Maydell (11):
hw/timer/armv7m_systick: assert that board code set system_clock_scale
target/arm: Convert Neon 3-same-fp size field to MO_* in decode
target/arm: Convert Neon VCVT fp size field to MO_* in decode
target/arm: Convert VCMLA, VCADD size field to MO_* in decode
target/arm: Remove KVM support for 32-bit Arm hosts
target/arm: Remove no-longer-reachable 32-bit KVM code
hw/arm/mps2: New board model mps2-an386
hw/arm/mps2: New board model mps2-an500
docs/system/arm/mps2.rst: Make board list consistent
Deprecate Unicore32 port
Deprecate lm32 port
Philippe Mathieu-Daudé (4):
hw/misc/a9scu: Do not allow invalid CPU count
hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fields
hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields
hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP)
Richard Henderson (1):
decodetree: Improve identifier matching
Vikram Garhwal (4):
hw/net/can: Introduce Xilinx ZynqMP CAN controller
xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers
tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller
MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller
docs/system/arm/mps2.rst | 20 +-
docs/system/arm/nuvoton.rst | 92 +++
docs/system/deprecated.rst | 32 +-
docs/system/target-arm.rst | 1 +
configure | 2 +-
default-configs/arm-softmmu.mak | 1 +
include/hw/arm/npcm7xx.h | 112 +++
include/hw/arm/xlnx-zynqmp.h | 8 +
include/hw/mem/npcm7xx_mc.h | 36 +
include/hw/misc/npcm7xx_clk.h | 48 ++
include/hw/misc/npcm7xx_gcr.h | 43 ++
include/hw/net/xlnx-zynqmp-can.h | 78 +++
include/hw/nvram/npcm7xx_otp.h | 79 +++
include/hw/ssi/npcm7xx_fiu.h | 73 ++
include/hw/timer/npcm7xx_timer.h | 78 +++
target/arm/kvm-consts.h | 7 -
target/arm/kvm_arm.h | 6 -
target/arm/neon-dp.decode | 18 +-
target/arm/neon-shared.decode | 18 +-
tests/decode/succ_ident1.decode | 7 +
hw/arm/mps2.c | 97 ++-
hw/arm/npcm7xx.c | 532 +++++++++++++++
hw/arm/npcm7xx_boards.c | 197 ++++++
hw/arm/xlnx-versal-virt.c | 2 +-
hw/arm/xlnx-zcu102.c | 20 +
hw/arm/xlnx-zynqmp.c | 34 +
hw/mem/npcm7xx_mc.c | 84 +++
hw/misc/a9scu.c | 59 +-
hw/misc/npcm7xx_clk.c | 266 ++++++++
hw/misc/npcm7xx_gcr.c | 269 ++++++++
hw/net/can/xlnx-zynqmp-can.c | 1165 ++++++++++++++++++++++++++++++++
hw/nvram/npcm7xx_otp.c | 440 ++++++++++++
hw/ssi/npcm7xx_fiu.c | 572 ++++++++++++++++
hw/timer/armv7m_systick.c | 8 +
hw/timer/npcm7xx_timer.c | 543 +++++++++++++++
target/arm/cpu.c | 101 ++-
target/arm/helper.c | 2 +-
target/arm/kvm.c | 7 -
target/arm/kvm32.c | 595 ----------------
tests/qtest/xlnx-can-test.c | 359 ++++++++++
.gitmodules | 3 +
MAINTAINERS | 18 +
hw/arm/Kconfig | 9 +
hw/arm/meson.build | 1 +
hw/mem/meson.build | 1 +
hw/misc/meson.build | 4 +
hw/misc/trace-events | 8 +
hw/net/can/meson.build | 1 +
hw/nvram/meson.build | 1 +
hw/ssi/meson.build | 1 +
hw/ssi/trace-events | 11 +
hw/timer/meson.build | 1 +
hw/timer/trace-events | 5 +
pc-bios/README | 6 +
pc-bios/meson.build | 1 +
pc-bios/npcm7xx_bootrom.bin | Bin 0 -> 768 bytes
roms/Makefile | 7 +
roms/vbootrom | 1 +
scripts/decodetree.py | 46 +-
target/arm/meson.build | 5 +-
target/arm/translate-neon.c.inc | 42 +-
tests/acceptance/boot_linux_console.py | 83 +++
tests/qtest/meson.build | 1 +
63 files changed, 5584 insertions(+), 783 deletions(-)
create mode 100644 docs/system/arm/nuvoton.rst
create mode 100644 include/hw/arm/npcm7xx.h
create mode 100644 include/hw/mem/npcm7xx_mc.h
create mode 100644 include/hw/misc/npcm7xx_clk.h
create mode 100644 include/hw/misc/npcm7xx_gcr.h
create mode 100644 include/hw/net/xlnx-zynqmp-can.h
create mode 100644 include/hw/nvram/npcm7xx_otp.h
create mode 100644 include/hw/ssi/npcm7xx_fiu.h
create mode 100644 include/hw/timer/npcm7xx_timer.h
create mode 100644 tests/decode/succ_ident1.decode
create mode 100644 hw/arm/npcm7xx.c
create mode 100644 hw/arm/npcm7xx_boards.c
create mode 100644 hw/mem/npcm7xx_mc.c
create mode 100644 hw/misc/npcm7xx_clk.c
create mode 100644 hw/misc/npcm7xx_gcr.c
create mode 100644 hw/net/can/xlnx-zynqmp-can.c
create mode 100644 hw/nvram/npcm7xx_otp.c
create mode 100644 hw/ssi/npcm7xx_fiu.c
create mode 100644 hw/timer/npcm7xx_timer.c
delete mode 100644 target/arm/kvm32.c
create mode 100644 tests/qtest/xlnx-can-test.c
create mode 100644 pc-bios/npcm7xx_bootrom.bin
create mode 160000 roms/vbootrom
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PULL 00/36] target-arm queue
@ 2020-12-10 11:47 Peter Maydell
2020-12-10 12:51 ` Peter Maydell
0 siblings, 1 reply; 55+ messages in thread
From: Peter Maydell @ 2020-12-10 11:47 UTC (permalink / raw)
To: qemu-devel
First pullreq for 6.0: mostly my v8.1M work, plus some other
bits and pieces. (I still have a lot of stuff in my to-review
folder, which I may or may not get to before the Christmas break...)
thanks
-- PMM
The following changes since commit 5e7b204dbfae9a562fc73684986f936b97f63877:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-12-09 20:08:54 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201210
for you to fetch changes up to 71f916be1c7e9ede0e37d9cabc781b5a9e8638ff:
hw/arm/armv7m: Correct typo in QOM object name (2020-12-10 11:44:56 +0000)
----------------------------------------------------------------
target-arm queue:
* hw/arm/smmuv3: Fix up L1STD_SPAN decoding
* xlnx-zynqmp: Support Xilinx ZynqMP CAN controllers
* sbsa-ref: allow to use Cortex-A53/57/72 cpus
* Various minor code cleanups
* hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
* Implement more pieces of ARMv8.1M support
----------------------------------------------------------------
Alex Chen (4):
i.MX25: Fix bad printf format specifiers
i.MX31: Fix bad printf format specifiers
i.MX6: Fix bad printf format specifiers
i.MX6ul: Fix bad printf format specifiers
Havard Skinnemoen (1):
tests/qtest/npcm7xx_rng-test: dump random data on failure
Kunkun Jiang (1):
hw/arm/smmuv3: Fix up L1STD_SPAN decoding
Marcin Juszkiewicz (1):
sbsa-ref: allow to use Cortex-A53/57/72 cpus
Peter Maydell (25):
hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
target/arm: Implement v8.1M PXN extension
target/arm: Don't clobber ID_PFR1.Security on M-profile cores
target/arm: Implement VSCCLRM insn
target/arm: Implement CLRM instruction
target/arm: Enforce M-profile VMRS/VMSR register restrictions
target/arm: Refactor M-profile VMSR/VMRS handling
target/arm: Move general-use constant expanders up in translate.c
target/arm: Implement VLDR/VSTR system register
target/arm: Implement M-profile FPSCR_nzcvqc
target/arm: Use new FPCR_NZCV_MASK constant
target/arm: Factor out preserve-fp-state from full_vfp_access_check()
target/arm: Implement FPCXT_S fp system register
hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M
target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry
target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures
target/arm: Implement v8.1M REVIDR register
target/arm: Implement new v8.1M NOCP check for exception return
target/arm: Implement new v8.1M VLLDM and VLSTM encodings
hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit
target/arm: Implement CCR_S.TRD behaviour for SG insns
hw/intc/armv7m_nvic: Fix "return from inactive handler" check
target/arm: Implement M-profile "minimal RAS implementation"
hw/intc/armv7m_nvic: Implement read/write for RAS register block
hw/arm/armv7m: Correct typo in QOM object name
Vikram Garhwal (4):
hw/net/can: Introduce Xilinx ZynqMP CAN controller
xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers
tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller
MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller
meson.build | 1 +
hw/arm/smmuv3-internal.h | 2 +-
hw/net/can/trace.h | 1 +
include/hw/arm/xlnx-zynqmp.h | 8 +
include/hw/intc/armv7m_nvic.h | 2 +
include/hw/net/xlnx-zynqmp-can.h | 78 +++
target/arm/cpu.h | 46 ++
target/arm/m-nocp.decode | 10 +-
target/arm/t32.decode | 10 +-
target/arm/vfp.decode | 14 +
hw/arm/armv7m.c | 4 +-
hw/arm/sbsa-ref.c | 23 +-
hw/arm/xlnx-zcu102.c | 20 +
hw/arm/xlnx-zynqmp.c | 34 ++
hw/intc/armv7m_nvic.c | 246 ++++++--
hw/misc/imx25_ccm.c | 12 +-
hw/misc/imx31_ccm.c | 14 +-
hw/misc/imx6_ccm.c | 20 +-
hw/misc/imx6_src.c | 2 +-
hw/misc/imx6ul_ccm.c | 4 +-
hw/misc/imx_ccm.c | 4 +-
hw/net/can/xlnx-zynqmp-can.c | 1161 ++++++++++++++++++++++++++++++++++++++
target/arm/cpu.c | 5 +-
target/arm/helper.c | 7 +-
target/arm/m_helper.c | 130 ++++-
target/arm/translate.c | 105 +++-
tests/qtest/npcm7xx_rng-test.c | 12 +
tests/qtest/xlnx-can-test.c | 360 ++++++++++++
MAINTAINERS | 8 +
hw/Kconfig | 1 +
hw/net/can/meson.build | 1 +
hw/net/can/trace-events | 9 +
target/arm/translate-vfp.c.inc | 511 ++++++++++++++++-
tests/qtest/meson.build | 1 +
34 files changed, 2713 insertions(+), 153 deletions(-)
create mode 100644 hw/net/can/trace.h
create mode 100644 include/hw/net/xlnx-zynqmp-can.h
create mode 100644 hw/net/can/xlnx-zynqmp-can.c
create mode 100644 tests/qtest/xlnx-can-test.c
create mode 100644 hw/net/can/trace-events
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/36] target-arm queue
2020-12-10 11:47 Peter Maydell
@ 2020-12-10 12:51 ` Peter Maydell
0 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2020-12-10 12:51 UTC (permalink / raw)
To: QEMU Developers
On Thu, 10 Dec 2020 at 11:47, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> First pullreq for 6.0: mostly my v8.1M work, plus some other
> bits and pieces. (I still have a lot of stuff in my to-review
> folder, which I may or may not get to before the Christmas break...)
>
> thanks
> -- PMM
>
> The following changes since commit 5e7b204dbfae9a562fc73684986f936b97f63877:
>
> Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-12-09 20:08:54 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201210
>
> for you to fetch changes up to 71f916be1c7e9ede0e37d9cabc781b5a9e8638ff:
>
> hw/arm/armv7m: Correct typo in QOM object name (2020-12-10 11:44:56 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * hw/arm/smmuv3: Fix up L1STD_SPAN decoding
> * xlnx-zynqmp: Support Xilinx ZynqMP CAN controllers
> * sbsa-ref: allow to use Cortex-A53/57/72 cpus
> * Various minor code cleanups
> * hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
> * Implement more pieces of ARMv8.1M support
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PULL 00/36] target-arm queue
@ 2024-01-26 14:33 Peter Maydell
2024-01-27 13:00 ` Peter Maydell
0 siblings, 1 reply; 55+ messages in thread
From: Peter Maydell @ 2024-01-26 14:33 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 5bab95dc74d43bbb28c6a96d24c810a664432057:
Merge tag 'pull-request-2024-01-24' of https://gitlab.com/thuth/qemu into staging (2024-01-25 12:33:42 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240126
for you to fetch changes up to 5e6be95ed1578c7cfac2082b39384d99fd912508:
hw/arm: add PCIe to Freescale i.MX6 (2024-01-26 12:23:04 +0000)
----------------------------------------------------------------
target-arm queue:
* Fix VNCR fault detection logic
* Fix A64 scalar SQSHRN and SQRSHRN
* Fix incorrect aa64_tidcp1 feature check
* hw/arm/virt.c: Remove newline from error_report() string
* hw/arm/musicpal: Convert to qemu_add_kbd_event_handler()
* hw/arm/allwinner-a10: Unconditionally map the USB Host controllers
* hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller
* hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board
* hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board
* hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board
* arm: various include header cleanups
* cleanups to allow some files to be built only once
* fsl-imx6ul: Add various missing unimplemented devices
* docs/system/arm/virt.rst: Add note on CPU features off by default
* hw/char/imx_serial: Implement receive FIFO and ageing timer
* target/xtensa: fix OOB TLB entry access
* bswap.h: Fix const_le64() macro
* hw/arm: add PCIe to Freescale i.MX6
----------------------------------------------------------------
Guenter Roeck (4):
hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board
hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board
hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board
fsl-imx6ul: Add various missing unimplemented devices
Gustavo Romero (1):
docs/system/arm/virt.rst: Add note on CPU features off by default
Max Filippov (1):
target/xtensa: fix OOB TLB entry access
Nikita Ostrenkov (1):
hw/arm: add PCIe to Freescale i.MX6
Peter Maydell (6):
target/arm: Fix VNCR fault detection logic
hw/arm/virt.c: Remove newline from error_report() string
hw/arm/musicpal: Convert to qemu_add_kbd_event_handler()
target/arm: Fix A64 scalar SQSHRN and SQRSHRN
bswap.h: Fix const_le64() macro
target/arm: Fix incorrect aa64_tidcp1 feature check
Philippe Mathieu-Daudé (20):
hw/arm/allwinner-a10: Unconditionally map the USB Host controllers
hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller
hw/arm/exynos4210: Include missing 'exec/tswap.h' header
hw/arm/xilinx_zynq: Include missing 'exec/tswap.h' header
hw/arm/smmuv3: Include missing 'hw/registerfields.h' header
hw/arm/xlnx-versal: Include missing 'cpu.h' header
target/arm/cpu-features: Include missing 'hw/registerfields.h' header
target/arm/cpregs: Include missing 'hw/registerfields.h' header
target/arm/cpregs: Include missing 'kvm-consts.h' header
target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header
target/arm: Declare ARM_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'
hw/cpu/a9mpcore: Build it only once
hw/misc/xlnx-versal-crl: Include generic 'cpu-qom.h' instead of 'cpu.h'
hw/misc/xlnx-versal-crl: Build it only once
target/arm: Expose M-profile register bank index definitions
hw/arm/armv7m: Make 'hw/intc/armv7m_nvic.h' a target agnostic header
target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header
target/arm: Move e2h_access() helper around
target/arm: Move GTimer definitions to new 'gtimer.h' header
hw/arm: Build various units only once
Rayhan Faizel (1):
hw/char/imx_serial: Implement receive FIFO and ageing timer
Richard Henderson (2):
target/arm: Rename arm_cpu_mp_affinity
target/arm: Create arm_cpu_mp_affinity
docs/system/arm/bananapi_m2u.rst | 5 +-
docs/system/arm/virt.rst | 13 ++++
hw/arm/smmuv3-internal.h | 1 +
include/hw/arm/allwinner-r40.h | 15 +++++
include/hw/arm/fsl-imx6.h | 44 +++++++------
include/hw/arm/fsl-imx6ul.h | 2 +
include/hw/arm/xlnx-versal.h | 1 +
include/hw/char/imx_serial.h | 20 +++++-
include/hw/intc/armv7m_nvic.h | 2 +-
include/hw/misc/xlnx-versal-crl.h | 2 +-
include/qemu/bswap.h | 16 ++---
target/arm/cpregs.h | 3 +
target/arm/cpu-features.h | 4 +-
target/arm/cpu-qom.h | 24 +++++++
target/arm/cpu.h | 34 +---------
target/arm/gtimer.h | 21 ++++++
target/arm/multiprocessing.h | 16 +++++
hw/arm/allwinner-a10.c | 50 ++++++--------
hw/arm/allwinner-h3.c | 2 +
hw/arm/allwinner-r40.c | 69 +++++++++++++++++++-
hw/arm/armv7m.c | 2 +
hw/arm/aspeed_ast2400.c | 1 +
hw/arm/aspeed_ast2600.c | 1 +
hw/arm/bcm2836.c | 2 +
hw/arm/collie.c | 1 -
hw/arm/exynos4210.c | 2 +
hw/arm/fsl-imx25.c | 1 +
hw/arm/fsl-imx31.c | 1 +
hw/arm/fsl-imx6.c | 26 ++++++++
hw/arm/fsl-imx6ul.c | 31 +++++++++
hw/arm/fsl-imx7.c | 1 +
hw/arm/gumstix.c | 1 -
hw/arm/highbank.c | 1 +
hw/arm/integratorcp.c | 2 +-
hw/arm/mainstone.c | 1 -
hw/arm/musicpal.c | 133 ++++++++++++++++++--------------------
hw/arm/npcm7xx.c | 3 +-
hw/arm/nseries.c | 4 +-
hw/arm/omap1.c | 1 +
hw/arm/omap2.c | 2 +-
hw/arm/omap_sx1.c | 1 -
hw/arm/palm.c | 1 -
hw/arm/realview.c | 1 +
hw/arm/sbsa-ref.c | 4 +-
hw/arm/spitz.c | 1 -
hw/arm/strongarm.c | 2 +-
hw/arm/versatilepb.c | 2 +-
hw/arm/vexpress.c | 2 +-
hw/arm/virt-acpi-build.c | 4 +-
hw/arm/virt.c | 15 +++--
hw/arm/xilinx_zynq.c | 3 +-
hw/arm/xlnx-versal-virt.c | 5 +-
hw/arm/xlnx-versal.c | 2 +
hw/arm/xlnx-zynqmp.c | 2 +
hw/arm/z2.c | 1 -
hw/char/imx_serial.c | 102 +++++++++++++++++++++++++----
hw/cpu/a15mpcore.c | 1 +
hw/cpu/a9mpcore.c | 2 +-
hw/misc/xlnx-versal-crl.c | 5 +-
target/arm/arm-powerctl.c | 3 +-
target/arm/cpu.c | 13 +++-
target/arm/helper.c | 30 +++++----
target/arm/hvf/hvf.c | 6 +-
target/arm/kvm.c | 1 +
target/arm/machine.c | 1 +
target/arm/tcg/psci.c | 3 +-
target/arm/tcg/tlb_helper.c | 2 +-
target/arm/tcg/translate-a64.c | 2 +-
target/xtensa/mmu_helper.c | 47 ++++++++++----
hw/arm/Kconfig | 6 ++
hw/arm/meson.build | 23 +++----
hw/cpu/meson.build | 2 +-
hw/misc/meson.build | 2 +-
73 files changed, 597 insertions(+), 261 deletions(-)
create mode 100644 target/arm/gtimer.h
create mode 100644 target/arm/multiprocessing.h
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/36] target-arm queue
2024-01-26 14:33 Peter Maydell
@ 2024-01-27 13:00 ` Peter Maydell
0 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2024-01-27 13:00 UTC (permalink / raw)
To: qemu-devel
On Fri, 26 Jan 2024 at 14:33, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The following changes since commit 5bab95dc74d43bbb28c6a96d24c810a664432057:
>
> Merge tag 'pull-request-2024-01-24' of https://gitlab.com/thuth/qemu into staging (2024-01-25 12:33:42 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240126
>
> for you to fetch changes up to 5e6be95ed1578c7cfac2082b39384d99fd912508:
>
> hw/arm: add PCIe to Freescale i.MX6 (2024-01-26 12:23:04 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Fix VNCR fault detection logic
> * Fix A64 scalar SQSHRN and SQRSHRN
> * Fix incorrect aa64_tidcp1 feature check
> * hw/arm/virt.c: Remove newline from error_report() string
> * hw/arm/musicpal: Convert to qemu_add_kbd_event_handler()
> * hw/arm/allwinner-a10: Unconditionally map the USB Host controllers
> * hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller
> * hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board
> * hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board
> * hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board
> * arm: various include header cleanups
> * cleanups to allow some files to be built only once
> * fsl-imx6ul: Add various missing unimplemented devices
> * docs/system/arm/virt.rst: Add note on CPU features off by default
> * hw/char/imx_serial: Implement receive FIFO and ageing timer
> * target/xtensa: fix OOB TLB entry access
> * bswap.h: Fix const_le64() macro
> * hw/arm: add PCIe to Freescale i.MX6
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PULL 00/36] target-arm queue
@ 2024-02-02 15:36 Peter Maydell
2024-02-03 13:27 ` Peter Maydell
0 siblings, 1 reply; 55+ messages in thread
From: Peter Maydell @ 2024-02-02 15:36 UTC (permalink / raw)
To: qemu-devel
The following changes since commit c3709fde5955d13f6d4f86ab46ef3cc2288ca65e:
Merge tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu into staging (2024-02-01 14:42:11 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240202
for you to fetch changes up to f09c2b7ba9908714a3e2f1decd989462536cf731:
hw/arm: Connect SPI Controller to BCM2835 (2024-02-02 13:51:59 +0000)
----------------------------------------------------------------
target/arm: fix exception syndrome for AArch32 bkpt insn
pci, vmbus, adb, s390x/css-bridge: Switch buses to 3-phase reset
system/vl.c: Fix handling of '-serial none -serial something'
target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set
tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array
target/arm: Reinstate "vfp" property on AArch32 CPUs
doc/sphinx/hxtool.py: add optional label argument to SRST directive
hw/arm: Check for CPU types in machine_run_board_init() for various boards
pci-host: designware: Limit value range of iATU viewport register
hw/arm: Convert some DPRINTF macros to trace events and guest errors
hw/arm: NPCM7XX SoC: Add GMAC ethernet controller devices
hw/arm: Implement BCM2835 SPI Controller
----------------------------------------------------------------
David Woodhouse (1):
doc/sphinx/hxtool.py: add optional label argument to SRST directive
Guenter Roeck (1):
pci-host: designware: Limit value range of iATU viewport register
Hao Wu (2):
hw/net: Add NPCMXXX GMAC device
hw/arm: Add GMAC devices to NPCM7XX SoC
Jan Klötzke (1):
target/arm: fix exception syndrome for AArch32 bkpt insn
Manos Pitsidianakis (6):
hw/arm/strongarm.c: convert DPRINTF to trace events and guest errors
hw/arm/z2: convert DPRINTF to trace events and guest errors
hw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reports
hw/xen/xen-mapcache.c: convert DPRINTF to tracepoints
hw/xen/xen-hvm-common.c: convert DPRINTF to tracepoints
hw/xen: convert stderr prints to error/warn reports
Nabih Estefan Diaz (4):
tests/qtest: Creating qtest for GMAC Module
hw/net: GMAC Rx Implementation
hw/net: GMAC Tx Implementation
tests/qtest: Adding PCS Module test to GMAC Qtest
Peter Maydell (10):
pci: Switch bus reset to 3-phase-reset
vmbus: Switch bus reset to 3-phase-reset
adb: Switch bus reset to 3-phase-reset
hw/s390x/css-bridge: switch virtual-css bus to 3-phase-reset
hw/core: Remove transitional infrastructure from BusClass
system/vl.c: Fix handling of '-serial none -serial something'
qemu-options.hx: Improve -serial option documentation
target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set
tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array
target/arm: Reinstate "vfp" property on AArch32 CPUs
Philippe Mathieu-Daudé (9):
hw/arm/exynos: Add missing QOM parent for CPU cores
hw/arm/exynos: Check for CPU types in machine_run_board_init()
hw/arm/highbank: Add missing QOM parent for CPU cores
hw/arm/highbank: Check for CPU types in machine_run_board_init()
hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[]
hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[]
hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[]
hw/arm/vexpress: Check for CPU types in machine_run_board_init()
hw/arm/zynq: Check for CPU types in machine_run_board_init()
Rayhan Faizel (2):
hw/ssi: Implement BCM2835 SPI Controller
hw/arm: Connect SPI Controller to BCM2835
docs/devel/docs.rst | 12 +-
docs/sphinx/hxtool.py | 16 +
docs/system/arm/raspi.rst | 2 +-
docs/system/i386/xen.rst | 3 +-
include/hw/arm/bcm2835_peripherals.h | 3 +-
include/hw/arm/msf2-soc.h | 3 -
include/hw/arm/npcm7xx.h | 2 +
include/hw/net/npcm_gmac.h | 343 +++++++++++++
include/hw/qdev-core.h | 2 -
include/hw/ssi/bcm2835_spi.h | 81 +++
target/arm/syndrome.h | 8 +
hw/arm/bcm2835_peripherals.c | 17 +-
hw/arm/exynos4210.c | 1 +
hw/arm/exynos4_boards.c | 8 +
hw/arm/highbank.c | 11 +
hw/arm/msf2-soc.c | 3 +-
hw/arm/msf2-som.c | 4 -
hw/arm/musca.c | 1 -
hw/arm/npcm7xx.c | 37 +-
hw/arm/npcm7xx_boards.c | 1 -
hw/arm/strongarm.c | 82 +--
hw/arm/vexpress.c | 12 +-
hw/arm/xen_arm.c | 23 +-
hw/arm/xilinx_zynq.c | 6 +-
hw/arm/z2.c | 27 +-
hw/core/bus.c | 67 ---
hw/hyperv/vmbus.c | 7 +-
hw/input/adb.c | 7 +-
hw/net/npcm_gmac.c | 942 +++++++++++++++++++++++++++++++++++
hw/pci-host/designware.c | 2 +
hw/pci/pci.c | 10 +-
hw/s390x/css-bridge.c | 5 +-
hw/ssi/bcm2835_spi.c | 288 +++++++++++
hw/xen/xen-hvm-common.c | 47 +-
hw/xen/xen-mapcache.c | 59 +--
system/vl.c | 22 +-
target/arm/cpu.c | 4 +
target/arm/helper.c | 19 +
tests/qtest/npcm_gmac-test.c | 344 +++++++++++++
tests/qtest/xlnx-versal-trng-test.c | 19 +-
tests/tcg/aarch64/sysregs.c | 2 +-
hw/arm/Kconfig | 1 +
hw/arm/trace-events | 15 +
hw/net/meson.build | 2 +-
hw/net/trace-events | 19 +
hw/ssi/Kconfig | 4 +
hw/ssi/meson.build | 1 +
hw/xen/trace-events | 21 +-
qemu-options.hx | 16 +-
tests/qtest/meson.build | 1 +
50 files changed, 2388 insertions(+), 244 deletions(-)
create mode 100644 include/hw/net/npcm_gmac.h
create mode 100644 include/hw/ssi/bcm2835_spi.h
create mode 100644 hw/net/npcm_gmac.c
create mode 100644 hw/ssi/bcm2835_spi.c
create mode 100644 tests/qtest/npcm_gmac-test.c
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/36] target-arm queue
2024-02-02 15:36 Peter Maydell
@ 2024-02-03 13:27 ` Peter Maydell
0 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2024-02-03 13:27 UTC (permalink / raw)
To: qemu-devel
On Fri, 2 Feb 2024 at 15:36, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The following changes since commit c3709fde5955d13f6d4f86ab46ef3cc2288ca65e:
>
> Merge tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu into staging (2024-02-01 14:42:11 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240202
>
> for you to fetch changes up to f09c2b7ba9908714a3e2f1decd989462536cf731:
>
> hw/arm: Connect SPI Controller to BCM2835 (2024-02-02 13:51:59 +0000)
>
> ----------------------------------------------------------------
> target/arm: fix exception syndrome for AArch32 bkpt insn
> pci, vmbus, adb, s390x/css-bridge: Switch buses to 3-phase reset
> system/vl.c: Fix handling of '-serial none -serial something'
> target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set
> tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array
> target/arm: Reinstate "vfp" property on AArch32 CPUs
> doc/sphinx/hxtool.py: add optional label argument to SRST directive
> hw/arm: Check for CPU types in machine_run_board_init() for various boards
> pci-host: designware: Limit value range of iATU viewport register
> hw/arm: Convert some DPRINTF macros to trace events and guest errors
> hw/arm: NPCM7XX SoC: Add GMAC ethernet controller devices
> hw/arm: Implement BCM2835 SPI Controller
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PULL 00/36] target-arm queue
@ 2025-01-28 20:12 Peter Maydell
2025-01-28 20:12 ` [PULL 01/36] hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m' Peter Maydell
` (36 more replies)
0 siblings, 37 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
Hi; here's another arm pullreq; by volume most of this is
refactoring from me, but there are also some bugfixes and
other bits and pieces here.
thanks
-- PMM
The following changes since commit ed734377ab3f3f3cc15d7aa301a87ab6370f2eed:
Merge tag 'linux-user-fix-gupnp-pull-request' of https://github.com/hdeller/qemu-hppa into staging (2025-01-24 14:43:07 -0500)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250128-1
for you to fetch changes up to 664280abddcb3cacc9c6204706bb739fcc1316f7:
hw/usb/canokey: Fix buffer overflow for OUT packet (2025-01-28 18:40:19 +0000)
----------------------------------------------------------------
target-arm queue:
* hw/arm: Remove various uses of first_cpu global
* hw/char/imx_serial: Fix reset value of UFCR register
* hw/char/imx_serial: Update all state before restarting ageing timer
* hw/pci-host/designware: Expose MSI IRQ
* hw/arm/stellaris: refactoring, cleanup
* hw/arm/stellaris: map both I2C controllers
* tests/functional: Add a test for the arm microbit machine
* target/arm: arm_reset_sve_state() should set FPSR, not FPCR
* target/arm: refactorings preparatory to FEAT_AFP implementation
* fpu: Rename float_flag_input_denormal to float_flag_input_denormal_flushed
* fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed
* hw/usb/canokey: Fix buffer overflow for OUT packet
----------------------------------------------------------------
Bernhard Beschow (3):
hw/char/imx_serial: Fix reset value of UFCR register
hw/char/imx_serial: Update all state before restarting ageing timer
hw/pci-host/designware: Expose MSI IRQ
Hongren Zheng (1):
hw/usb/canokey: Fix buffer overflow for OUT packet
Peter Maydell (22):
target/arm: arm_reset_sve_state() should set FPSR, not FPCR
target/arm: Use FPSR_ constants in vfp_exceptbits_from_host()
target/arm: Use uint32_t in vfp_exceptbits_from_host()
target/arm: Define new fp_status_a32 and fp_status_a64
target/arm: Use vfp.fp_status_a64 in A64-only helper functions
target/arm: Use fp_status_a64 or fp_status_a32 in is_ebf()
target/arm: Use fp_status_a32 in vjvct helper
target/arm: Use fp_status_a32 in vfp_cmp helpers
target/arm: Use FPST_A32 in A32 decoder
target/arm: Use FPST_A64 in A64 decoder
target/arm: Remove now-unused vfp.fp_status and FPST_FPCR
target/arm: Define new fp_status_f16_a32 and fp_status_f16_a64
target/arm: Use fp_status_f16_a32 in AArch32-only helpers
target/arm: Use fp_status_f16_a64 in AArch64-only helpers
target/arm: Use FPST_A32_F16 in A32 decoder
target/arm: Use FPST_A64_F16 in A64 decoder
target/arm: Remove now-unused vfp.fp_status_f16 and FPST_FPCR_F16
fpu: Rename float_flag_input_denormal to float_flag_input_denormal_flushed
fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed
fpu: Fix a comment in softfloat-types.h
target/arm: Remove redundant advsimd float16 helpers
target/arm: Use FPST_A64_F16 for halfprec-to-other conversions
Philippe Mathieu-Daudé (9):
hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m'
hw/arm/stellaris: Add 'armv7m' local variable
hw/arm/v7m: Remove use of &first_cpu in machine_init()
hw/arm/stellaris: Link each board schematic
hw/arm/stellaris: Constify read-only arrays
hw/arm/stellaris: Remove incorrect unimplemented i2c-0 at 0x40002000
hw/arm/stellaris: Replace magic numbers by definitions
hw/arm/stellaris: Use DEVCAP macro to access DeviceCapability registers
hw/arm/stellaris: Map both I2C controllers
Thomas Huth (1):
tests/functional: Add a test for the arm microbit machine
MAINTAINERS | 1 +
hw/usb/canokey.h | 4 --
include/fpu/softfloat-types.h | 10 +--
include/hw/arm/fsl-imx6.h | 4 +-
include/hw/arm/fsl-imx7.h | 4 +-
include/hw/arm/nrf51_soc.h | 2 +-
include/hw/char/imx_serial.h | 2 +-
include/hw/pci-host/designware.h | 1 +
target/arm/cpu.h | 12 ++--
target/arm/tcg/helper-a64.h | 8 ---
target/arm/tcg/translate.h | 32 ++++++---
fpu/softfloat.c | 6 +-
hw/arm/b-l475e-iot01a.c | 2 +-
hw/arm/fsl-imx6.c | 13 +++-
hw/arm/fsl-imx7.c | 13 +++-
hw/arm/microbit.c | 2 +-
hw/arm/mps2-tz.c | 2 +-
hw/arm/mps2.c | 2 +-
hw/arm/msf2-som.c | 2 +-
hw/arm/musca.c | 2 +-
hw/arm/netduino2.c | 2 +-
hw/arm/netduinoplus2.c | 2 +-
hw/arm/nrf51_soc.c | 18 ++---
hw/arm/olimex-stm32-h405.c | 2 +-
hw/arm/stellaris.c | 118 +++++++++++++++++++-----------
hw/arm/stm32vldiscovery.c | 2 +-
hw/char/imx_serial.c | 7 +-
hw/pci-host/designware.c | 7 +-
hw/usb/canokey.c | 6 +-
target/arm/cpu.c | 6 +-
target/arm/helper.c | 2 +-
target/arm/tcg/helper-a64.c | 9 ---
target/arm/tcg/sme_helper.c | 6 +-
target/arm/tcg/sve_helper.c | 6 +-
target/arm/tcg/translate-a64.c | 103 ++++++++++++++-------------
target/arm/tcg/translate-sme.c | 4 +-
target/arm/tcg/translate-sve.c | 130 +++++++++++++++++-----------------
target/arm/tcg/translate-vfp.c | 78 ++++++++++----------
target/arm/tcg/vec_helper.c | 22 +++---
target/arm/vfp_helper.c | 73 +++++++++++--------
target/i386/tcg/fpu_helper.c | 8 +--
target/m68k/fpu_helper.c | 2 +-
target/mips/tcg/msa_helper.c | 4 +-
target/rx/op_helper.c | 4 +-
target/tricore/fpu_helper.c | 6 +-
fpu/softfloat-parts.c.inc | 4 +-
hw/arm/Kconfig | 2 +
tests/functional/meson.build | 1 +
tests/functional/test_arm_microbit.py | 31 ++++++++
49 files changed, 452 insertions(+), 337 deletions(-)
create mode 100755 tests/functional/test_arm_microbit.py
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PULL 01/36] hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m'
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 02/36] hw/arm/stellaris: Add 'armv7m' local variable Peter Maydell
` (35 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The ARMv7MState object is not simply a CPU, it also
contains the NVIC, SysTick timer, and various MemoryRegions.
Rename the field as 'armv7m', like other Cortex-M boards.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20250112225614.33723-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/nrf51_soc.h | 2 +-
hw/arm/nrf51_soc.c | 18 +++++++++---------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h
index e52a56e75e0..f88ab1b7d3e 100644
--- a/include/hw/arm/nrf51_soc.h
+++ b/include/hw/arm/nrf51_soc.h
@@ -30,7 +30,7 @@ struct NRF51State {
SysBusDevice parent_obj;
/*< public >*/
- ARMv7MState cpu;
+ ARMv7MState armv7m;
NRF51UARTState uart;
NRF51RNGState rng;
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index 37dd4cf5f40..dee06ab5654 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -76,16 +76,16 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
}
/* This clock doesn't need migration because it is fixed-frequency */
clock_set_hz(s->sysclk, HCLK_FRQ);
- qdev_connect_clock_in(DEVICE(&s->cpu), "cpuclk", s->sysclk);
+ qdev_connect_clock_in(DEVICE(&s->armv7m), "cpuclk", s->sysclk);
/*
* This SoC has no systick device, so don't connect refclk.
* TODO: model the lack of systick (currently the armv7m object
* will always provide one).
*/
- object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
+ object_property_set_link(OBJECT(&s->armv7m), "memory", OBJECT(&s->container),
&error_abort);
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
return;
}
@@ -104,7 +104,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
- qdev_get_gpio_in(DEVICE(&s->cpu),
+ qdev_get_gpio_in(DEVICE(&s->armv7m),
BASE_TO_IRQ(NRF51_UART_BASE)));
/* RNG */
@@ -115,7 +115,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
- qdev_get_gpio_in(DEVICE(&s->cpu),
+ qdev_get_gpio_in(DEVICE(&s->armv7m),
BASE_TO_IRQ(NRF51_RNG_BASE)));
/* UICR, FICR, NVMC, FLASH */
@@ -161,7 +161,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->cpu),
+ qdev_get_gpio_in(DEVICE(&s->armv7m),
BASE_TO_IRQ(base_addr)));
}
@@ -185,10 +185,10 @@ static void nrf51_soc_init(Object *obj)
memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
- object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M);
- qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
+ object_initialize_child(OBJECT(s), "armv6m", &s->armv7m, TYPE_ARMV7M);
+ qdev_prop_set_string(DEVICE(&s->armv7m), "cpu-type",
ARM_CPU_TYPE_NAME("cortex-m0"));
- qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
+ qdev_prop_set_uint32(DEVICE(&s->armv7m), "num-irq", 32);
object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART);
object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 02/36] hw/arm/stellaris: Add 'armv7m' local variable
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
2025-01-28 20:12 ` [PULL 01/36] hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m' Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 03/36] hw/arm/v7m: Remove use of &first_cpu in machine_init() Peter Maydell
` (34 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
While the TYPE_ARMV7M object forward its NVIC interrupt lines,
it is somehow misleading to name it 'nvic'. Add the 'armv7m'
local variable for clarity, but also keep the 'nvic' variable
behaving like before when used for wiring IRQ lines.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20250112225614.33723-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stellaris.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 1bba96df14e..7303e096ef7 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1031,7 +1031,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
*/
Object *soc_container;
- DeviceState *gpio_dev[7], *nvic;
+ DeviceState *gpio_dev[7], *armv7m, *nvic;
qemu_irq gpio_in[7][8];
qemu_irq gpio_out[7][8];
qemu_irq adc;
@@ -1095,19 +1095,20 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4);
sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
- nvic = qdev_new(TYPE_ARMV7M);
- object_property_add_child(soc_container, "v7m", OBJECT(nvic));
- qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
- qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
- qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
- qdev_prop_set_bit(nvic, "enable-bitband", true);
- qdev_connect_clock_in(nvic, "cpuclk",
+ armv7m = qdev_new(TYPE_ARMV7M);
+ object_property_add_child(soc_container, "v7m", OBJECT(armv7m));
+ qdev_prop_set_uint32(armv7m, "num-irq", NUM_IRQ_LINES);
+ qdev_prop_set_uint8(armv7m, "num-prio-bits", NUM_PRIO_BITS);
+ qdev_prop_set_string(armv7m, "cpu-type", ms->cpu_type);
+ qdev_prop_set_bit(armv7m, "enable-bitband", true);
+ qdev_connect_clock_in(armv7m, "cpuclk",
qdev_get_clock_out(ssys_dev, "SYSCLK"));
/* This SoC does not connect the systick reference clock */
- object_property_set_link(OBJECT(nvic), "memory",
+ object_property_set_link(OBJECT(armv7m), "memory",
OBJECT(get_system_memory()), &error_abort);
/* This will exit with an error if the user passed us a bad cpu_type */
- sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(armv7m), &error_fatal);
+ nvic = armv7m;
/* Now we can wire up the IRQ and MMIO of the system registers */
sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000);
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 03/36] hw/arm/v7m: Remove use of &first_cpu in machine_init()
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
2025-01-28 20:12 ` [PULL 01/36] hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m' Peter Maydell
2025-01-28 20:12 ` [PULL 02/36] hw/arm/stellaris: Add 'armv7m' local variable Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 04/36] hw/char/imx_serial: Fix reset value of UFCR register Peter Maydell
` (33 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
When instanciating the machine model, the machine_init()
implementations usually create the CPUs, so have access
to its first CPU. Use that rather then the &first_cpu
global.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Samuel Tardieu <sam@rfc1149.net>
Message-id: 20250112225614.33723-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/b-l475e-iot01a.c | 2 +-
hw/arm/microbit.c | 2 +-
hw/arm/mps2-tz.c | 2 +-
hw/arm/mps2.c | 2 +-
hw/arm/msf2-som.c | 2 +-
hw/arm/musca.c | 2 +-
hw/arm/netduino2.c | 2 +-
hw/arm/netduinoplus2.c | 2 +-
hw/arm/olimex-stm32-h405.c | 2 +-
hw/arm/stellaris.c | 2 +-
hw/arm/stm32vldiscovery.c | 2 +-
11 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index 5002a40f06d..c9a5209216c 100644
--- a/hw/arm/b-l475e-iot01a.c
+++ b/hw/arm/b-l475e-iot01a.c
@@ -82,7 +82,7 @@ static void bl475e_init(MachineState *machine)
sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
sc = STM32L4X5_SOC_GET_CLASS(&s->soc);
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,
+ armv7m_load_kernel(s->soc.armv7m.cpu, machine->kernel_filename, 0,
sc->flash_size);
if (object_class_by_name(TYPE_DM163)) {
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index 374fbcb3618..3f56fb45ce1 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -56,7 +56,7 @@ static void microbit_init(MachineState *machine)
memory_region_add_subregion_overlap(&s->nrf51.container, NRF51_TWI_BASE,
mr, -1);
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(s->nrf51.armv7m.cpu, machine->kernel_filename,
0, s->nrf51.flash_size);
}
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 0136e419bfd..d3a9f1b03ac 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -1211,7 +1211,7 @@ static void mps2tz_common_init(MachineState *machine)
mms->remap_irq);
}
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(mms->iotkit.armv7m[0].cpu, machine->kernel_filename,
0, boot_ram_size(mms));
}
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index efb3500742f..56b2af40f1d 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -460,7 +460,7 @@ static void mps2_common_init(MachineState *machine)
qdev_get_gpio_in(armv7m,
mmc->fpga_type == FPGA_AN511 ? 47 : 13));
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(mms->armv7m.cpu, machine->kernel_filename,
0, 0x400000);
}
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index 5c415abe852..9b20f1e2c98 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -92,7 +92,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(soc->armv7m.cpu, machine->kernel_filename,
0, soc->envm_size);
}
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index 3c3b534cb72..e9c092abc3d 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -590,7 +590,7 @@ static void musca_init(MachineState *machine)
"cfg_sec_resp", 0));
}
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(mms->sse.armv7m[0].cpu, machine->kernel_filename,
0, 0x2000000);
}
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index 8b1a9a24379..df793c77fe1 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -48,7 +48,7 @@ static void netduino2_init(MachineState *machine)
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(STM32F205_SOC(dev)->armv7m.cpu, machine->kernel_filename,
0, FLASH_SIZE);
}
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index bccd1003549..81b6334cf72 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -48,7 +48,7 @@ static void netduinoplus2_init(MachineState *machine)
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- armv7m_load_kernel(ARM_CPU(first_cpu),
+ armv7m_load_kernel(STM32F405_SOC(dev)->armv7m.cpu,
machine->kernel_filename,
0, FLASH_SIZE);
}
diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
index 4ad7b043be0..1f15620f9fd 100644
--- a/hw/arm/olimex-stm32-h405.c
+++ b/hw/arm/olimex-stm32-h405.c
@@ -51,7 +51,7 @@ static void olimex_stm32_h405_init(MachineState *machine)
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- armv7m_load_kernel(ARM_CPU(first_cpu),
+ armv7m_load_kernel(STM32F405_SOC(dev)->armv7m.cpu,
machine->kernel_filename,
0, FLASH_SIZE);
}
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 7303e096ef7..284980ad4b5 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1366,7 +1366,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
- armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, 0, flash_size);
+ armv7m_load_kernel(ARMV7M(armv7m)->cpu, ms->kernel_filename, 0, flash_size);
}
/* FIXME: Figure out how to generate these from stellaris_boards. */
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index cc419351605..e6c1f5b8d7d 100644
--- a/hw/arm/stm32vldiscovery.c
+++ b/hw/arm/stm32vldiscovery.c
@@ -51,7 +51,7 @@ static void stm32vldiscovery_init(MachineState *machine)
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- armv7m_load_kernel(ARM_CPU(first_cpu),
+ armv7m_load_kernel(STM32F100_SOC(dev)->armv7m.cpu,
machine->kernel_filename,
0, FLASH_SIZE);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 04/36] hw/char/imx_serial: Fix reset value of UFCR register
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2025-01-28 20:12 ` [PULL 03/36] hw/arm/v7m: Remove use of &first_cpu in machine_init() Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 05/36] hw/char/imx_serial: Update all state before restarting ageing timer Peter Maydell
` (32 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
From: Bernhard Beschow <shentey@gmail.com>
The value of the UCFR register is respected when echoing characters to the
terminal, but its reset value is reserved. Fix the reset value to the one
documented in the datasheet.
While at it move the related attribute out of the section of unimplemented
registers since its value is actually respected.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/char/imx_serial.h | 2 +-
hw/char/imx_serial.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
index 65f0e97c76b..90ba3ff18c2 100644
--- a/include/hw/char/imx_serial.h
+++ b/include/hw/char/imx_serial.h
@@ -109,13 +109,13 @@ struct IMXSerialState {
uint32_t ucr1;
uint32_t ucr2;
uint32_t uts1;
+ uint32_t ufcr;
/*
* The registers below are implemented just so that the
* guest OS sees what it has written
*/
uint32_t onems;
- uint32_t ufcr;
uint32_t ubmr;
uint32_t ubrc;
uint32_t ucr3;
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index 7c353fde509..cb6761d40e4 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -160,6 +160,7 @@ static void imx_serial_reset(IMXSerialState *s)
s->ucr3 = 0x700;
s->ubmr = 0;
s->ubrc = 4;
+ s->ufcr = BIT(11) | BIT(0);
fifo32_reset(&s->rx_fifo);
timer_del(&s->ageing_timer);
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 05/36] hw/char/imx_serial: Update all state before restarting ageing timer
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2025-01-28 20:12 ` [PULL 04/36] hw/char/imx_serial: Fix reset value of UFCR register Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 06/36] hw/pci-host/designware: Expose MSI IRQ Peter Maydell
` (31 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
From: Bernhard Beschow <shentey@gmail.com>
Fixes characters to be "echoed" after each keystroke rather than after every
other since imx_serial_rx_fifo_ageing_timer_restart() would see ~UTS1_RXEMPTY
only after every other keystroke.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/char/imx_serial.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index cb6761d40e4..38b4865157e 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -401,14 +401,14 @@ static void imx_put_data(void *opaque, uint32_t value)
if (fifo32_num_used(&s->rx_fifo) >= rxtl) {
s->usr1 |= USR1_RRDY;
}
-
- imx_serial_rx_fifo_ageing_timer_restart(s);
-
s->usr2 |= USR2_RDR;
s->uts1 &= ~UTS1_RXEMPTY;
if (value & URXD_BRK) {
s->usr2 |= USR2_BRCD;
}
+
+ imx_serial_rx_fifo_ageing_timer_restart(s);
+
imx_update(s);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 06/36] hw/pci-host/designware: Expose MSI IRQ
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2025-01-28 20:12 ` [PULL 05/36] hw/char/imx_serial: Update all state before restarting ageing timer Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 07/36] hw/arm/stellaris: Link each board schematic Peter Maydell
` (30 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
From: Bernhard Beschow <shentey@gmail.com>
Fixes INTD and MSI interrupts poking the same IRQ line without keeping track of
each other's IRQ level. Furthermore, SoCs such as the i.MX 8M Plus don't share
the MSI IRQ with the INTx lines, so expose it as a dedicated pin.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/fsl-imx6.h | 4 +++-
include/hw/arm/fsl-imx7.h | 4 +++-
include/hw/pci-host/designware.h | 1 +
hw/arm/fsl-imx6.c | 13 ++++++++++++-
hw/arm/fsl-imx7.c | 13 ++++++++++++-
hw/pci-host/designware.c | 7 +++----
hw/arm/Kconfig | 2 ++
7 files changed, 36 insertions(+), 8 deletions(-)
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index 61c593ffd24..9da32fc1895 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -33,6 +33,7 @@
#include "hw/usb/chipidea.h"
#include "hw/usb/imx-usb-phy.h"
#include "hw/pci-host/designware.h"
+#include "hw/or-irq.h"
#include "exec/memory.h"
#include "cpu.h"
#include "qom/object.h"
@@ -73,6 +74,7 @@ struct FslIMX6State {
ChipideaState usb[FSL_IMX6_NUM_USBS];
IMXFECState eth;
DesignwarePCIEHost pcie;
+ OrIRQState pcie4_msi_irq;
MemoryRegion rom;
MemoryRegion caam;
MemoryRegion ocram;
@@ -457,7 +459,7 @@ struct FslIMX6State {
#define FSL_IMX6_PCIE1_IRQ 120
#define FSL_IMX6_PCIE2_IRQ 121
#define FSL_IMX6_PCIE3_IRQ 122
-#define FSL_IMX6_PCIE4_IRQ 123
+#define FSL_IMX6_PCIE4_MSI_IRQ 123
#define FSL_IMX6_DCIC1_IRQ 124
#define FSL_IMX6_DCIC2_IRQ 125
#define FSL_IMX6_MLB150_HIGH_IRQ 126
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index 411fa1c2e37..aa7818c4999 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -36,6 +36,7 @@
#include "hw/net/imx_fec.h"
#include "hw/pci-host/designware.h"
#include "hw/usb/chipidea.h"
+#include "hw/or-irq.h"
#include "cpu.h"
#include "qom/object.h"
#include "qemu/units.h"
@@ -85,6 +86,7 @@ struct FslIMX7State {
IMX7GPRState gpr;
ChipideaState usb[FSL_IMX7_NUM_USBS];
DesignwarePCIEHost pcie;
+ OrIRQState pcie4_msi_irq;
MemoryRegion rom;
MemoryRegion caam;
MemoryRegion ocram;
@@ -428,7 +430,7 @@ enum FslIMX7IRQs {
FSL_IMX7_PCI_INTA_IRQ = 125,
FSL_IMX7_PCI_INTB_IRQ = 124,
FSL_IMX7_PCI_INTC_IRQ = 123,
- FSL_IMX7_PCI_INTD_IRQ = 122,
+ FSL_IMX7_PCI_INTD_MSI_IRQ = 122,
FSL_IMX7_UART7_IRQ = 126,
diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h
index c484e377a81..bf8b2789787 100644
--- a/include/hw/pci-host/designware.h
+++ b/include/hw/pci-host/designware.h
@@ -86,6 +86,7 @@ struct DesignwarePCIEHost {
MemoryRegion io;
qemu_irq irqs[4];
+ qemu_irq msi;
} pci;
MemoryRegion mmio;
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index ac8c66e242c..88b9ccff493 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -106,6 +106,8 @@ static void fsl_imx6_init(Object *obj)
object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET);
object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
+ object_initialize_child(obj, "pcie4-msi-irq", &s->pcie4_msi_irq,
+ TYPE_OR_IRQ);
}
static void fsl_imx6_realize(DeviceState *dev, Error **errp)
@@ -435,14 +437,23 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX6_PCIe_REG_ADDR);
+ object_property_set_int(OBJECT(&s->pcie4_msi_irq), "num-lines", 2,
+ &error_abort);
+ qdev_realize(DEVICE(&s->pcie4_msi_irq), NULL, &error_abort);
+
+ irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE4_MSI_IRQ);
+ qdev_connect_gpio_out(DEVICE(&s->pcie4_msi_irq), 0, irq);
+
irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE1_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE2_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE3_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);
- irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE4_IRQ);
+ irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 1);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4, irq);
/*
* PCIe PHY
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index 05e3389fbe0..004bf499376 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -150,6 +150,8 @@ static void fsl_imx7_init(Object *obj)
* PCIE
*/
object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
+ object_initialize_child(obj, "pcie4-msi-irq", &s->pcie4_msi_irq,
+ TYPE_OR_IRQ);
/*
* USBs
@@ -597,14 +599,23 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
+ object_property_set_int(OBJECT(&s->pcie4_msi_irq), "num-lines", 2,
+ &error_abort);
+ qdev_realize(DEVICE(&s->pcie4_msi_irq), NULL, &error_abort);
+
+ irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_MSI_IRQ);
+ qdev_connect_gpio_out(DEVICE(&s->pcie4_msi_irq), 0, irq);
+
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
+ irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 1);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4, irq);
/*
* USBs
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index c3fc37b9047..3e8c36e6a76 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -55,8 +55,6 @@
#define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff)
#define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C
-#define DESIGNWARE_PCIE_IRQ_MSI 3
-
static DesignwarePCIEHost *
designware_pcie_root_to_host(DesignwarePCIERoot *root)
{
@@ -90,7 +88,7 @@ static void designware_pcie_root_msi_write(void *opaque, hwaddr addr,
root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable;
if (root->msi.intr[0].status & ~root->msi.intr[0].mask) {
- qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1);
+ qemu_set_irq(host->pci.msi, 1);
}
}
@@ -335,7 +333,7 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
case DESIGNWARE_PCIE_MSI_INTR0_STATUS:
root->msi.intr[0].status ^= val;
if (!root->msi.intr[0].status) {
- qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0);
+ qemu_set_irq(host->pci.msi, 0);
}
break;
@@ -680,6 +678,7 @@ static void designware_pcie_host_realize(DeviceState *dev, Error **errp)
for (i = 0; i < ARRAY_SIZE(s->pci.irqs); i++) {
sysbus_init_irq(sbd, &s->pci.irqs[i]);
}
+ sysbus_init_irq(sbd, &s->pci.msi);
memory_region_init_io(&s->mmio,
OBJECT(s),
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index e779b5af958..256013ca808 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -516,6 +516,7 @@ config FSL_IMX6
select PL310 # cache controller
select PCI_EXPRESS_DESIGNWARE
select SDHCI
+ select OR_IRQ
config ASPEED_SOC
bool
@@ -573,6 +574,7 @@ config FSL_IMX7
select WDT_IMX2
select PCI_EXPRESS_DESIGNWARE
select SDHCI
+ select OR_IRQ
select UNIMP
config ARM_SMMUV3
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 07/36] hw/arm/stellaris: Link each board schematic
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (5 preceding siblings ...)
2025-01-28 20:12 ` [PULL 06/36] hw/pci-host/designware: Expose MSI IRQ Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 08/36] hw/arm/stellaris: Constify read-only arrays Peter Maydell
` (29 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Board schematic is useful to corroborate GPIOs/IRQs wiring.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250110160204.74997-2-philmd@linaro.org
[PMM: Use https:// URLs]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stellaris.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 284980ad4b5..3f525d2dcf6 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1380,6 +1380,10 @@ static void lm3s6965evb_init(MachineState *machine)
stellaris_init(machine, &stellaris_boards[1]);
}
+/*
+ * Stellaris LM3S811 Evaluation Board Schematics:
+ * https://www.ti.com/lit/ug/symlink/spmu030.pdf
+ */
static void lm3s811evb_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1396,6 +1400,10 @@ static const TypeInfo lm3s811evb_type = {
.class_init = lm3s811evb_class_init,
};
+/*
+ * Stellaris: LM3S6965 Evaluation Board Schematics:
+ * https://www.ti.com/lit/ug/symlink/spmu029.pdf
+ */
static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 08/36] hw/arm/stellaris: Constify read-only arrays
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (6 preceding siblings ...)
2025-01-28 20:12 ` [PULL 07/36] hw/arm/stellaris: Link each board schematic Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 09/36] hw/arm/stellaris: Remove incorrect unimplemented i2c-0 at 0x40002000 Peter Maydell
` (28 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250110160204.74997-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stellaris.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 3f525d2dcf6..42498cc1e53 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -101,7 +101,7 @@ static void ssys_update(ssys_state *s)
qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
}
-static uint32_t pllcfg_sandstorm[16] = {
+static const uint32_t pllcfg_sandstorm[16] = {
0x31c0, /* 1 Mhz */
0x1ae0, /* 1.8432 Mhz */
0x18c0, /* 2 Mhz */
@@ -120,7 +120,7 @@ static uint32_t pllcfg_sandstorm[16] = {
0x585b /* 8.192 Mhz */
};
-static uint32_t pllcfg_fury[16] = {
+static const uint32_t pllcfg_fury[16] = {
0x3200, /* 1 Mhz */
0x1b20, /* 1.8432 Mhz */
0x1900, /* 2 Mhz */
@@ -964,7 +964,7 @@ static void stellaris_adc_init(Object *obj)
}
/* Board init. */
-static stellaris_board_info stellaris_boards[] = {
+static const stellaris_board_info stellaris_boards[] = {
{ "LM3S811EVB",
0,
0x0032000e,
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 09/36] hw/arm/stellaris: Remove incorrect unimplemented i2c-0 at 0x40002000
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (7 preceding siblings ...)
2025-01-28 20:12 ` [PULL 08/36] hw/arm/stellaris: Constify read-only arrays Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 10/36] hw/arm/stellaris: Replace magic numbers by definitions Peter Maydell
` (27 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
There is nothing mapped at 0x40002000.
I2C#0 is already mapped at 0x40021000.
Remove the invalid mapping added in commits aecfbbc97a2 & 394c8bbfb7a.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250110160204.74997-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stellaris.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 42498cc1e53..4df02138ac5 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1001,7 +1001,6 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
* http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
*
* 40000000 wdtimer
- * 40002000 i2c (unimplemented)
* 40004000 GPIO
* 40005000 GPIO
* 40006000 GPIO
@@ -1357,7 +1356,6 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
/* Add dummy regions for the devices we don't implement yet,
* so guest accesses don't cause unlogged crashes.
*/
- create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
create_unimplemented_device("PWM", 0x40028000, 0x1000);
create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 10/36] hw/arm/stellaris: Replace magic numbers by definitions
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (8 preceding siblings ...)
2025-01-28 20:12 ` [PULL 09/36] hw/arm/stellaris: Remove incorrect unimplemented i2c-0 at 0x40002000 Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 11/36] hw/arm/stellaris: Use DEVCAP macro to access DeviceCapability registers Peter Maydell
` (26 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Add definitions for the number of controllers.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250110160204.74997-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stellaris.c | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 4df02138ac5..dd342b17d2a 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -49,6 +49,11 @@
#define NUM_IRQ_LINES 64
#define NUM_PRIO_BITS 3
+#define NUM_GPIO 7
+#define NUM_UART 4
+#define NUM_GPTM 4
+#define NUM_I2C 2
+
typedef const struct {
const char *name;
uint32_t did0;
@@ -989,12 +994,12 @@ static const stellaris_board_info stellaris_boards[] = {
static void stellaris_init(MachineState *ms, stellaris_board_info *board)
{
- static const int uart_irq[] = {5, 6, 33, 34};
- static const int timer_irq[] = {19, 21, 23, 35};
- static const uint32_t gpio_addr[7] =
+ static const int uart_irq[NUM_UART] = {5, 6, 33, 34};
+ static const int timer_irq[NUM_GPTM] = {19, 21, 23, 35};
+ static const uint32_t gpio_addr[NUM_GPIO] =
{ 0x40004000, 0x40005000, 0x40006000, 0x40007000,
0x40024000, 0x40025000, 0x40026000};
- static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
+ static const int gpio_irq[NUM_GPIO] = {0, 1, 2, 3, 4, 30, 31};
/* Memory map of SoC devices, from
* Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
@@ -1030,9 +1035,9 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
*/
Object *soc_container;
- DeviceState *gpio_dev[7], *armv7m, *nvic;
- qemu_irq gpio_in[7][8];
- qemu_irq gpio_out[7][8];
+ DeviceState *gpio_dev[NUM_GPIO], *armv7m, *nvic;
+ qemu_irq gpio_in[NUM_GPIO][8];
+ qemu_irq gpio_out[NUM_GPIO][8];
qemu_irq adc;
int sram_size;
int flash_size;
@@ -1124,7 +1129,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
} else {
adc = NULL;
}
- for (i = 0; i < 4; i++) {
+ for (i = 0; i < NUM_GPTM; i++) {
if (board->dc2 & (0x10000 << i)) {
SysBusDevice *sbd;
@@ -1158,7 +1163,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
}
- for (i = 0; i < 7; i++) {
+ for (i = 0; i < NUM_GPIO; i++) {
if (board->dc4 & (1 << i)) {
gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
qdev_get_gpio_in(nvic,
@@ -1179,7 +1184,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
}
}
- for (i = 0; i < 4; i++) {
+ for (i = 0; i < NUM_UART; i++) {
if (board->dc2 & (1 << i)) {
SysBusDevice *sbd;
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 11/36] hw/arm/stellaris: Use DEVCAP macro to access DeviceCapability registers
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (9 preceding siblings ...)
2025-01-28 20:12 ` [PULL 10/36] hw/arm/stellaris: Replace magic numbers by definitions Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 12/36] hw/arm/stellaris: Map both I2C controllers Peter Maydell
` (25 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Add definitions (DCx_periph) for the DeviceCapability bits,
replace direct bitmask checks with the DEV_CAP() macro,
which use the extract/deposit API.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250110160204.74997-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stellaris.c | 37 +++++++++++++++++++++++++++++--------
1 file changed, 29 insertions(+), 8 deletions(-)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index dd342b17d2a..82f935cb329 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -8,6 +8,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/bitops.h"
#include "qapi/error.h"
#include "hw/core/split-irq.h"
#include "hw/sysbus.h"
@@ -54,6 +55,26 @@
#define NUM_GPTM 4
#define NUM_I2C 2
+/*
+ * See Stellaris Data Sheet chapter 5.2.5 "System Control",
+ * Register 13 .. 17: Device Capabilities 0 .. 4 (DC0 .. DC4).
+ */
+#define DC1_WDT 3
+#define DC1_HIB 6
+#define DC1_MPU 7
+#define DC1_ADC 16
+#define DC1_PWM 20
+#define DC2_UART(n) (n)
+#define DC2_SSI 4
+#define DC2_QEI(n) (8 + n)
+#define DC2_I2C(n) (12 + 2 * n)
+#define DC2_GPTM(n) (16 + n)
+#define DC2_COMP(n) (24 + n)
+#define DC4_GPIO(n) (n)
+#define DC4_EMAC 28
+
+#define DEV_CAP(_dc, _cap) extract32(board->dc##_dc, DC##_dc##_##_cap, 1)
+
typedef const struct {
const char *name;
uint32_t did0;
@@ -1118,7 +1139,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000);
sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28));
- if (board->dc1 & (1 << 16)) {
+ if (DEV_CAP(1, ADC)) {
dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
qdev_get_gpio_in(nvic, 14),
qdev_get_gpio_in(nvic, 15),
@@ -1130,7 +1151,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
adc = NULL;
}
for (i = 0; i < NUM_GPTM; i++) {
- if (board->dc2 & (0x10000 << i)) {
+ if (DEV_CAP(2, GPTM(i))) {
SysBusDevice *sbd;
dev = qdev_new(TYPE_STELLARIS_GPTM);
@@ -1147,7 +1168,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
}
}
- if (board->dc1 & (1 << 3)) { /* watchdog present */
+ if (DEV_CAP(1, WDT)) {
dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
object_property_add_child(soc_container, "wdg", OBJECT(dev));
qdev_connect_clock_in(dev, "WDOGCLK",
@@ -1164,7 +1185,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
for (i = 0; i < NUM_GPIO; i++) {
- if (board->dc4 & (1 << i)) {
+ if (DEV_CAP(4, GPIO(i))) {
gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
qdev_get_gpio_in(nvic,
gpio_irq[i]));
@@ -1175,7 +1196,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
}
}
- if (board->dc2 & (1 << 12)) {
+ if (DEV_CAP(2, I2C(0))) {
dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,
qdev_get_gpio_in(nvic, 8));
i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
@@ -1185,7 +1206,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
}
for (i = 0; i < NUM_UART; i++) {
- if (board->dc2 & (1 << i)) {
+ if (DEV_CAP(2, UART(i))) {
SysBusDevice *sbd;
dev = qdev_new("pl011_luminary");
@@ -1197,7 +1218,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i]));
}
}
- if (board->dc2 & (1 << 4)) {
+ if (DEV_CAP(2, SSI)) {
dev = sysbus_create_simple("pl022", 0x40008000,
qdev_get_gpio_in(nvic, 7));
if (board->peripherals & BP_OLED_SSI) {
@@ -1306,7 +1327,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
qemu_irq_raise(gpio_out[GPIO_D][0]);
}
}
- if (board->dc4 & (1 << 28)) {
+ if (DEV_CAP(4, EMAC)) {
DeviceState *enet;
enet = qdev_new("stellaris_enet");
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 12/36] hw/arm/stellaris: Map both I2C controllers
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (10 preceding siblings ...)
2025-01-28 20:12 ` [PULL 11/36] hw/arm/stellaris: Use DEVCAP macro to access DeviceCapability registers Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 13/36] tests/functional: Add a test for the arm microbit machine Peter Maydell
` (24 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
There are 2 I2C controllers, map them both, removing
the unimplemented one. Keep the OLED controller on the
first I2C bus.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250110160204.74997-7-philmd@linaro.org
[PMM: tweak to appease maybe-use-uninitialized warning]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stellaris.c | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 82f935cb329..c3c3fd0410e 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1021,6 +1021,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
{ 0x40004000, 0x40005000, 0x40006000, 0x40007000,
0x40024000, 0x40025000, 0x40026000};
static const int gpio_irq[NUM_GPIO] = {0, 1, 2, 3, 4, 30, 31};
+ static const uint32_t i2c_addr[NUM_I2C] = {0x40020000, 0x40021000};
+ static const int i2c_irq[NUM_I2C] = {8, 37};
/* Memory map of SoC devices, from
* Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
@@ -1062,7 +1064,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
qemu_irq adc;
int sram_size;
int flash_size;
- I2CBus *i2c;
+ DeviceState *i2c_dev[NUM_I2C] = { };
DeviceState *dev;
DeviceState *ssys_dev;
int i;
@@ -1196,14 +1198,18 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
}
}
- if (DEV_CAP(2, I2C(0))) {
- dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,
- qdev_get_gpio_in(nvic, 8));
- i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
- if (board->peripherals & BP_OLED_I2C) {
- i2c_slave_create_simple(i2c, "ssd0303", 0x3d);
+ for (i = 0; i < NUM_I2C; i++) {
+ if (DEV_CAP(2, I2C(i))) {
+ i2c_dev[i] = sysbus_create_simple(TYPE_STELLARIS_I2C, i2c_addr[i],
+ qdev_get_gpio_in(nvic,
+ i2c_irq[i]));
}
}
+ if (board->peripherals & BP_OLED_I2C) {
+ I2CBus *bus = (I2CBus *)qdev_get_child_bus(i2c_dev[0], "i2c");
+
+ i2c_slave_create_simple(bus, "ssd0303", 0x3d);
+ }
for (i = 0; i < NUM_UART; i++) {
if (DEV_CAP(2, UART(i))) {
@@ -1382,7 +1388,6 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
/* Add dummy regions for the devices we don't implement yet,
* so guest accesses don't cause unlogged crashes.
*/
- create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
create_unimplemented_device("PWM", 0x40028000, 0x1000);
create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 13/36] tests/functional: Add a test for the arm microbit machine
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (11 preceding siblings ...)
2025-01-28 20:12 ` [PULL 12/36] hw/arm/stellaris: Map both I2C controllers Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 14/36] target/arm: arm_reset_sve_state() should set FPSR, not FPCR Peter Maydell
` (23 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
From: Thomas Huth <thuth@redhat.com>
We don't have any functional tests for this machine yet, thus let's
add a test with a MicroPython binary that is available online
(thanks to Joel Stanley for providing it, see:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg606064.html ).
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20250124101709.1591761-1-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
MAINTAINERS | 1 +
tests/functional/meson.build | 1 +
tests/functional/test_arm_microbit.py | 31 +++++++++++++++++++++++++++
3 files changed, 33 insertions(+)
create mode 100755 tests/functional/test_arm_microbit.py
diff --git a/MAINTAINERS b/MAINTAINERS
index 7be3d8f431a..bb96a00db04 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1157,6 +1157,7 @@ F: hw/*/microbit*.c
F: include/hw/*/nrf51*.h
F: include/hw/*/microbit*.h
F: tests/qtest/microbit-test.c
+F: tests/functional/test_arm_microbit.py
F: docs/system/arm/nrf.rst
ARM PL011 Rust device
diff --git a/tests/functional/meson.build b/tests/functional/meson.build
index b7719ab85f9..b62f7142201 100644
--- a/tests/functional/meson.build
+++ b/tests/functional/meson.build
@@ -91,6 +91,7 @@ tests_arm_system_thorough = [
'arm_cubieboard',
'arm_emcraft_sf2',
'arm_integratorcp',
+ 'arm_microbit',
'arm_orangepi',
'arm_quanta_gsj',
'arm_raspi2',
diff --git a/tests/functional/test_arm_microbit.py b/tests/functional/test_arm_microbit.py
new file mode 100755
index 00000000000..68ea4e73d62
--- /dev/null
+++ b/tests/functional/test_arm_microbit.py
@@ -0,0 +1,31 @@
+#!/usr/bin/env python3
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright 2025, The QEMU Project Developers.
+#
+# A functional test that runs MicroPython on the arm microbit machine.
+
+from qemu_test import QemuSystemTest, Asset, exec_command_and_wait_for_pattern
+from qemu_test import wait_for_console_pattern
+
+
+class MicrobitMachine(QemuSystemTest):
+
+ ASSET_MICRO = Asset('https://ozlabs.org/~joel/microbit-micropython.hex',
+ '021641f93dfb11767d4978dbb3ca7f475d1b13c69e7f4aec3382f212636bffd6')
+
+ def test_arm_microbit(self):
+ self.set_machine('microbit')
+
+ micropython = self.ASSET_MICRO.fetch()
+ self.vm.set_console()
+ self.vm.add_args('-device', f'loader,file={micropython}')
+ self.vm.launch()
+ wait_for_console_pattern(self, 'Type "help()" for more information.')
+ exec_command_and_wait_for_pattern(self, 'import machine as mch', '>>>')
+ exec_command_and_wait_for_pattern(self, 'mch.reset()', 'MicroPython')
+ wait_for_console_pattern(self, '>>>')
+
+if __name__ == '__main__':
+ QemuSystemTest.main()
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 14/36] target/arm: arm_reset_sve_state() should set FPSR, not FPCR
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (12 preceding siblings ...)
2025-01-28 20:12 ` [PULL 13/36] tests/functional: Add a test for the arm microbit machine Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 15/36] target/arm: Use FPSR_ constants in vfp_exceptbits_from_host() Peter Maydell
` (22 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
The pseudocode ResetSVEState() does:
FPSR = ZeroExtend(0x0800009f<31:0>, 64);
but QEMU's arm_reset_sve_state() called vfp_set_fpcr() by accident.
Before the advent of FEAT_AFP, this was only setting a collection of
RES0 bits, which vfp_set_fpsr() would then ignore, so the only effect
was that we didn't actually set the FPSR the way we are supposed to
do. Once FEAT_AFP is implemented, setting the bottom bits of FPSR
will change the floating point behaviour.
Call vfp_set_fpsr(), as we ought to.
(Note for stable backports: commit 7f2a01e7368f9 moved this function
from sme_helper.c to helper.c, but it had the same bug before the
move too.)
Cc: qemu-stable@nongnu.org
Fixes: f84734b87461 ("target/arm: Implement SMSTART, SMSTOP")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-4-peter.maydell@linaro.org
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 63997678513..40bdfc851a5 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6413,7 +6413,7 @@ static void arm_reset_sve_state(CPUARMState *env)
memset(env->vfp.zregs, 0, sizeof(env->vfp.zregs));
/* Recall that FFR is stored as pregs[16]. */
memset(env->vfp.pregs, 0, sizeof(env->vfp.pregs));
- vfp_set_fpcr(env, 0x0800009f);
+ vfp_set_fpsr(env, 0x0800009f);
}
void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask)
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 15/36] target/arm: Use FPSR_ constants in vfp_exceptbits_from_host()
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (13 preceding siblings ...)
2025-01-28 20:12 ` [PULL 14/36] target/arm: arm_reset_sve_state() should set FPSR, not FPCR Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 16/36] target/arm: Use uint32_t " Peter Maydell
` (21 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
Use the FPSR_ named constants in vfp_exceptbits_from_host(),
rather than hardcoded magic numbers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-5-peter.maydell@linaro.org
---
target/arm/vfp_helper.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index fc20a567530..fcc9e5d382e 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -39,22 +39,22 @@ static inline int vfp_exceptbits_from_host(int host_bits)
int target_bits = 0;
if (host_bits & float_flag_invalid) {
- target_bits |= 1;
+ target_bits |= FPSR_IOC;
}
if (host_bits & float_flag_divbyzero) {
- target_bits |= 2;
+ target_bits |= FPSR_DZC;
}
if (host_bits & float_flag_overflow) {
- target_bits |= 4;
+ target_bits |= FPSR_OFC;
}
if (host_bits & (float_flag_underflow | float_flag_output_denormal)) {
- target_bits |= 8;
+ target_bits |= FPSR_UFC;
}
if (host_bits & float_flag_inexact) {
- target_bits |= 0x10;
+ target_bits |= FPSR_IXC;
}
if (host_bits & float_flag_input_denormal) {
- target_bits |= 0x80;
+ target_bits |= FPSR_IDC;
}
return target_bits;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 16/36] target/arm: Use uint32_t in vfp_exceptbits_from_host()
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (14 preceding siblings ...)
2025-01-28 20:12 ` [PULL 15/36] target/arm: Use FPSR_ constants in vfp_exceptbits_from_host() Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 17/36] target/arm: Define new fp_status_a32 and fp_status_a64 Peter Maydell
` (20 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
In vfp_exceptbits_from_host(), we accumulate the FPSR flags in
an "int", and our return type is also "int". However, the only
callsite returns the same information as a uint32_t, and
more generally we handle FPSR values in the code as uint32_t,
not int. Bring this function in to line with that convention.
There is no behaviour change because none of the FPSR bits
we set in this function are bit 31. The input argument to
the function remains 'int' because that is the return type
of the softfloat get_float_exception_flags().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-6-peter.maydell@linaro.org
---
target/arm/vfp_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index fcc9e5d382e..afc41420eb1 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -34,9 +34,9 @@
#ifdef CONFIG_TCG
/* Convert host exception flags to vfp form. */
-static inline int vfp_exceptbits_from_host(int host_bits)
+static inline uint32_t vfp_exceptbits_from_host(int host_bits)
{
- int target_bits = 0;
+ uint32_t target_bits = 0;
if (host_bits & float_flag_invalid) {
target_bits |= FPSR_IOC;
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 17/36] target/arm: Define new fp_status_a32 and fp_status_a64
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (15 preceding siblings ...)
2025-01-28 20:12 ` [PULL 16/36] target/arm: Use uint32_t " Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 18/36] target/arm: Use vfp.fp_status_a64 in A64-only helper functions Peter Maydell
` (19 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
We want to split the existing fp_status in the Arm CPUState into
separate float_status fields for AArch32 and AArch64. (This is
because new control bits defined by FEAT_AFP only have an effect for
AArch64, not AArch32.) To make this split we will:
* define new fp_status_a32 and fp_status_a64 which have
identical behaviour to the existing fp_status
* move existing uses of fp_status to fp_status_a32 or
fp_status_a64 as appropriate
* delete the old fp_status when it has no uses left
In this patch we add the new float_status fields.
We will also need to split fp_status_f16, but we will do that
as a separate series of patches.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-7-peter.maydell@linaro.org
---
target/arm/cpu.h | 4 ++++
target/arm/tcg/translate.h | 12 ++++++++++++
target/arm/cpu.c | 2 ++
target/arm/vfp_helper.c | 12 ++++++++++++
4 files changed, 30 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9a6e8e589cc..337c5383748 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -634,6 +634,8 @@ typedef struct CPUArchState {
/* There are a number of distinct float control structures:
*
* fp_status: is the "normal" fp status.
+ * fp_status_a32: is the "normal" fp status for AArch32 insns
+ * fp_status_a64: is the "normal" fp status for AArch64 insns
* fp_status_fp16: used for half-precision calculations
* standard_fp_status : the ARM "Standard FPSCR Value"
* standard_fp_status_fp16 : used for half-precision
@@ -659,6 +661,8 @@ typedef struct CPUArchState {
* an explicit FPSCR read.
*/
float_status fp_status;
+ float_status fp_status_a32;
+ float_status fp_status_a64;
float_status fp_status_f16;
float_status standard_fp_status;
float_status standard_fp_status_f16;
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index 2d37d7c9f21..c8414d94d5e 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -671,6 +671,8 @@ static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb)
*/
typedef enum ARMFPStatusFlavour {
FPST_FPCR,
+ FPST_A32,
+ FPST_A64,
FPST_FPCR_F16,
FPST_STD,
FPST_STD_F16,
@@ -686,6 +688,10 @@ typedef enum ARMFPStatusFlavour {
*
* FPST_FPCR
* for non-FP16 operations controlled by the FPCR
+ * FPST_A32
+ * for AArch32 non-FP16 operations controlled by the FPCR
+ * FPST_A64
+ * for AArch64 non-FP16 operations controlled by the FPCR
* FPST_FPCR_F16
* for operations controlled by the FPCR where FPCR.FZ16 is to be used
* FPST_STD
@@ -702,6 +708,12 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour)
case FPST_FPCR:
offset = offsetof(CPUARMState, vfp.fp_status);
break;
+ case FPST_A32:
+ offset = offsetof(CPUARMState, vfp.fp_status_a32);
+ break;
+ case FPST_A64:
+ offset = offsetof(CPUARMState, vfp.fp_status_a64);
+ break;
case FPST_FPCR_F16:
offset = offsetof(CPUARMState, vfp.fp_status_f16);
break;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index dc0231233a6..8bdd535db95 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -573,6 +573,8 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type)
set_default_nan_mode(1, &env->vfp.standard_fp_status);
set_default_nan_mode(1, &env->vfp.standard_fp_status_f16);
arm_set_default_fp_behaviours(&env->vfp.fp_status);
+ arm_set_default_fp_behaviours(&env->vfp.fp_status_a32);
+ arm_set_default_fp_behaviours(&env->vfp.fp_status_a64);
arm_set_default_fp_behaviours(&env->vfp.standard_fp_status);
arm_set_default_fp_behaviours(&env->vfp.fp_status_f16);
arm_set_default_fp_behaviours(&env->vfp.standard_fp_status_f16);
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index afc41420eb1..7475f97e0ce 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -64,6 +64,8 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
uint32_t i;
i = get_float_exception_flags(&env->vfp.fp_status);
+ i |= get_float_exception_flags(&env->vfp.fp_status_a32);
+ i |= get_float_exception_flags(&env->vfp.fp_status_a64);
i |= get_float_exception_flags(&env->vfp.standard_fp_status);
/* FZ16 does not generate an input denormal exception. */
i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
@@ -81,6 +83,8 @@ static void vfp_clear_float_status_exc_flags(CPUARMState *env)
* be the architecturally up-to-date exception flag information first.
*/
set_float_exception_flags(0, &env->vfp.fp_status);
+ set_float_exception_flags(0, &env->vfp.fp_status_a32);
+ set_float_exception_flags(0, &env->vfp.fp_status_a64);
set_float_exception_flags(0, &env->vfp.fp_status_f16);
set_float_exception_flags(0, &env->vfp.standard_fp_status);
set_float_exception_flags(0, &env->vfp.standard_fp_status_f16);
@@ -109,6 +113,8 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
break;
}
set_float_rounding_mode(i, &env->vfp.fp_status);
+ set_float_rounding_mode(i, &env->vfp.fp_status_a32);
+ set_float_rounding_mode(i, &env->vfp.fp_status_a64);
set_float_rounding_mode(i, &env->vfp.fp_status_f16);
}
if (changed & FPCR_FZ16) {
@@ -122,10 +128,16 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
bool ftz_enabled = val & FPCR_FZ;
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
+ set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a32);
+ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_a32);
+ set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a64);
+ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_a64);
}
if (changed & FPCR_DN) {
bool dnan_enabled = val & FPCR_DN;
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
+ set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32);
+ set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 18/36] target/arm: Use vfp.fp_status_a64 in A64-only helper functions
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (16 preceding siblings ...)
2025-01-28 20:12 ` [PULL 17/36] target/arm: Define new fp_status_a32 and fp_status_a64 Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 19/36] target/arm: Use fp_status_a64 or fp_status_a32 in is_ebf() Peter Maydell
` (18 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
Switch from vfp.fp_status to vfp.fp_status_a64 for helpers which:
* directly reference an fp_status field
* are called only from the A64 decoder
* are not called inside a set_rmode/restore_rmode sequence
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250124162836.2332150-8-peter.maydell@linaro.org
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/sme_helper.c | 2 +-
target/arm/tcg/vec_helper.c | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
index a0e6b4a41ea..2aad00d3ad9 100644
--- a/target/arm/tcg/sme_helper.c
+++ b/target/arm/tcg/sme_helper.c
@@ -1044,7 +1044,7 @@ void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn,
* round-to-odd -- see above.
*/
fpst_f16 = env->vfp.fp_status_f16;
- fpst_std = env->vfp.fp_status;
+ fpst_std = env->vfp.fp_status_a64;
set_default_nan_mode(true, &fpst_std);
set_default_nan_mode(true, &fpst_f16);
fpst_odd = fpst_std;
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index e3083c6e84e..011726a72d4 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -2066,7 +2066,7 @@ void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm,
void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
CPUARMState *env, uint32_t desc)
{
- do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc,
+ do_fmlal(vd, vn, vm, &env->vfp.fp_status_a64, desc,
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
}
@@ -2076,7 +2076,7 @@ void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, void *vm, void *va,
intptr_t i, oprsz = simd_oprsz(desc);
uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15;
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
- float_status *status = &env->vfp.fp_status;
+ float_status *status = &env->vfp.fp_status_a64;
bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16);
for (i = 0; i < oprsz; i += sizeof(float32)) {
@@ -2128,7 +2128,7 @@ void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm,
void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
CPUARMState *env, uint32_t desc)
{
- do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc,
+ do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status_a64, desc,
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
}
@@ -2139,7 +2139,7 @@ void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va,
uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15;
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
intptr_t idx = extract32(desc, SIMD_DATA_SHIFT + 2, 3) * sizeof(float16);
- float_status *status = &env->vfp.fp_status;
+ float_status *status = &env->vfp.fp_status_a64;
bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16);
for (i = 0; i < oprsz; i += 16) {
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 19/36] target/arm: Use fp_status_a64 or fp_status_a32 in is_ebf()
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (17 preceding siblings ...)
2025-01-28 20:12 ` [PULL 18/36] target/arm: Use vfp.fp_status_a64 in A64-only helper functions Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 20/36] target/arm: Use fp_status_a32 in vjvct helper Peter Maydell
` (17 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
In is_ebf(), we might be called for A64 or A32, but we have
the CPUARMState* so we can select fp_status_a64 or
fp_status_a32 accordingly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/vec_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index 011726a72d4..2ba1f7cb32e 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -2808,7 +2808,7 @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp)
*/
bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF;
- *statusp = env->vfp.fp_status;
+ *statusp = is_a64(env) ? env->vfp.fp_status_a64 : env->vfp.fp_status_a32;
set_default_nan_mode(true, statusp);
if (ebf) {
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 20/36] target/arm: Use fp_status_a32 in vjvct helper
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (18 preceding siblings ...)
2025-01-28 20:12 ` [PULL 19/36] target/arm: Use fp_status_a64 or fp_status_a32 in is_ebf() Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:12 ` [PULL 21/36] target/arm: Use fp_status_a32 in vfp_cmp helpers Peter Maydell
` (16 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
Use fp_status_a32 in the vjcvt helper function; this is called only
from the A32/T32 decoder and is not used inside a
set_rmode/restore_rmode sequence.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-9-peter.maydell@linaro.org
---
target/arm/vfp_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 7475f97e0ce..0671ba3a88b 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -1144,7 +1144,7 @@ uint64_t HELPER(fjcvtzs)(float64 value, float_status *status)
uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env)
{
- uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status);
+ uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status_a32);
uint32_t result = pair;
uint32_t z = (pair >> 32) == 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 21/36] target/arm: Use fp_status_a32 in vfp_cmp helpers
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (19 preceding siblings ...)
2025-01-28 20:12 ` [PULL 20/36] target/arm: Use fp_status_a32 in vjvct helper Peter Maydell
@ 2025-01-28 20:12 ` Peter Maydell
2025-01-28 20:13 ` [PULL 22/36] target/arm: Use FPST_A32 in A32 decoder Peter Maydell
` (15 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:12 UTC (permalink / raw)
To: qemu-devel
The helpers vfp_cmps, vfp_cmpes, vfp_cmpd, vfp_cmped are used only from
the A32 decoder; the A64 decoder uses separate vfp_cmps_a64 etc helpers
(because for A64 we update the main NZCV flags and for A32 we update
the FPSCR NZCV flags). So we can make these helpers use the fp_status_a32
field instead of fp_status.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-10-peter.maydell@linaro.org
---
target/arm/vfp_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 0671ba3a88b..034f26e5daa 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -373,8 +373,8 @@ void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \
}
DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status_f16)
-DO_VFP_cmp(s, float32, float32, fp_status)
-DO_VFP_cmp(d, float64, float64, fp_status)
+DO_VFP_cmp(s, float32, float32, fp_status_a32)
+DO_VFP_cmp(d, float64, float64, fp_status_a32)
#undef DO_VFP_cmp
/* Integer to float and float to integer conversions */
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 22/36] target/arm: Use FPST_A32 in A32 decoder
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (20 preceding siblings ...)
2025-01-28 20:12 ` [PULL 21/36] target/arm: Use fp_status_a32 in vfp_cmp helpers Peter Maydell
@ 2025-01-28 20:13 ` Peter Maydell
2025-01-28 20:13 ` [PULL 23/36] target/arm: Use FPST_A64 in A64 decoder Peter Maydell
` (14 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:13 UTC (permalink / raw)
To: qemu-devel
In the A32 decoder, use FPST_A32 rather than FPST_FPCR. By
doing an automated conversion of the whole file we avoid possibly
using more than one fpst value in a set_rmode/op/restore_rmode
sequence.
Patch created with
perl -p -i -e 's/FPST_FPCR(?!_)/FPST_A32/g' target/arm/tcg/translate-vfp.c
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-11-peter.maydell@linaro.org
---
target/arm/tcg/translate-vfp.c | 54 +++++++++++++++++-----------------
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c
index 3cbe9a7418d..c82f41234cd 100644
--- a/target/arm/tcg/translate-vfp.c
+++ b/target/arm/tcg/translate-vfp.c
@@ -462,7 +462,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
if (sz == 1) {
fpst = fpstatus_ptr(FPST_FPCR_F16);
} else {
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
}
tcg_rmode = gen_set_rmode(rounding, fpst);
@@ -529,7 +529,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
if (sz == 1) {
fpst = fpstatus_ptr(FPST_FPCR_F16);
} else {
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
}
tcg_shift = tcg_constant_i32(0);
@@ -1398,7 +1398,7 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
f0 = tcg_temp_new_i32();
f1 = tcg_temp_new_i32();
fd = tcg_temp_new_i32();
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
vfp_load_reg32(f0, vn);
vfp_load_reg32(f1, vm);
@@ -1517,7 +1517,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
f0 = tcg_temp_new_i64();
f1 = tcg_temp_new_i64();
fd = tcg_temp_new_i64();
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
vfp_load_reg64(f0, vn);
vfp_load_reg64(f1, vm);
@@ -2181,7 +2181,7 @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
/* VFNMA, VFNMS */
gen_vfp_negs(vd, vd);
}
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
gen_helper_vfp_muladds(vd, vn, vm, vd, fpst);
vfp_store_reg32(vd, a->vd);
return true;
@@ -2246,7 +2246,7 @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d)
/* VFNMA, VFNMS */
gen_vfp_negd(vd, vd);
}
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst);
vfp_store_reg64(vd, a->vd);
return true;
@@ -2429,12 +2429,12 @@ static void gen_VSQRT_hp(TCGv_i32 vd, TCGv_i32 vm)
static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm)
{
- gen_helper_vfp_sqrts(vd, vm, fpstatus_ptr(FPST_FPCR));
+ gen_helper_vfp_sqrts(vd, vm, fpstatus_ptr(FPST_A32));
}
static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm)
{
- gen_helper_vfp_sqrtd(vd, vm, fpstatus_ptr(FPST_FPCR));
+ gen_helper_vfp_sqrtd(vd, vm, fpstatus_ptr(FPST_A32));
}
DO_VFP_2OP(VSQRT, hp, gen_VSQRT_hp, aa32_fp16_arith)
@@ -2565,7 +2565,7 @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a)
return true;
}
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
ahp_mode = get_ahp_flag();
tmp = tcg_temp_new_i32();
/* The T bit tells us if we want the low or high 16 bits of Vm */
@@ -2599,7 +2599,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
return true;
}
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
ahp_mode = get_ahp_flag();
tmp = tcg_temp_new_i32();
/* The T bit tells us if we want the low or high 16 bits of Vm */
@@ -2623,7 +2623,7 @@ static bool trans_VCVT_b16_f32(DisasContext *s, arg_VCVT_b16_f32 *a)
return true;
}
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
@@ -2646,7 +2646,7 @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a)
return true;
}
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
ahp_mode = get_ahp_flag();
tmp = tcg_temp_new_i32();
@@ -2680,7 +2680,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
return true;
}
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
ahp_mode = get_ahp_flag();
tmp = tcg_temp_new_i32();
vm = tcg_temp_new_i64();
@@ -2727,7 +2727,7 @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
gen_helper_rints(tmp, tmp, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
@@ -2757,7 +2757,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
tmp = tcg_temp_new_i64();
vfp_load_reg64(tmp, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
gen_helper_rintd(tmp, tmp, fpst);
vfp_store_reg64(tmp, a->vd);
return true;
@@ -2803,7 +2803,7 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rints(tmp, tmp, fpst);
gen_restore_rmode(tcg_rmode, fpst);
@@ -2836,7 +2836,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
tmp = tcg_temp_new_i64();
vfp_load_reg64(tmp, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rintd(tmp, tmp, fpst);
gen_restore_rmode(tcg_rmode, fpst);
@@ -2880,7 +2880,7 @@ static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
gen_helper_rints_exact(tmp, tmp, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
@@ -2910,7 +2910,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
tmp = tcg_temp_new_i64();
vfp_load_reg64(tmp, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
gen_helper_rintd_exact(tmp, tmp, fpst);
vfp_store_reg64(tmp, a->vd);
return true;
@@ -2937,7 +2937,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
vm = tcg_temp_new_i32();
vd = tcg_temp_new_i64();
vfp_load_reg32(vm, a->vm);
- gen_helper_vfp_fcvtds(vd, vm, fpstatus_ptr(FPST_FPCR));
+ gen_helper_vfp_fcvtds(vd, vm, fpstatus_ptr(FPST_A32));
vfp_store_reg64(vd, a->vd);
return true;
}
@@ -2963,7 +2963,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
vd = tcg_temp_new_i32();
vm = tcg_temp_new_i64();
vfp_load_reg64(vm, a->vm);
- gen_helper_vfp_fcvtsd(vd, vm, fpstatus_ptr(FPST_FPCR));
+ gen_helper_vfp_fcvtsd(vd, vm, fpstatus_ptr(FPST_A32));
vfp_store_reg32(vd, a->vd);
return true;
}
@@ -3010,7 +3010,7 @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
vm = tcg_temp_new_i32();
vfp_load_reg32(vm, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
if (a->s) {
/* i32 -> f32 */
gen_helper_vfp_sitos(vm, vm, fpst);
@@ -3044,7 +3044,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
vm = tcg_temp_new_i32();
vd = tcg_temp_new_i64();
vfp_load_reg32(vm, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
if (a->s) {
/* i32 -> f64 */
gen_helper_vfp_sitod(vd, vm, fpst);
@@ -3161,7 +3161,7 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
vd = tcg_temp_new_i32();
vfp_load_reg32(vd, a->vd);
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
shift = tcg_constant_i32(frac_bits);
/* Switch on op:U:sx bits */
@@ -3223,7 +3223,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
vd = tcg_temp_new_i64();
vfp_load_reg64(vd, a->vd);
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
shift = tcg_constant_i32(frac_bits);
/* Switch on op:U:sx bits */
@@ -3307,7 +3307,7 @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
return true;
}
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
vm = tcg_temp_new_i32();
vfp_load_reg32(vm, a->vm);
@@ -3347,7 +3347,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
return true;
}
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A32);
vm = tcg_temp_new_i64();
vd = tcg_temp_new_i32();
vfp_load_reg64(vm, a->vm);
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 23/36] target/arm: Use FPST_A64 in A64 decoder
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (21 preceding siblings ...)
2025-01-28 20:13 ` [PULL 22/36] target/arm: Use FPST_A32 in A32 decoder Peter Maydell
@ 2025-01-28 20:13 ` Peter Maydell
2025-01-28 20:13 ` [PULL 24/36] target/arm: Remove now-unused vfp.fp_status and FPST_FPCR Peter Maydell
` (13 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:13 UTC (permalink / raw)
To: qemu-devel
In the A64 decoder, use FPST_A64 rather than FPST_FPCR. By
doing an automated conversion of the whole file we avoid possibly
using more than one fpst value in a set_rmode/op/restore_rmode
sequence.
Patch created with
perl -p -i -e 's/FPST_FPCR(?!_)/FPST_A64/g' target/arm/tcg/translate-{a64,sve,sme}.c
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-12-peter.maydell@linaro.org
---
target/arm/tcg/translate-a64.c | 70 +++++++++++-----------
target/arm/tcg/translate-sme.c | 4 +-
target/arm/tcg/translate-sve.c | 106 ++++++++++++++++-----------------
3 files changed, 90 insertions(+), 90 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index bd814849c19..d9c00713675 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -726,7 +726,7 @@ static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn,
int rm, bool is_fp16, int data,
gen_helper_gvec_3_ptr *fn)
{
- TCGv_ptr fpst = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR);
+ TCGv_ptr fpst = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_A64);
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm), fpst,
@@ -768,7 +768,7 @@ static void gen_gvec_op4_fpst(DisasContext *s, bool is_q, int rd, int rn,
int rm, int ra, bool is_fp16, int data,
gen_helper_gvec_4_ptr *fn)
{
- TCGv_ptr fpst = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR);
+ TCGv_ptr fpst = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_A64);
tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm),
@@ -5043,7 +5043,7 @@ static bool do_fp3_scalar(DisasContext *s, arg_rrr_e *a, const FPScalar *f)
if (fp_access_check(s)) {
TCGv_i64 t0 = read_fp_dreg(s, a->rn);
TCGv_i64 t1 = read_fp_dreg(s, a->rm);
- f->gen_d(t0, t0, t1, fpstatus_ptr(FPST_FPCR));
+ f->gen_d(t0, t0, t1, fpstatus_ptr(FPST_A64));
write_fp_dreg(s, a->rd, t0);
}
break;
@@ -5051,7 +5051,7 @@ static bool do_fp3_scalar(DisasContext *s, arg_rrr_e *a, const FPScalar *f)
if (fp_access_check(s)) {
TCGv_i32 t0 = read_fp_sreg(s, a->rn);
TCGv_i32 t1 = read_fp_sreg(s, a->rm);
- f->gen_s(t0, t0, t1, fpstatus_ptr(FPST_FPCR));
+ f->gen_s(t0, t0, t1, fpstatus_ptr(FPST_A64));
write_fp_sreg(s, a->rd, t0);
}
break;
@@ -5243,9 +5243,9 @@ static bool do_fcmp0_s(DisasContext *s, arg_rr_e *a,
TCGv_i64 t0 = read_fp_dreg(s, a->rn);
TCGv_i64 t1 = tcg_constant_i64(0);
if (swap) {
- f->gen_d(t0, t1, t0, fpstatus_ptr(FPST_FPCR));
+ f->gen_d(t0, t1, t0, fpstatus_ptr(FPST_A64));
} else {
- f->gen_d(t0, t0, t1, fpstatus_ptr(FPST_FPCR));
+ f->gen_d(t0, t0, t1, fpstatus_ptr(FPST_A64));
}
write_fp_dreg(s, a->rd, t0);
}
@@ -5255,9 +5255,9 @@ static bool do_fcmp0_s(DisasContext *s, arg_rr_e *a,
TCGv_i32 t0 = read_fp_sreg(s, a->rn);
TCGv_i32 t1 = tcg_constant_i32(0);
if (swap) {
- f->gen_s(t0, t1, t0, fpstatus_ptr(FPST_FPCR));
+ f->gen_s(t0, t1, t0, fpstatus_ptr(FPST_A64));
} else {
- f->gen_s(t0, t0, t1, fpstatus_ptr(FPST_FPCR));
+ f->gen_s(t0, t0, t1, fpstatus_ptr(FPST_A64));
}
write_fp_sreg(s, a->rd, t0);
}
@@ -6207,7 +6207,7 @@ static bool do_fp3_scalar_idx(DisasContext *s, arg_rrx_e *a, const FPScalar *f)
TCGv_i64 t1 = tcg_temp_new_i64();
read_vec_element(s, t1, a->rm, a->idx, MO_64);
- f->gen_d(t0, t0, t1, fpstatus_ptr(FPST_FPCR));
+ f->gen_d(t0, t0, t1, fpstatus_ptr(FPST_A64));
write_fp_dreg(s, a->rd, t0);
}
break;
@@ -6217,7 +6217,7 @@ static bool do_fp3_scalar_idx(DisasContext *s, arg_rrx_e *a, const FPScalar *f)
TCGv_i32 t1 = tcg_temp_new_i32();
read_vec_element_i32(s, t1, a->rm, a->idx, MO_32);
- f->gen_s(t0, t0, t1, fpstatus_ptr(FPST_FPCR));
+ f->gen_s(t0, t0, t1, fpstatus_ptr(FPST_A64));
write_fp_sreg(s, a->rd, t0);
}
break;
@@ -6256,7 +6256,7 @@ static bool do_fmla_scalar_idx(DisasContext *s, arg_rrx_e *a, bool neg)
if (neg) {
gen_vfp_negd(t1, t1);
}
- gen_helper_vfp_muladdd(t0, t1, t2, t0, fpstatus_ptr(FPST_FPCR));
+ gen_helper_vfp_muladdd(t0, t1, t2, t0, fpstatus_ptr(FPST_A64));
write_fp_dreg(s, a->rd, t0);
}
break;
@@ -6270,7 +6270,7 @@ static bool do_fmla_scalar_idx(DisasContext *s, arg_rrx_e *a, bool neg)
if (neg) {
gen_vfp_negs(t1, t1);
}
- gen_helper_vfp_muladds(t0, t1, t2, t0, fpstatus_ptr(FPST_FPCR));
+ gen_helper_vfp_muladds(t0, t1, t2, t0, fpstatus_ptr(FPST_A64));
write_fp_sreg(s, a->rd, t0);
}
break;
@@ -6601,7 +6601,7 @@ static bool do_fp3_scalar_pair(DisasContext *s, arg_rr_e *a, const FPScalar *f)
read_vec_element(s, t0, a->rn, 0, MO_64);
read_vec_element(s, t1, a->rn, 1, MO_64);
- f->gen_d(t0, t0, t1, fpstatus_ptr(FPST_FPCR));
+ f->gen_d(t0, t0, t1, fpstatus_ptr(FPST_A64));
write_fp_dreg(s, a->rd, t0);
}
break;
@@ -6612,7 +6612,7 @@ static bool do_fp3_scalar_pair(DisasContext *s, arg_rr_e *a, const FPScalar *f)
read_vec_element_i32(s, t0, a->rn, 0, MO_32);
read_vec_element_i32(s, t1, a->rn, 1, MO_32);
- f->gen_s(t0, t0, t1, fpstatus_ptr(FPST_FPCR));
+ f->gen_s(t0, t0, t1, fpstatus_ptr(FPST_A64));
write_fp_sreg(s, a->rd, t0);
}
break;
@@ -6762,7 +6762,7 @@ static bool do_fmadd(DisasContext *s, arg_rrrr_e *a, bool neg_a, bool neg_n)
if (neg_n) {
gen_vfp_negd(tn, tn);
}
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A64);
gen_helper_vfp_muladdd(ta, tn, tm, ta, fpst);
write_fp_dreg(s, a->rd, ta);
}
@@ -6780,7 +6780,7 @@ static bool do_fmadd(DisasContext *s, arg_rrrr_e *a, bool neg_a, bool neg_n)
if (neg_n) {
gen_vfp_negs(tn, tn);
}
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A64);
gen_helper_vfp_muladds(ta, tn, tm, ta, fpst);
write_fp_sreg(s, a->rd, ta);
}
@@ -6895,7 +6895,7 @@ static bool do_fp_reduction(DisasContext *s, arg_qrr_e *a,
if (fp_access_check(s)) {
MemOp esz = a->esz;
int elts = (a->q ? 16 : 8) >> esz;
- TCGv_ptr fpst = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ TCGv_ptr fpst = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
TCGv_i32 res = do_reduction_op(s, a->rn, esz, 0, elts, fpst, fn);
write_fp_sreg(s, a->rd, res);
}
@@ -6939,7 +6939,7 @@ static void handle_fp_compare(DisasContext *s, int size,
bool cmp_with_zero, bool signal_all_nans)
{
TCGv_i64 tcg_flags = tcg_temp_new_i64();
- TCGv_ptr fpst = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ TCGv_ptr fpst = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_A64);
if (size == MO_64) {
TCGv_i64 tcg_vn, tcg_vm;
@@ -8407,7 +8407,7 @@ static bool do_fp1_scalar(DisasContext *s, arg_rr_e *a,
return check == 0;
}
- fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
if (rmode >= 0) {
tcg_rmode = gen_set_rmode(rmode, fpst);
}
@@ -8513,7 +8513,7 @@ static bool trans_FCVT_s_ds(DisasContext *s, arg_rr *a)
if (fp_access_check(s)) {
TCGv_i32 tcg_rn = read_fp_sreg(s, a->rn);
TCGv_i64 tcg_rd = tcg_temp_new_i64();
- TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
+ TCGv_ptr fpst = fpstatus_ptr(FPST_A64);
gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, fpst);
write_fp_dreg(s, a->rd, tcg_rd);
@@ -8526,7 +8526,7 @@ static bool trans_FCVT_s_hs(DisasContext *s, arg_rr *a)
if (fp_access_check(s)) {
TCGv_i32 tmp = read_fp_sreg(s, a->rn);
TCGv_i32 ahp = get_ahp_flag();
- TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
+ TCGv_ptr fpst = fpstatus_ptr(FPST_A64);
gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
/* write_fp_sreg is OK here because top half of result is zero */
@@ -8540,7 +8540,7 @@ static bool trans_FCVT_s_sd(DisasContext *s, arg_rr *a)
if (fp_access_check(s)) {
TCGv_i64 tcg_rn = read_fp_dreg(s, a->rn);
TCGv_i32 tcg_rd = tcg_temp_new_i32();
- TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
+ TCGv_ptr fpst = fpstatus_ptr(FPST_A64);
gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, fpst);
write_fp_sreg(s, a->rd, tcg_rd);
@@ -8554,7 +8554,7 @@ static bool trans_FCVT_s_hd(DisasContext *s, arg_rr *a)
TCGv_i64 tcg_rn = read_fp_dreg(s, a->rn);
TCGv_i32 tcg_rd = tcg_temp_new_i32();
TCGv_i32 ahp = get_ahp_flag();
- TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
+ TCGv_ptr fpst = fpstatus_ptr(FPST_A64);
gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp);
/* write_fp_sreg is OK here because top half of tcg_rd is zero */
@@ -8568,7 +8568,7 @@ static bool trans_FCVT_s_sh(DisasContext *s, arg_rr *a)
if (fp_access_check(s)) {
TCGv_i32 tcg_rn = read_fp_hreg(s, a->rn);
TCGv_i32 tcg_rd = tcg_temp_new_i32();
- TCGv_ptr tcg_fpst = fpstatus_ptr(FPST_FPCR);
+ TCGv_ptr tcg_fpst = fpstatus_ptr(FPST_A64);
TCGv_i32 tcg_ahp = get_ahp_flag();
gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
@@ -8582,7 +8582,7 @@ static bool trans_FCVT_s_dh(DisasContext *s, arg_rr *a)
if (fp_access_check(s)) {
TCGv_i32 tcg_rn = read_fp_hreg(s, a->rn);
TCGv_i64 tcg_rd = tcg_temp_new_i64();
- TCGv_ptr tcg_fpst = fpstatus_ptr(FPST_FPCR);
+ TCGv_ptr tcg_fpst = fpstatus_ptr(FPST_A64);
TCGv_i32 tcg_ahp = get_ahp_flag();
gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
@@ -8598,7 +8598,7 @@ static bool do_cvtf_scalar(DisasContext *s, MemOp esz, int rd, int shift,
TCGv_i32 tcg_shift, tcg_single;
TCGv_i64 tcg_double;
- tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
tcg_shift = tcg_constant_i32(shift);
switch (esz) {
@@ -8693,7 +8693,7 @@ static void do_fcvt_scalar(DisasContext *s, MemOp out, MemOp esz,
TCGv_ptr tcg_fpstatus;
TCGv_i32 tcg_shift, tcg_rmode, tcg_single;
- tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
tcg_shift = tcg_constant_i32(shift);
tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
@@ -8857,7 +8857,7 @@ static bool trans_FJCVTZS(DisasContext *s, arg_FJCVTZS *a)
}
if (fp_access_check(s)) {
TCGv_i64 t = read_fp_dreg(s, a->rn);
- TCGv_ptr fpstatus = fpstatus_ptr(FPST_FPCR);
+ TCGv_ptr fpstatus = fpstatus_ptr(FPST_A64);
gen_helper_fjcvtzs(t, t, fpstatus);
@@ -9115,7 +9115,7 @@ static void gen_fcvtxn_sd(TCGv_i64 d, TCGv_i64 n)
* with von Neumann rounding (round to odd)
*/
TCGv_i32 tmp = tcg_temp_new_i32();
- gen_helper_fcvtx_f64_to_f32(tmp, n, fpstatus_ptr(FPST_FPCR));
+ gen_helper_fcvtx_f64_to_f32(tmp, n, fpstatus_ptr(FPST_A64));
tcg_gen_extu_i32_i64(d, tmp);
}
@@ -9208,7 +9208,7 @@ static void gen_fcvtn_hs(TCGv_i64 d, TCGv_i64 n)
{
TCGv_i32 tcg_lo = tcg_temp_new_i32();
TCGv_i32 tcg_hi = tcg_temp_new_i32();
- TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
+ TCGv_ptr fpst = fpstatus_ptr(FPST_A64);
TCGv_i32 ahp = get_ahp_flag();
tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, n);
@@ -9221,7 +9221,7 @@ static void gen_fcvtn_hs(TCGv_i64 d, TCGv_i64 n)
static void gen_fcvtn_sd(TCGv_i64 d, TCGv_i64 n)
{
TCGv_i32 tmp = tcg_temp_new_i32();
- TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
+ TCGv_ptr fpst = fpstatus_ptr(FPST_A64);
gen_helper_vfp_fcvtsd(tmp, n, fpst);
tcg_gen_extu_i32_i64(d, tmp);
@@ -9237,7 +9237,7 @@ TRANS(FCVTXN_v, do_2misc_narrow_vector, a, f_scalar_fcvtxn)
static void gen_bfcvtn_hs(TCGv_i64 d, TCGv_i64 n)
{
- TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
+ TCGv_ptr fpst = fpstatus_ptr(FPST_A64);
TCGv_i32 tmp = tcg_temp_new_i32();
gen_helper_bfcvt_pair(tmp, n, fpst);
tcg_gen_extu_i32_i64(d, tmp);
@@ -9312,7 +9312,7 @@ static bool do_fp1_vector(DisasContext *s, arg_qrr_e *a,
return check == 0;
}
- fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
if (rmode >= 0) {
tcg_rmode = gen_set_rmode(rmode, fpst);
}
@@ -9372,7 +9372,7 @@ static bool do_gvec_op2_fpst(DisasContext *s, MemOp esz, bool is_q,
return check == 0;
}
- fpst = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ fpst = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn), fpst,
is_q ? 16 : 8, vec_full_reg_size(s),
@@ -9511,7 +9511,7 @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
return true;
}
- fpst = fpstatus_ptr(FPST_FPCR);
+ fpst = fpstatus_ptr(FPST_A64);
if (a->esz == MO_64) {
/* 32 -> 64 bit fp conversion */
TCGv_i64 tcg_res[2];
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
index 01ece570164..fcbb3500161 100644
--- a/target/arm/tcg/translate-sme.c
+++ b/target/arm/tcg/translate-sme.c
@@ -358,9 +358,9 @@ static bool do_outprod_env(DisasContext *s, arg_op *a, MemOp esz,
TRANS_FEAT(FMOPA_h, aa64_sme, do_outprod_env, a,
MO_32, gen_helper_sme_fmopa_h)
TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a,
- MO_32, FPST_FPCR, gen_helper_sme_fmopa_s)
+ MO_32, FPST_A64, gen_helper_sme_fmopa_s)
TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a,
- MO_64, FPST_FPCR, gen_helper_sme_fmopa_d)
+ MO_64, FPST_A64, gen_helper_sme_fmopa_d)
TRANS_FEAT(BFMOPA, aa64_sme, do_outprod_env, a, MO_32, gen_helper_sme_bfmopa)
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index e3031965920..d32a67331df 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -141,7 +141,7 @@ static bool gen_gvec_fpst_arg_zz(DisasContext *s, gen_helper_gvec_2_ptr *fn,
arg_rr_esz *a, int data)
{
return gen_gvec_fpst_zz(s, fn, a->rd, a->rn, data,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
}
/* Invoke an out-of-line helper on 3 Zregs. */
@@ -191,7 +191,7 @@ static bool gen_gvec_fpst_arg_zzz(DisasContext *s, gen_helper_gvec_3_ptr *fn,
arg_rrr_esz *a, int data)
{
return gen_gvec_fpst_zzz(s, fn, a->rd, a->rn, a->rm, data,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
}
/* Invoke an out-of-line helper on 4 Zregs. */
@@ -397,7 +397,7 @@ static bool gen_gvec_fpst_arg_zpzz(DisasContext *s, gen_helper_gvec_4_ptr *fn,
arg_rprr_esz *a)
{
return gen_gvec_fpst_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
}
/* Invoke a vector expander on two Zregs and an immediate. */
@@ -3517,7 +3517,7 @@ static bool do_FMLA_zzxz(DisasContext *s, arg_rrxr_esz *a, bool sub)
};
return gen_gvec_fpst_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra,
(a->index << 1) | sub,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
}
TRANS_FEAT(FMLA_zzxz, aa64_sve, do_FMLA_zzxz, a, false)
@@ -3533,7 +3533,7 @@ static gen_helper_gvec_3_ptr * const fmul_idx_fns[4] = {
};
TRANS_FEAT(FMUL_zzx, aa64_sve, gen_gvec_fpst_zzz,
fmul_idx_fns[a->esz], a->rd, a->rn, a->rm, a->index,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
/*
*** SVE Floating Point Fast Reduction Group
@@ -3566,7 +3566,7 @@ static bool do_reduce(DisasContext *s, arg_rpr_esz *a,
tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg));
- status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
fn(temp, t_zn, t_pg, status, t_desc);
@@ -3618,7 +3618,7 @@ static bool do_ppz_fp(DisasContext *s, arg_rpr_esz *a,
if (sve_access_check(s)) {
unsigned vsz = vec_full_reg_size(s);
TCGv_ptr status =
- fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
tcg_gen_gvec_3_ptr(pred_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
@@ -3654,7 +3654,7 @@ static gen_helper_gvec_3_ptr * const ftmad_fns[4] = {
};
TRANS_FEAT_NONSTREAMING(FTMAD, aa64_sve, gen_gvec_fpst_zzz,
ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
/*
*** SVE Floating Point Accumulating Reduction Group
@@ -3687,7 +3687,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_rm, tcg_env, vec_full_reg_offset(s, a->rm));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg));
- t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
t_desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc);
@@ -3762,7 +3762,7 @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16,
tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, zn));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
- status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR);
+ status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_A64);
desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
fn(t_zd, t_zn, t_pg, scalar, status, desc);
}
@@ -3814,7 +3814,7 @@ static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *a,
}
if (sve_access_check(s)) {
unsigned vsz = vec_full_reg_size(s);
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
tcg_gen_gvec_4_ptr(pred_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm),
@@ -3847,7 +3847,7 @@ static gen_helper_gvec_4_ptr * const fcadd_fns[] = {
};
TRANS_FEAT(FCADD, aa64_sve, gen_gvec_fpst_zzzp, fcadd_fns[a->esz],
a->rd, a->rn, a->rm, a->pg, a->rot,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
#define DO_FMLA(NAME, name) \
static gen_helper_gvec_5_ptr * const name##_fns[4] = { \
@@ -3856,7 +3856,7 @@ TRANS_FEAT(FCADD, aa64_sve, gen_gvec_fpst_zzzp, fcadd_fns[a->esz],
}; \
TRANS_FEAT(NAME, aa64_sve, gen_gvec_fpst_zzzzp, name##_fns[a->esz], \
a->rd, a->rn, a->rm, a->ra, a->pg, 0, \
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
DO_FMLA(FMLA_zpzzz, fmla_zpzzz)
DO_FMLA(FMLS_zpzzz, fmls_zpzzz)
@@ -3871,35 +3871,35 @@ static gen_helper_gvec_5_ptr * const fcmla_fns[4] = {
};
TRANS_FEAT(FCMLA_zpzzz, aa64_sve, gen_gvec_fpst_zzzzp, fcmla_fns[a->esz],
a->rd, a->rn, a->rm, a->ra, a->pg, a->rot,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
static gen_helper_gvec_4_ptr * const fcmla_idx_fns[4] = {
NULL, gen_helper_gvec_fcmlah_idx, gen_helper_gvec_fcmlas_idx, NULL
};
TRANS_FEAT(FCMLA_zzxz, aa64_sve, gen_gvec_fpst_zzzz, fcmla_idx_fns[a->esz],
a->rd, a->rn, a->rm, a->ra, a->index * 4 + a->rot,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
/*
*** SVE Floating Point Unary Operations Predicated Group
*/
TRANS_FEAT(FCVT_sh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvt_sh, a, 0, FPST_FPCR)
+ gen_helper_sve_fcvt_sh, a, 0, FPST_A64)
TRANS_FEAT(FCVT_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvt_hs, a, 0, FPST_FPCR)
+ gen_helper_sve_fcvt_hs, a, 0, FPST_A64)
TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_bfcvt, a, 0, FPST_FPCR)
+ gen_helper_sve_bfcvt, a, 0, FPST_A64)
TRANS_FEAT(FCVT_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvt_dh, a, 0, FPST_FPCR)
+ gen_helper_sve_fcvt_dh, a, 0, FPST_A64)
TRANS_FEAT(FCVT_hd, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvt_hd, a, 0, FPST_FPCR)
+ gen_helper_sve_fcvt_hd, a, 0, FPST_A64)
TRANS_FEAT(FCVT_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvt_ds, a, 0, FPST_FPCR)
+ gen_helper_sve_fcvt_ds, a, 0, FPST_A64)
TRANS_FEAT(FCVT_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvt_sd, a, 0, FPST_FPCR)
+ gen_helper_sve_fcvt_sd, a, 0, FPST_A64)
TRANS_FEAT(FCVTZS_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_fcvtzs_hh, a, 0, FPST_FPCR_F16)
@@ -3915,22 +3915,22 @@ TRANS_FEAT(FCVTZU_hd, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_fcvtzu_hd, a, 0, FPST_FPCR_F16)
TRANS_FEAT(FCVTZS_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzs_ss, a, 0, FPST_FPCR)
+ gen_helper_sve_fcvtzs_ss, a, 0, FPST_A64)
TRANS_FEAT(FCVTZU_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzu_ss, a, 0, FPST_FPCR)
+ gen_helper_sve_fcvtzu_ss, a, 0, FPST_A64)
TRANS_FEAT(FCVTZS_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzs_sd, a, 0, FPST_FPCR)
+ gen_helper_sve_fcvtzs_sd, a, 0, FPST_A64)
TRANS_FEAT(FCVTZU_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzu_sd, a, 0, FPST_FPCR)
+ gen_helper_sve_fcvtzu_sd, a, 0, FPST_A64)
TRANS_FEAT(FCVTZS_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzs_ds, a, 0, FPST_FPCR)
+ gen_helper_sve_fcvtzs_ds, a, 0, FPST_A64)
TRANS_FEAT(FCVTZU_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzu_ds, a, 0, FPST_FPCR)
+ gen_helper_sve_fcvtzu_ds, a, 0, FPST_A64)
TRANS_FEAT(FCVTZS_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzs_dd, a, 0, FPST_FPCR)
+ gen_helper_sve_fcvtzs_dd, a, 0, FPST_A64)
TRANS_FEAT(FCVTZU_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzu_dd, a, 0, FPST_FPCR)
+ gen_helper_sve_fcvtzu_dd, a, 0, FPST_A64)
static gen_helper_gvec_3_ptr * const frint_fns[] = {
NULL,
@@ -3939,7 +3939,7 @@ static gen_helper_gvec_3_ptr * const frint_fns[] = {
gen_helper_sve_frint_d
};
TRANS_FEAT(FRINTI, aa64_sve, gen_gvec_fpst_arg_zpz, frint_fns[a->esz],
- a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
static gen_helper_gvec_3_ptr * const frintx_fns[] = {
NULL,
@@ -3948,7 +3948,7 @@ static gen_helper_gvec_3_ptr * const frintx_fns[] = {
gen_helper_sve_frintx_d
};
TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz],
- a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
ARMFPRounding mode, gen_helper_gvec_3_ptr *fn)
@@ -3965,7 +3965,7 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
}
vsz = vec_full_reg_size(s);
- status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
tmode = gen_set_rmode(mode, status);
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
@@ -3993,14 +3993,14 @@ static gen_helper_gvec_3_ptr * const frecpx_fns[] = {
gen_helper_sve_frecpx_s, gen_helper_sve_frecpx_d,
};
TRANS_FEAT(FRECPX, aa64_sve, gen_gvec_fpst_arg_zpz, frecpx_fns[a->esz],
- a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
static gen_helper_gvec_3_ptr * const fsqrt_fns[] = {
NULL, gen_helper_sve_fsqrt_h,
gen_helper_sve_fsqrt_s, gen_helper_sve_fsqrt_d,
};
TRANS_FEAT(FSQRT, aa64_sve, gen_gvec_fpst_arg_zpz, fsqrt_fns[a->esz],
- a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
TRANS_FEAT(SCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_scvt_hh, a, 0, FPST_FPCR_F16)
@@ -4010,14 +4010,14 @@ TRANS_FEAT(SCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_scvt_dh, a, 0, FPST_FPCR_F16)
TRANS_FEAT(SCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_scvt_ss, a, 0, FPST_FPCR)
+ gen_helper_sve_scvt_ss, a, 0, FPST_A64)
TRANS_FEAT(SCVTF_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_scvt_ds, a, 0, FPST_FPCR)
+ gen_helper_sve_scvt_ds, a, 0, FPST_A64)
TRANS_FEAT(SCVTF_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_scvt_sd, a, 0, FPST_FPCR)
+ gen_helper_sve_scvt_sd, a, 0, FPST_A64)
TRANS_FEAT(SCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_scvt_dd, a, 0, FPST_FPCR)
+ gen_helper_sve_scvt_dd, a, 0, FPST_A64)
TRANS_FEAT(UCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_ucvt_hh, a, 0, FPST_FPCR_F16)
@@ -4027,14 +4027,14 @@ TRANS_FEAT(UCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_ucvt_dh, a, 0, FPST_FPCR_F16)
TRANS_FEAT(UCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_ucvt_ss, a, 0, FPST_FPCR)
+ gen_helper_sve_ucvt_ss, a, 0, FPST_A64)
TRANS_FEAT(UCVTF_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_ucvt_ds, a, 0, FPST_FPCR)
+ gen_helper_sve_ucvt_ds, a, 0, FPST_A64)
TRANS_FEAT(UCVTF_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_ucvt_sd, a, 0, FPST_FPCR)
+ gen_helper_sve_ucvt_sd, a, 0, FPST_A64)
TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_ucvt_dd, a, 0, FPST_FPCR)
+ gen_helper_sve_ucvt_dd, a, 0, FPST_A64)
/*
*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
@@ -6916,10 +6916,10 @@ DO_ZPZZ_FP(FMINP, aa64_sve2, sve2_fminp_zpzz)
TRANS_FEAT_NONSTREAMING(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz,
gen_helper_fmmla_s, a->rd, a->rn, a->rm, a->ra,
- 0, FPST_FPCR)
+ 0, FPST_A64)
TRANS_FEAT_NONSTREAMING(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz,
gen_helper_fmmla_d, a->rd, a->rn, a->rm, a->ra,
- 0, FPST_FPCR)
+ 0, FPST_A64)
static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = {
NULL, gen_helper_sve2_sqdmlal_zzzw_h,
@@ -7035,17 +7035,17 @@ TRANS_FEAT_NONSTREAMING(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz,
gen_gvec_rax1, a)
TRANS_FEAT(FCVTNT_sh, aa64_sve2, gen_gvec_fpst_arg_zpz,
- gen_helper_sve2_fcvtnt_sh, a, 0, FPST_FPCR)
+ gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64)
TRANS_FEAT(FCVTNT_ds, aa64_sve2, gen_gvec_fpst_arg_zpz,
- gen_helper_sve2_fcvtnt_ds, a, 0, FPST_FPCR)
+ gen_helper_sve2_fcvtnt_ds, a, 0, FPST_A64)
TRANS_FEAT(BFCVTNT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_bfcvtnt, a, 0, FPST_FPCR)
+ gen_helper_sve_bfcvtnt, a, 0, FPST_A64)
TRANS_FEAT(FCVTLT_hs, aa64_sve2, gen_gvec_fpst_arg_zpz,
- gen_helper_sve2_fcvtlt_hs, a, 0, FPST_FPCR)
+ gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64)
TRANS_FEAT(FCVTLT_sd, aa64_sve2, gen_gvec_fpst_arg_zpz,
- gen_helper_sve2_fcvtlt_sd, a, 0, FPST_FPCR)
+ gen_helper_sve2_fcvtlt_sd, a, 0, FPST_A64)
TRANS_FEAT(FCVTX_ds, aa64_sve2, do_frint_mode, a,
FPROUNDING_ODD, gen_helper_sve_fcvt_ds)
@@ -7057,7 +7057,7 @@ static gen_helper_gvec_3_ptr * const flogb_fns[] = {
gen_helper_flogb_s, gen_helper_flogb_d
};
TRANS_FEAT(FLOGB, aa64_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->esz],
- a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel)
{
@@ -7101,7 +7101,7 @@ TRANS_FEAT_NONSTREAMING(BFMMLA, aa64_sve_bf16, gen_gvec_env_arg_zzzz,
static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
{
return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal,
- a->rd, a->rn, a->rm, a->ra, sel, FPST_FPCR);
+ a->rd, a->rn, a->rm, a->ra, sel, FPST_A64);
}
TRANS_FEAT(BFMLALB_zzzw, aa64_sve_bf16, do_BFMLAL_zzzw, a, false)
@@ -7111,7 +7111,7 @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel)
{
return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal_idx,
a->rd, a->rn, a->rm, a->ra,
- (a->index << 1) | sel, FPST_FPCR);
+ (a->index << 1) | sel, FPST_A64);
}
TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false)
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 24/36] target/arm: Remove now-unused vfp.fp_status and FPST_FPCR
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (22 preceding siblings ...)
2025-01-28 20:13 ` [PULL 23/36] target/arm: Use FPST_A64 in A64 decoder Peter Maydell
@ 2025-01-28 20:13 ` Peter Maydell
2025-01-28 20:13 ` [PULL 25/36] target/arm: Define new fp_status_f16_a32 and fp_status_f16_a64 Peter Maydell
` (12 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:13 UTC (permalink / raw)
To: qemu-devel
Now we have moved all the uses of vfp.fp_status and FPST_FPCR
to either the A32 or A64 fields, we can remove these.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-13-peter.maydell@linaro.org
---
target/arm/cpu.h | 2 --
target/arm/tcg/translate.h | 6 ------
target/arm/cpu.c | 1 -
target/arm/vfp_helper.c | 8 +-------
4 files changed, 1 insertion(+), 16 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 337c5383748..7b967bbd1d2 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -633,7 +633,6 @@ typedef struct CPUArchState {
/* There are a number of distinct float control structures:
*
- * fp_status: is the "normal" fp status.
* fp_status_a32: is the "normal" fp status for AArch32 insns
* fp_status_a64: is the "normal" fp status for AArch64 insns
* fp_status_fp16: used for half-precision calculations
@@ -660,7 +659,6 @@ typedef struct CPUArchState {
* only thing which needs to read the exception flags being
* an explicit FPSCR read.
*/
- float_status fp_status;
float_status fp_status_a32;
float_status fp_status_a64;
float_status fp_status_f16;
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index c8414d94d5e..fca68b7c4c8 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -670,7 +670,6 @@ static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb)
* Enum for argument to fpstatus_ptr().
*/
typedef enum ARMFPStatusFlavour {
- FPST_FPCR,
FPST_A32,
FPST_A64,
FPST_FPCR_F16,
@@ -686,8 +685,6 @@ typedef enum ARMFPStatusFlavour {
* been set up to point to the requested field in the CPU state struct.
* The options are:
*
- * FPST_FPCR
- * for non-FP16 operations controlled by the FPCR
* FPST_A32
* for AArch32 non-FP16 operations controlled by the FPCR
* FPST_A64
@@ -705,9 +702,6 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour)
int offset;
switch (flavour) {
- case FPST_FPCR:
- offset = offsetof(CPUARMState, vfp.fp_status);
- break;
case FPST_A32:
offset = offsetof(CPUARMState, vfp.fp_status_a32);
break;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 8bdd535db95..a2b9bd3fb9d 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -572,7 +572,6 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type)
set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
set_default_nan_mode(1, &env->vfp.standard_fp_status);
set_default_nan_mode(1, &env->vfp.standard_fp_status_f16);
- arm_set_default_fp_behaviours(&env->vfp.fp_status);
arm_set_default_fp_behaviours(&env->vfp.fp_status_a32);
arm_set_default_fp_behaviours(&env->vfp.fp_status_a64);
arm_set_default_fp_behaviours(&env->vfp.standard_fp_status);
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 034f26e5daa..9fee6265f20 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -61,9 +61,8 @@ static inline uint32_t vfp_exceptbits_from_host(int host_bits)
static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
{
- uint32_t i;
+ uint32_t i = 0;
- i = get_float_exception_flags(&env->vfp.fp_status);
i |= get_float_exception_flags(&env->vfp.fp_status_a32);
i |= get_float_exception_flags(&env->vfp.fp_status_a64);
i |= get_float_exception_flags(&env->vfp.standard_fp_status);
@@ -82,7 +81,6 @@ static void vfp_clear_float_status_exc_flags(CPUARMState *env)
* values. The caller should have arranged for env->vfp.fpsr to
* be the architecturally up-to-date exception flag information first.
*/
- set_float_exception_flags(0, &env->vfp.fp_status);
set_float_exception_flags(0, &env->vfp.fp_status_a32);
set_float_exception_flags(0, &env->vfp.fp_status_a64);
set_float_exception_flags(0, &env->vfp.fp_status_f16);
@@ -112,7 +110,6 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
i = float_round_to_zero;
break;
}
- set_float_rounding_mode(i, &env->vfp.fp_status);
set_float_rounding_mode(i, &env->vfp.fp_status_a32);
set_float_rounding_mode(i, &env->vfp.fp_status_a64);
set_float_rounding_mode(i, &env->vfp.fp_status_f16);
@@ -126,8 +123,6 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
}
if (changed & FPCR_FZ) {
bool ftz_enabled = val & FPCR_FZ;
- set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
- set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a32);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_a32);
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a64);
@@ -135,7 +130,6 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
}
if (changed & FPCR_DN) {
bool dnan_enabled = val & FPCR_DN;
- set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 25/36] target/arm: Define new fp_status_f16_a32 and fp_status_f16_a64
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (23 preceding siblings ...)
2025-01-28 20:13 ` [PULL 24/36] target/arm: Remove now-unused vfp.fp_status and FPST_FPCR Peter Maydell
@ 2025-01-28 20:13 ` Peter Maydell
2025-01-28 20:13 ` [PULL 26/36] target/arm: Use fp_status_f16_a32 in AArch32-only helpers Peter Maydell
` (11 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:13 UTC (permalink / raw)
To: qemu-devel
As the first part of splitting the existing fp_status_f16
into separate float_status fields for AArch32 and AArch64
(so that we can make FEAT_AFP control bits apply only
for AArch64), define the two new fp_status_f16_a32 and
fp_status_f16_a64 fields, but don't use them yet.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-14-peter.maydell@linaro.org
---
target/arm/cpu.h | 4 ++++
target/arm/tcg/translate.h | 12 ++++++++++++
target/arm/cpu.c | 2 ++
target/arm/vfp_helper.c | 14 ++++++++++++++
4 files changed, 32 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 7b967bbd1d2..be409c5c76e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -636,6 +636,8 @@ typedef struct CPUArchState {
* fp_status_a32: is the "normal" fp status for AArch32 insns
* fp_status_a64: is the "normal" fp status for AArch64 insns
* fp_status_fp16: used for half-precision calculations
+ * fp_status_fp16_a32: used for AArch32 half-precision calculations
+ * fp_status_fp16_a64: used for AArch64 half-precision calculations
* standard_fp_status : the ARM "Standard FPSCR Value"
* standard_fp_status_fp16 : used for half-precision
* calculations with the ARM "Standard FPSCR Value"
@@ -662,6 +664,8 @@ typedef struct CPUArchState {
float_status fp_status_a32;
float_status fp_status_a64;
float_status fp_status_f16;
+ float_status fp_status_f16_a32;
+ float_status fp_status_f16_a64;
float_status standard_fp_status;
float_status standard_fp_status_f16;
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index fca68b7c4c8..d84c6d74aa4 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -673,6 +673,8 @@ typedef enum ARMFPStatusFlavour {
FPST_A32,
FPST_A64,
FPST_FPCR_F16,
+ FPST_A32_F16,
+ FPST_A64_F16,
FPST_STD,
FPST_STD_F16,
} ARMFPStatusFlavour;
@@ -691,6 +693,10 @@ typedef enum ARMFPStatusFlavour {
* for AArch64 non-FP16 operations controlled by the FPCR
* FPST_FPCR_F16
* for operations controlled by the FPCR where FPCR.FZ16 is to be used
+ * FPST_A32_F16
+ * for AArch32 operations controlled by the FPCR where FPCR.FZ16 is to be used
+ * FPST_A64_F16
+ * for AArch64 operations controlled by the FPCR where FPCR.FZ16 is to be used
* FPST_STD
* for A32/T32 Neon operations using the "standard FPSCR value"
* FPST_STD_F16
@@ -711,6 +717,12 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour)
case FPST_FPCR_F16:
offset = offsetof(CPUARMState, vfp.fp_status_f16);
break;
+ case FPST_A32_F16:
+ offset = offsetof(CPUARMState, vfp.fp_status_f16_a32);
+ break;
+ case FPST_A64_F16:
+ offset = offsetof(CPUARMState, vfp.fp_status_f16_a64);
+ break;
case FPST_STD:
offset = offsetof(CPUARMState, vfp.standard_fp_status);
break;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index a2b9bd3fb9d..ff8514edc6d 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -576,6 +576,8 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type)
arm_set_default_fp_behaviours(&env->vfp.fp_status_a64);
arm_set_default_fp_behaviours(&env->vfp.standard_fp_status);
arm_set_default_fp_behaviours(&env->vfp.fp_status_f16);
+ arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a32);
+ arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a64);
arm_set_default_fp_behaviours(&env->vfp.standard_fp_status_f16);
#ifndef CONFIG_USER_ONLY
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 9fee6265f20..45f9dfc8861 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -69,6 +69,10 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
/* FZ16 does not generate an input denormal exception. */
i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
& ~float_flag_input_denormal);
+ i |= (get_float_exception_flags(&env->vfp.fp_status_f16_a32)
+ & ~float_flag_input_denormal);
+ i |= (get_float_exception_flags(&env->vfp.fp_status_f16_a64)
+ & ~float_flag_input_denormal);
i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16)
& ~float_flag_input_denormal);
return vfp_exceptbits_from_host(i);
@@ -84,6 +88,8 @@ static void vfp_clear_float_status_exc_flags(CPUARMState *env)
set_float_exception_flags(0, &env->vfp.fp_status_a32);
set_float_exception_flags(0, &env->vfp.fp_status_a64);
set_float_exception_flags(0, &env->vfp.fp_status_f16);
+ set_float_exception_flags(0, &env->vfp.fp_status_f16_a32);
+ set_float_exception_flags(0, &env->vfp.fp_status_f16_a64);
set_float_exception_flags(0, &env->vfp.standard_fp_status);
set_float_exception_flags(0, &env->vfp.standard_fp_status_f16);
}
@@ -113,12 +119,18 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
set_float_rounding_mode(i, &env->vfp.fp_status_a32);
set_float_rounding_mode(i, &env->vfp.fp_status_a64);
set_float_rounding_mode(i, &env->vfp.fp_status_f16);
+ set_float_rounding_mode(i, &env->vfp.fp_status_f16_a32);
+ set_float_rounding_mode(i, &env->vfp.fp_status_f16_a64);
}
if (changed & FPCR_FZ16) {
bool ftz_enabled = val & FPCR_FZ16;
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
+ set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32);
+ set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a64);
set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
+ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32);
+ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a64);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
}
if (changed & FPCR_FZ) {
@@ -133,6 +145,8 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
+ set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a32);
+ set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a64);
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 26/36] target/arm: Use fp_status_f16_a32 in AArch32-only helpers
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (24 preceding siblings ...)
2025-01-28 20:13 ` [PULL 25/36] target/arm: Define new fp_status_f16_a32 and fp_status_f16_a64 Peter Maydell
@ 2025-01-28 20:13 ` Peter Maydell
2025-01-28 20:13 ` [PULL 27/36] target/arm: Use fp_status_f16_a64 in AArch64-only helpers Peter Maydell
` (10 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:13 UTC (permalink / raw)
To: qemu-devel
We directly use fp_status_f16 in a handful of helpers that
are AArch32-specific; switch to fp_status_f16_a32 for these.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-15-peter.maydell@linaro.org
---
target/arm/tcg/vec_helper.c | 4 ++--
target/arm/vfp_helper.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index 2ba1f7cb32e..1b1deda9422 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -2060,7 +2060,7 @@ void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm,
CPUARMState *env, uint32_t desc)
{
do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc,
- get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
+ get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a32));
}
void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
@@ -2122,7 +2122,7 @@ void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm,
CPUARMState *env, uint32_t desc)
{
do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc,
- get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
+ get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a32));
}
void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 45f9dfc8861..f3aa80bbfb6 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -380,7 +380,7 @@ void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
softfloat_to_vfp_compare(env, \
FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \
}
-DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status_f16)
+DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status_f16_a32)
DO_VFP_cmp(s, float32, float32, fp_status_a32)
DO_VFP_cmp(d, float64, float64, fp_status_a32)
#undef DO_VFP_cmp
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 27/36] target/arm: Use fp_status_f16_a64 in AArch64-only helpers
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (25 preceding siblings ...)
2025-01-28 20:13 ` [PULL 26/36] target/arm: Use fp_status_f16_a32 in AArch32-only helpers Peter Maydell
@ 2025-01-28 20:13 ` Peter Maydell
2025-01-28 20:13 ` [PULL 28/36] target/arm: Use FPST_A32_F16 in A32 decoder Peter Maydell
` (9 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:13 UTC (permalink / raw)
To: qemu-devel
We directly use fp_status_f16 in a handful of helpers that are
AArch64-specific; switch to fp_status_f16_a64 for these.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-16-peter.maydell@linaro.org
---
target/arm/tcg/sme_helper.c | 4 ++--
target/arm/tcg/vec_helper.c | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
index 2aad00d3ad9..727c085f374 100644
--- a/target/arm/tcg/sme_helper.c
+++ b/target/arm/tcg/sme_helper.c
@@ -1038,12 +1038,12 @@ void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn,
float_status fpst_odd, fpst_std, fpst_f16;
/*
- * Make copies of fp_status and fp_status_f16, because this operation
+ * Make copies of the fp status fields we use, because this operation
* does not update the cumulative fp exception status. It also
* produces default NaNs. We also need a second copy of fp_status with
* round-to-odd -- see above.
*/
- fpst_f16 = env->vfp.fp_status_f16;
+ fpst_f16 = env->vfp.fp_status_f16_a64;
fpst_std = env->vfp.fp_status_a64;
set_default_nan_mode(true, &fpst_std);
set_default_nan_mode(true, &fpst_f16);
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index 1b1deda9422..7330b373c38 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -2067,7 +2067,7 @@ void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
CPUARMState *env, uint32_t desc)
{
do_fmlal(vd, vn, vm, &env->vfp.fp_status_a64, desc,
- get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
+ get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64));
}
void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, void *vm, void *va,
@@ -2077,7 +2077,7 @@ void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, void *vm, void *va,
uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15;
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
float_status *status = &env->vfp.fp_status_a64;
- bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16);
+ bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64);
for (i = 0; i < oprsz; i += sizeof(float32)) {
float16 nn_16 = *(float16 *)(vn + H1_2(i + sel)) ^ negn;
@@ -2129,7 +2129,7 @@ void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
CPUARMState *env, uint32_t desc)
{
do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status_a64, desc,
- get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
+ get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64));
}
void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va,
@@ -2140,7 +2140,7 @@ void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va,
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
intptr_t idx = extract32(desc, SIMD_DATA_SHIFT + 2, 3) * sizeof(float16);
float_status *status = &env->vfp.fp_status_a64;
- bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16);
+ bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64);
for (i = 0; i < oprsz; i += 16) {
float16 mm_16 = *(float16 *)(vm + i + idx);
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 28/36] target/arm: Use FPST_A32_F16 in A32 decoder
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (26 preceding siblings ...)
2025-01-28 20:13 ` [PULL 27/36] target/arm: Use fp_status_f16_a64 in AArch64-only helpers Peter Maydell
@ 2025-01-28 20:13 ` Peter Maydell
2025-01-28 20:13 ` [PULL 29/36] target/arm: Use FPST_A64_F16 in A64 decoder Peter Maydell
` (8 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:13 UTC (permalink / raw)
To: qemu-devel
In the A32 decoder, use FPST_A32_F16 rather than FPST_FPCR_F16.
By doing an automated conversion of the whole file we avoid possibly
using more than one fpst value in a set_rmode/op/restore_rmode
sequence.
Patch created with
perl -p -i -e 's/FPST_FPCR_F16(?!_)/FPST_A32_F16/g' target/arm/tcg/translate-vfp.c
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-17-peter.maydell@linaro.org
---
target/arm/tcg/translate-vfp.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c
index c82f41234cd..8d9d1ab877a 100644
--- a/target/arm/tcg/translate-vfp.c
+++ b/target/arm/tcg/translate-vfp.c
@@ -460,7 +460,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
}
if (sz == 1) {
- fpst = fpstatus_ptr(FPST_FPCR_F16);
+ fpst = fpstatus_ptr(FPST_A32_F16);
} else {
fpst = fpstatus_ptr(FPST_A32);
}
@@ -527,7 +527,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
}
if (sz == 1) {
- fpst = fpstatus_ptr(FPST_FPCR_F16);
+ fpst = fpstatus_ptr(FPST_A32_F16);
} else {
fpst = fpstatus_ptr(FPST_A32);
}
@@ -1433,7 +1433,7 @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3OpSPFn *fn,
/*
* Do a half-precision operation. Functionally this is
* the same as do_vfp_3op_sp(), except:
- * - it uses the FPST_FPCR_F16
+ * - it uses the FPST_A32_F16
* - it doesn't need the VFP vector handling (fp16 is a
* v8 feature, and in v8 VFP vectors don't exist)
* - it does the aa32_fp16_arith feature test
@@ -1456,7 +1456,7 @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3OpSPFn *fn,
f0 = tcg_temp_new_i32();
f1 = tcg_temp_new_i32();
fd = tcg_temp_new_i32();
- fpst = fpstatus_ptr(FPST_FPCR_F16);
+ fpst = fpstatus_ptr(FPST_A32_F16);
vfp_load_reg16(f0, vn);
vfp_load_reg16(f1, vm);
@@ -2122,7 +2122,7 @@ static bool do_vfm_hp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
/* VFNMA, VFNMS */
gen_vfp_negh(vd, vd);
}
- fpst = fpstatus_ptr(FPST_FPCR_F16);
+ fpst = fpstatus_ptr(FPST_A32_F16);
gen_helper_vfp_muladdh(vd, vn, vm, vd, fpst);
vfp_store_reg32(vd, a->vd);
return true;
@@ -2424,7 +2424,7 @@ DO_VFP_2OP(VNEG, dp, gen_vfp_negd, aa32_fpdp_v2)
static void gen_VSQRT_hp(TCGv_i32 vd, TCGv_i32 vm)
{
- gen_helper_vfp_sqrth(vd, vm, fpstatus_ptr(FPST_FPCR_F16));
+ gen_helper_vfp_sqrth(vd, vm, fpstatus_ptr(FPST_A32_F16));
}
static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm)
@@ -2706,7 +2706,7 @@ static bool trans_VRINTR_hp(DisasContext *s, arg_VRINTR_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg16(tmp, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR_F16);
+ fpst = fpstatus_ptr(FPST_A32_F16);
gen_helper_rinth(tmp, tmp, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
@@ -2779,7 +2779,7 @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg16(tmp, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR_F16);
+ fpst = fpstatus_ptr(FPST_A32_F16);
tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rinth(tmp, tmp, fpst);
gen_restore_rmode(tcg_rmode, fpst);
@@ -2859,7 +2859,7 @@ static bool trans_VRINTX_hp(DisasContext *s, arg_VRINTX_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg16(tmp, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR_F16);
+ fpst = fpstatus_ptr(FPST_A32_F16);
gen_helper_rinth_exact(tmp, tmp, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
@@ -2983,7 +2983,7 @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a)
vm = tcg_temp_new_i32();
vfp_load_reg32(vm, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR_F16);
+ fpst = fpstatus_ptr(FPST_A32_F16);
if (a->s) {
/* i32 -> f16 */
gen_helper_vfp_sitoh(vm, vm, fpst);
@@ -3105,7 +3105,7 @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a)
vd = tcg_temp_new_i32();
vfp_load_reg32(vd, a->vd);
- fpst = fpstatus_ptr(FPST_FPCR_F16);
+ fpst = fpstatus_ptr(FPST_A32_F16);
shift = tcg_constant_i32(frac_bits);
/* Switch on op:U:sx bits */
@@ -3273,7 +3273,7 @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a)
return true;
}
- fpst = fpstatus_ptr(FPST_FPCR_F16);
+ fpst = fpstatus_ptr(FPST_A32_F16);
vm = tcg_temp_new_i32();
vfp_load_reg16(vm, a->vm);
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 29/36] target/arm: Use FPST_A64_F16 in A64 decoder
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (27 preceding siblings ...)
2025-01-28 20:13 ` [PULL 28/36] target/arm: Use FPST_A32_F16 in A32 decoder Peter Maydell
@ 2025-01-28 20:13 ` Peter Maydell
2025-01-28 20:13 ` [PULL 30/36] target/arm: Remove now-unused vfp.fp_status_f16 and FPST_FPCR_F16 Peter Maydell
` (7 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:13 UTC (permalink / raw)
To: qemu-devel
In the A32 decoder, use FPST_A64_F16 rather than FPST_FPCR_F16.
By doing an automated conversion of the whole file we avoid possibly
using more than one fpst value in a set_rmode/op/restore_rmode
sequence.
Patch created with
perl -p -i -e 's/FPST_FPCR_F16(?!_)/FPST_A64_F16/g' target/arm/tcg/translate-{a64,sve,sme}.c
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-18-peter.maydell@linaro.org
---
target/arm/tcg/translate-a64.c | 32 ++++++++---------
target/arm/tcg/translate-sve.c | 66 +++++++++++++++++-----------------
2 files changed, 49 insertions(+), 49 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index d9c00713675..2b8b253479a 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -726,7 +726,7 @@ static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn,
int rm, bool is_fp16, int data,
gen_helper_gvec_3_ptr *fn)
{
- TCGv_ptr fpst = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_A64);
+ TCGv_ptr fpst = fpstatus_ptr(is_fp16 ? FPST_A64_F16 : FPST_A64);
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm), fpst,
@@ -768,7 +768,7 @@ static void gen_gvec_op4_fpst(DisasContext *s, bool is_q, int rd, int rn,
int rm, int ra, bool is_fp16, int data,
gen_helper_gvec_4_ptr *fn)
{
- TCGv_ptr fpst = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_A64);
+ TCGv_ptr fpst = fpstatus_ptr(is_fp16 ? FPST_A64_F16 : FPST_A64);
tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm),
@@ -5062,7 +5062,7 @@ static bool do_fp3_scalar(DisasContext *s, arg_rrr_e *a, const FPScalar *f)
if (fp_access_check(s)) {
TCGv_i32 t0 = read_fp_hreg(s, a->rn);
TCGv_i32 t1 = read_fp_hreg(s, a->rm);
- f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_FPCR_F16));
+ f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_A64_F16));
write_fp_sreg(s, a->rd, t0);
}
break;
@@ -5270,9 +5270,9 @@ static bool do_fcmp0_s(DisasContext *s, arg_rr_e *a,
TCGv_i32 t0 = read_fp_hreg(s, a->rn);
TCGv_i32 t1 = tcg_constant_i32(0);
if (swap) {
- f->gen_h(t0, t1, t0, fpstatus_ptr(FPST_FPCR_F16));
+ f->gen_h(t0, t1, t0, fpstatus_ptr(FPST_A64_F16));
} else {
- f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_FPCR_F16));
+ f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_A64_F16));
}
write_fp_sreg(s, a->rd, t0);
}
@@ -6230,7 +6230,7 @@ static bool do_fp3_scalar_idx(DisasContext *s, arg_rrx_e *a, const FPScalar *f)
TCGv_i32 t1 = tcg_temp_new_i32();
read_vec_element_i32(s, t1, a->rm, a->idx, MO_16);
- f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_FPCR_F16));
+ f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_A64_F16));
write_fp_sreg(s, a->rd, t0);
}
break;
@@ -6288,7 +6288,7 @@ static bool do_fmla_scalar_idx(DisasContext *s, arg_rrx_e *a, bool neg)
gen_vfp_negh(t1, t1);
}
gen_helper_advsimd_muladdh(t0, t1, t2, t0,
- fpstatus_ptr(FPST_FPCR_F16));
+ fpstatus_ptr(FPST_A64_F16));
write_fp_sreg(s, a->rd, t0);
}
break;
@@ -6626,7 +6626,7 @@ static bool do_fp3_scalar_pair(DisasContext *s, arg_rr_e *a, const FPScalar *f)
read_vec_element_i32(s, t0, a->rn, 0, MO_16);
read_vec_element_i32(s, t1, a->rn, 1, MO_16);
- f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_FPCR_F16));
+ f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_A64_F16));
write_fp_sreg(s, a->rd, t0);
}
break;
@@ -6801,7 +6801,7 @@ static bool do_fmadd(DisasContext *s, arg_rrrr_e *a, bool neg_a, bool neg_n)
if (neg_n) {
gen_vfp_negh(tn, tn);
}
- fpst = fpstatus_ptr(FPST_FPCR_F16);
+ fpst = fpstatus_ptr(FPST_A64_F16);
gen_helper_advsimd_muladdh(ta, tn, tm, ta, fpst);
write_fp_sreg(s, a->rd, ta);
}
@@ -6895,7 +6895,7 @@ static bool do_fp_reduction(DisasContext *s, arg_qrr_e *a,
if (fp_access_check(s)) {
MemOp esz = a->esz;
int elts = (a->q ? 16 : 8) >> esz;
- TCGv_ptr fpst = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
+ TCGv_ptr fpst = fpstatus_ptr(esz == MO_16 ? FPST_A64_F16 : FPST_A64);
TCGv_i32 res = do_reduction_op(s, a->rn, esz, 0, elts, fpst, fn);
write_fp_sreg(s, a->rd, res);
}
@@ -6939,7 +6939,7 @@ static void handle_fp_compare(DisasContext *s, int size,
bool cmp_with_zero, bool signal_all_nans)
{
TCGv_i64 tcg_flags = tcg_temp_new_i64();
- TCGv_ptr fpst = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_A64);
+ TCGv_ptr fpst = fpstatus_ptr(size == MO_16 ? FPST_A64_F16 : FPST_A64);
if (size == MO_64) {
TCGv_i64 tcg_vn, tcg_vm;
@@ -8407,7 +8407,7 @@ static bool do_fp1_scalar(DisasContext *s, arg_rr_e *a,
return check == 0;
}
- fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
+ fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
if (rmode >= 0) {
tcg_rmode = gen_set_rmode(rmode, fpst);
}
@@ -8598,7 +8598,7 @@ static bool do_cvtf_scalar(DisasContext *s, MemOp esz, int rd, int shift,
TCGv_i32 tcg_shift, tcg_single;
TCGv_i64 tcg_double;
- tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
+ tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_A64_F16 : FPST_A64);
tcg_shift = tcg_constant_i32(shift);
switch (esz) {
@@ -8693,7 +8693,7 @@ static void do_fcvt_scalar(DisasContext *s, MemOp out, MemOp esz,
TCGv_ptr tcg_fpstatus;
TCGv_i32 tcg_shift, tcg_rmode, tcg_single;
- tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
+ tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_A64_F16 : FPST_A64);
tcg_shift = tcg_constant_i32(shift);
tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
@@ -9312,7 +9312,7 @@ static bool do_fp1_vector(DisasContext *s, arg_qrr_e *a,
return check == 0;
}
- fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
+ fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
if (rmode >= 0) {
tcg_rmode = gen_set_rmode(rmode, fpst);
}
@@ -9372,7 +9372,7 @@ static bool do_gvec_op2_fpst(DisasContext *s, MemOp esz, bool is_q,
return check == 0;
}
- fpst = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
+ fpst = fpstatus_ptr(esz == MO_16 ? FPST_A64_F16 : FPST_A64);
tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn), fpst,
is_q ? 16 : 8, vec_full_reg_size(s),
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index d32a67331df..a7dbea5acd0 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -141,7 +141,7 @@ static bool gen_gvec_fpst_arg_zz(DisasContext *s, gen_helper_gvec_2_ptr *fn,
arg_rr_esz *a, int data)
{
return gen_gvec_fpst_zz(s, fn, a->rd, a->rn, data,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
+ a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
}
/* Invoke an out-of-line helper on 3 Zregs. */
@@ -191,7 +191,7 @@ static bool gen_gvec_fpst_arg_zzz(DisasContext *s, gen_helper_gvec_3_ptr *fn,
arg_rrr_esz *a, int data)
{
return gen_gvec_fpst_zzz(s, fn, a->rd, a->rn, a->rm, data,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
+ a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
}
/* Invoke an out-of-line helper on 4 Zregs. */
@@ -397,7 +397,7 @@ static bool gen_gvec_fpst_arg_zpzz(DisasContext *s, gen_helper_gvec_4_ptr *fn,
arg_rprr_esz *a)
{
return gen_gvec_fpst_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
+ a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
}
/* Invoke a vector expander on two Zregs and an immediate. */
@@ -3517,7 +3517,7 @@ static bool do_FMLA_zzxz(DisasContext *s, arg_rrxr_esz *a, bool sub)
};
return gen_gvec_fpst_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra,
(a->index << 1) | sub,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
+ a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
}
TRANS_FEAT(FMLA_zzxz, aa64_sve, do_FMLA_zzxz, a, false)
@@ -3533,7 +3533,7 @@ static gen_helper_gvec_3_ptr * const fmul_idx_fns[4] = {
};
TRANS_FEAT(FMUL_zzx, aa64_sve, gen_gvec_fpst_zzz,
fmul_idx_fns[a->esz], a->rd, a->rn, a->rm, a->index,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
+ a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
/*
*** SVE Floating Point Fast Reduction Group
@@ -3566,7 +3566,7 @@ static bool do_reduce(DisasContext *s, arg_rpr_esz *a,
tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg));
- status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
+ status = fpstatus_ptr(a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
fn(temp, t_zn, t_pg, status, t_desc);
@@ -3618,7 +3618,7 @@ static bool do_ppz_fp(DisasContext *s, arg_rpr_esz *a,
if (sve_access_check(s)) {
unsigned vsz = vec_full_reg_size(s);
TCGv_ptr status =
- fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
+ fpstatus_ptr(a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
tcg_gen_gvec_3_ptr(pred_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
@@ -3654,7 +3654,7 @@ static gen_helper_gvec_3_ptr * const ftmad_fns[4] = {
};
TRANS_FEAT_NONSTREAMING(FTMAD, aa64_sve, gen_gvec_fpst_zzz,
ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
+ a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
/*
*** SVE Floating Point Accumulating Reduction Group
@@ -3687,7 +3687,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_rm, tcg_env, vec_full_reg_offset(s, a->rm));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg));
- t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
+ t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
t_desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc);
@@ -3762,7 +3762,7 @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16,
tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, zn));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
- status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_A64);
+ status = fpstatus_ptr(is_fp16 ? FPST_A64_F16 : FPST_A64);
desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
fn(t_zd, t_zn, t_pg, scalar, status, desc);
}
@@ -3814,7 +3814,7 @@ static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *a,
}
if (sve_access_check(s)) {
unsigned vsz = vec_full_reg_size(s);
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
+ TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
tcg_gen_gvec_4_ptr(pred_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm),
@@ -3847,7 +3847,7 @@ static gen_helper_gvec_4_ptr * const fcadd_fns[] = {
};
TRANS_FEAT(FCADD, aa64_sve, gen_gvec_fpst_zzzp, fcadd_fns[a->esz],
a->rd, a->rn, a->rm, a->pg, a->rot,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
+ a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
#define DO_FMLA(NAME, name) \
static gen_helper_gvec_5_ptr * const name##_fns[4] = { \
@@ -3856,7 +3856,7 @@ TRANS_FEAT(FCADD, aa64_sve, gen_gvec_fpst_zzzp, fcadd_fns[a->esz],
}; \
TRANS_FEAT(NAME, aa64_sve, gen_gvec_fpst_zzzzp, name##_fns[a->esz], \
a->rd, a->rn, a->rm, a->ra, a->pg, 0, \
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
+ a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
DO_FMLA(FMLA_zpzzz, fmla_zpzzz)
DO_FMLA(FMLS_zpzzz, fmls_zpzzz)
@@ -3871,14 +3871,14 @@ static gen_helper_gvec_5_ptr * const fcmla_fns[4] = {
};
TRANS_FEAT(FCMLA_zpzzz, aa64_sve, gen_gvec_fpst_zzzzp, fcmla_fns[a->esz],
a->rd, a->rn, a->rm, a->ra, a->pg, a->rot,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
+ a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
static gen_helper_gvec_4_ptr * const fcmla_idx_fns[4] = {
NULL, gen_helper_gvec_fcmlah_idx, gen_helper_gvec_fcmlas_idx, NULL
};
TRANS_FEAT(FCMLA_zzxz, aa64_sve, gen_gvec_fpst_zzzz, fcmla_idx_fns[a->esz],
a->rd, a->rn, a->rm, a->ra, a->index * 4 + a->rot,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
+ a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
/*
*** SVE Floating Point Unary Operations Predicated Group
@@ -3902,17 +3902,17 @@ TRANS_FEAT(FCVT_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_fcvt_sd, a, 0, FPST_A64)
TRANS_FEAT(FCVTZS_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzs_hh, a, 0, FPST_FPCR_F16)
+ gen_helper_sve_fcvtzs_hh, a, 0, FPST_A64_F16)
TRANS_FEAT(FCVTZU_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzu_hh, a, 0, FPST_FPCR_F16)
+ gen_helper_sve_fcvtzu_hh, a, 0, FPST_A64_F16)
TRANS_FEAT(FCVTZS_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzs_hs, a, 0, FPST_FPCR_F16)
+ gen_helper_sve_fcvtzs_hs, a, 0, FPST_A64_F16)
TRANS_FEAT(FCVTZU_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzu_hs, a, 0, FPST_FPCR_F16)
+ gen_helper_sve_fcvtzu_hs, a, 0, FPST_A64_F16)
TRANS_FEAT(FCVTZS_hd, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzs_hd, a, 0, FPST_FPCR_F16)
+ gen_helper_sve_fcvtzs_hd, a, 0, FPST_A64_F16)
TRANS_FEAT(FCVTZU_hd, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzu_hd, a, 0, FPST_FPCR_F16)
+ gen_helper_sve_fcvtzu_hd, a, 0, FPST_A64_F16)
TRANS_FEAT(FCVTZS_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_fcvtzs_ss, a, 0, FPST_A64)
@@ -3939,7 +3939,7 @@ static gen_helper_gvec_3_ptr * const frint_fns[] = {
gen_helper_sve_frint_d
};
TRANS_FEAT(FRINTI, aa64_sve, gen_gvec_fpst_arg_zpz, frint_fns[a->esz],
- a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
+ a, 0, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
static gen_helper_gvec_3_ptr * const frintx_fns[] = {
NULL,
@@ -3948,7 +3948,7 @@ static gen_helper_gvec_3_ptr * const frintx_fns[] = {
gen_helper_sve_frintx_d
};
TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz],
- a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
+ a, 0, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
ARMFPRounding mode, gen_helper_gvec_3_ptr *fn)
@@ -3965,7 +3965,7 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
}
vsz = vec_full_reg_size(s);
- status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64);
+ status = fpstatus_ptr(a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
tmode = gen_set_rmode(mode, status);
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
@@ -3993,21 +3993,21 @@ static gen_helper_gvec_3_ptr * const frecpx_fns[] = {
gen_helper_sve_frecpx_s, gen_helper_sve_frecpx_d,
};
TRANS_FEAT(FRECPX, aa64_sve, gen_gvec_fpst_arg_zpz, frecpx_fns[a->esz],
- a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
+ a, 0, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
static gen_helper_gvec_3_ptr * const fsqrt_fns[] = {
NULL, gen_helper_sve_fsqrt_h,
gen_helper_sve_fsqrt_s, gen_helper_sve_fsqrt_d,
};
TRANS_FEAT(FSQRT, aa64_sve, gen_gvec_fpst_arg_zpz, fsqrt_fns[a->esz],
- a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
+ a, 0, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
TRANS_FEAT(SCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_scvt_hh, a, 0, FPST_FPCR_F16)
+ gen_helper_sve_scvt_hh, a, 0, FPST_A64_F16)
TRANS_FEAT(SCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_scvt_sh, a, 0, FPST_FPCR_F16)
+ gen_helper_sve_scvt_sh, a, 0, FPST_A64_F16)
TRANS_FEAT(SCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_scvt_dh, a, 0, FPST_FPCR_F16)
+ gen_helper_sve_scvt_dh, a, 0, FPST_A64_F16)
TRANS_FEAT(SCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_scvt_ss, a, 0, FPST_A64)
@@ -4020,11 +4020,11 @@ TRANS_FEAT(SCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_scvt_dd, a, 0, FPST_A64)
TRANS_FEAT(UCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_ucvt_hh, a, 0, FPST_FPCR_F16)
+ gen_helper_sve_ucvt_hh, a, 0, FPST_A64_F16)
TRANS_FEAT(UCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_ucvt_sh, a, 0, FPST_FPCR_F16)
+ gen_helper_sve_ucvt_sh, a, 0, FPST_A64_F16)
TRANS_FEAT(UCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_ucvt_dh, a, 0, FPST_FPCR_F16)
+ gen_helper_sve_ucvt_dh, a, 0, FPST_A64_F16)
TRANS_FEAT(UCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_ucvt_ss, a, 0, FPST_A64)
@@ -7057,7 +7057,7 @@ static gen_helper_gvec_3_ptr * const flogb_fns[] = {
gen_helper_flogb_s, gen_helper_flogb_d
};
TRANS_FEAT(FLOGB, aa64_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->esz],
- a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_A64)
+ a, 0, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 30/36] target/arm: Remove now-unused vfp.fp_status_f16 and FPST_FPCR_F16
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (28 preceding siblings ...)
2025-01-28 20:13 ` [PULL 29/36] target/arm: Use FPST_A64_F16 in A64 decoder Peter Maydell
@ 2025-01-28 20:13 ` Peter Maydell
2025-01-28 20:13 ` [PULL 31/36] fpu: Rename float_flag_input_denormal to float_flag_input_denormal_flushed Peter Maydell
` (6 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:13 UTC (permalink / raw)
To: qemu-devel
Now we have moved all the uses of vfp.fp_status_f16 and FPST_FPCR_F16
to the new A32 or A64 fields, we can remove these.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-19-peter.maydell@linaro.org
---
target/arm/cpu.h | 2 --
target/arm/tcg/translate.h | 6 ------
target/arm/cpu.c | 1 -
target/arm/vfp_helper.c | 7 -------
4 files changed, 16 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index be409c5c76e..2213c277348 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -635,7 +635,6 @@ typedef struct CPUArchState {
*
* fp_status_a32: is the "normal" fp status for AArch32 insns
* fp_status_a64: is the "normal" fp status for AArch64 insns
- * fp_status_fp16: used for half-precision calculations
* fp_status_fp16_a32: used for AArch32 half-precision calculations
* fp_status_fp16_a64: used for AArch64 half-precision calculations
* standard_fp_status : the ARM "Standard FPSCR Value"
@@ -663,7 +662,6 @@ typedef struct CPUArchState {
*/
float_status fp_status_a32;
float_status fp_status_a64;
- float_status fp_status_f16;
float_status fp_status_f16_a32;
float_status fp_status_f16_a64;
float_status standard_fp_status;
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index d84c6d74aa4..084ee63d990 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -672,7 +672,6 @@ static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb)
typedef enum ARMFPStatusFlavour {
FPST_A32,
FPST_A64,
- FPST_FPCR_F16,
FPST_A32_F16,
FPST_A64_F16,
FPST_STD,
@@ -691,8 +690,6 @@ typedef enum ARMFPStatusFlavour {
* for AArch32 non-FP16 operations controlled by the FPCR
* FPST_A64
* for AArch64 non-FP16 operations controlled by the FPCR
- * FPST_FPCR_F16
- * for operations controlled by the FPCR where FPCR.FZ16 is to be used
* FPST_A32_F16
* for AArch32 operations controlled by the FPCR where FPCR.FZ16 is to be used
* FPST_A64_F16
@@ -714,9 +711,6 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour)
case FPST_A64:
offset = offsetof(CPUARMState, vfp.fp_status_a64);
break;
- case FPST_FPCR_F16:
- offset = offsetof(CPUARMState, vfp.fp_status_f16);
- break;
case FPST_A32_F16:
offset = offsetof(CPUARMState, vfp.fp_status_f16_a32);
break;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index ff8514edc6d..7a83b9ee34f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -575,7 +575,6 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type)
arm_set_default_fp_behaviours(&env->vfp.fp_status_a32);
arm_set_default_fp_behaviours(&env->vfp.fp_status_a64);
arm_set_default_fp_behaviours(&env->vfp.standard_fp_status);
- arm_set_default_fp_behaviours(&env->vfp.fp_status_f16);
arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a32);
arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a64);
arm_set_default_fp_behaviours(&env->vfp.standard_fp_status_f16);
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index f3aa80bbfb6..3ed69d73698 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -67,8 +67,6 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
i |= get_float_exception_flags(&env->vfp.fp_status_a64);
i |= get_float_exception_flags(&env->vfp.standard_fp_status);
/* FZ16 does not generate an input denormal exception. */
- i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
- & ~float_flag_input_denormal);
i |= (get_float_exception_flags(&env->vfp.fp_status_f16_a32)
& ~float_flag_input_denormal);
i |= (get_float_exception_flags(&env->vfp.fp_status_f16_a64)
@@ -87,7 +85,6 @@ static void vfp_clear_float_status_exc_flags(CPUARMState *env)
*/
set_float_exception_flags(0, &env->vfp.fp_status_a32);
set_float_exception_flags(0, &env->vfp.fp_status_a64);
- set_float_exception_flags(0, &env->vfp.fp_status_f16);
set_float_exception_flags(0, &env->vfp.fp_status_f16_a32);
set_float_exception_flags(0, &env->vfp.fp_status_f16_a64);
set_float_exception_flags(0, &env->vfp.standard_fp_status);
@@ -118,17 +115,14 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
}
set_float_rounding_mode(i, &env->vfp.fp_status_a32);
set_float_rounding_mode(i, &env->vfp.fp_status_a64);
- set_float_rounding_mode(i, &env->vfp.fp_status_f16);
set_float_rounding_mode(i, &env->vfp.fp_status_f16_a32);
set_float_rounding_mode(i, &env->vfp.fp_status_f16_a64);
}
if (changed & FPCR_FZ16) {
bool ftz_enabled = val & FPCR_FZ16;
- set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32);
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a64);
set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
- set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a64);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
@@ -144,7 +138,6 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
bool dnan_enabled = val & FPCR_DN;
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64);
- set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a32);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a64);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 31/36] fpu: Rename float_flag_input_denormal to float_flag_input_denormal_flushed
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (29 preceding siblings ...)
2025-01-28 20:13 ` [PULL 30/36] target/arm: Remove now-unused vfp.fp_status_f16 and FPST_FPCR_F16 Peter Maydell
@ 2025-01-28 20:13 ` Peter Maydell
2025-01-28 20:13 ` [PULL 32/36] fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed Peter Maydell
` (5 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:13 UTC (permalink / raw)
To: qemu-devel
Our float_flag_input_denormal exception flag is set when the fpu code
flushes an input denormal to zero. This is what many guest
architectures (eg classic Arm behaviour) require, but it is not the
only donarmal-related reason we might want to set an exception flag.
The x86 behaviour (which we do not currently model correctly) wants
to see an exception flag when a denormal input is *not* flushed to
zero and is actually used in an arithmetic operation. Arm's FEAT_AFP
also wants these semantics.
Rename float_flag_input_denormal to float_flag_input_denormal_flushed
to make it clearer when it is set and to allow us to add a new
float_flag_input_denormal_used next to it for the x86/FEAT_AFP
semantics.
Commit created with
for f in `git grep -l float_flag_input_denormal`; do sed -i -e 's/float_flag_input_denormal/float_flag_input_denormal_flushed/' $f; done
and manual editing of softfloat-types.h and softfloat.c to clean
up the indentation afterwards and to fix a comment which wasn't
using the full name of the flag.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-20-peter.maydell@linaro.org
---
include/fpu/softfloat-types.h | 5 +++--
fpu/softfloat.c | 4 ++--
target/arm/tcg/sve_helper.c | 6 +++---
target/arm/vfp_helper.c | 10 +++++-----
target/i386/tcg/fpu_helper.c | 6 +++---
target/mips/tcg/msa_helper.c | 2 +-
target/rx/op_helper.c | 2 +-
fpu/softfloat-parts.c.inc | 2 +-
8 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 9d37cdfaa8e..24cd290a1df 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -154,7 +154,8 @@ enum {
float_flag_overflow = 0x0004,
float_flag_underflow = 0x0008,
float_flag_inexact = 0x0010,
- float_flag_input_denormal = 0x0020,
+ /* We flushed an input denormal to 0 (because of flush_inputs_to_zero) */
+ float_flag_input_denormal_flushed = 0x0020,
float_flag_output_denormal = 0x0040,
float_flag_invalid_isi = 0x0080, /* inf - inf */
float_flag_invalid_imz = 0x0100, /* inf * 0 */
@@ -302,7 +303,7 @@ typedef struct float_status {
bool tininess_before_rounding;
/* should denormalised results go to zero and set the inexact flag? */
bool flush_to_zero;
- /* should denormalised inputs go to zero and set the input_denormal flag? */
+ /* should denormalised inputs go to zero and set input_denormal_flushed? */
bool flush_inputs_to_zero;
bool default_nan_mode;
/*
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 8d75d668172..648050be6fb 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -132,7 +132,7 @@ this code that are retained.
if (unlikely(soft_t ## _is_denormal(*a))) { \
*a = soft_t ## _set_sign(soft_t ## _zero, \
soft_t ## _is_neg(*a)); \
- float_raise(float_flag_input_denormal, s); \
+ float_raise(float_flag_input_denormal_flushed, s); \
} \
}
@@ -4848,7 +4848,7 @@ float128 float128_silence_nan(float128 a, float_status *status)
static bool parts_squash_denormal(FloatParts64 p, float_status *status)
{
if (p.exp == 0 && p.frac != 0) {
- float_raise(float_flag_input_denormal, status);
+ float_raise(float_flag_input_denormal_flushed, status);
return true;
}
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
index d0865dece35..9837c5bc7ac 100644
--- a/target/arm/tcg/sve_helper.c
+++ b/target/arm/tcg/sve_helper.c
@@ -4658,7 +4658,7 @@ static int16_t do_float16_logb_as_int(float16 a, float_status *s)
return -15 - clz32(frac);
}
/* flush to zero */
- float_raise(float_flag_input_denormal, s);
+ float_raise(float_flag_input_denormal_flushed, s);
}
} else if (unlikely(exp == 0x1f)) {
if (frac == 0) {
@@ -4686,7 +4686,7 @@ static int32_t do_float32_logb_as_int(float32 a, float_status *s)
return -127 - clz32(frac);
}
/* flush to zero */
- float_raise(float_flag_input_denormal, s);
+ float_raise(float_flag_input_denormal_flushed, s);
}
} else if (unlikely(exp == 0xff)) {
if (frac == 0) {
@@ -4714,7 +4714,7 @@ static int64_t do_float64_logb_as_int(float64 a, float_status *s)
return -1023 - clz64(frac);
}
/* flush to zero */
- float_raise(float_flag_input_denormal, s);
+ float_raise(float_flag_input_denormal_flushed, s);
}
} else if (unlikely(exp == 0x7ff)) {
if (frac == 0) {
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 3ed69d73698..444702a4600 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -53,7 +53,7 @@ static inline uint32_t vfp_exceptbits_from_host(int host_bits)
if (host_bits & float_flag_inexact) {
target_bits |= FPSR_IXC;
}
- if (host_bits & float_flag_input_denormal) {
+ if (host_bits & float_flag_input_denormal_flushed) {
target_bits |= FPSR_IDC;
}
return target_bits;
@@ -68,11 +68,11 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
i |= get_float_exception_flags(&env->vfp.standard_fp_status);
/* FZ16 does not generate an input denormal exception. */
i |= (get_float_exception_flags(&env->vfp.fp_status_f16_a32)
- & ~float_flag_input_denormal);
+ & ~float_flag_input_denormal_flushed);
i |= (get_float_exception_flags(&env->vfp.fp_status_f16_a64)
- & ~float_flag_input_denormal);
+ & ~float_flag_input_denormal_flushed);
i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16)
- & ~float_flag_input_denormal);
+ & ~float_flag_input_denormal_flushed);
return vfp_exceptbits_from_host(i);
}
@@ -1133,7 +1133,7 @@ uint64_t HELPER(fjcvtzs)(float64 value, float_status *status)
/* Normal inexact, denormal with flush-to-zero, or overflow or NaN */
inexact = e_new & (float_flag_inexact |
- float_flag_input_denormal |
+ float_flag_input_denormal_flushed |
float_flag_invalid);
/* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index d0a1e2f3c8a..9c33ac7898b 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -204,7 +204,7 @@ static void merge_exception_flags(CPUX86State *env, uint8_t old_flags)
(new_flags & float_flag_overflow ? FPUS_OE : 0) |
(new_flags & float_flag_underflow ? FPUS_UE : 0) |
(new_flags & float_flag_inexact ? FPUS_PE : 0) |
- (new_flags & float_flag_input_denormal ? FPUS_DE : 0)));
+ (new_flags & float_flag_input_denormal_flushed ? FPUS_DE : 0)));
}
static inline floatx80 helper_fdiv(CPUX86State *env, floatx80 a, floatx80 b)
@@ -1829,7 +1829,7 @@ void helper_fxtract(CPUX86State *env)
int shift = clz64(temp.l.lower);
temp.l.lower <<= shift;
expdif = 1 - EXPBIAS - shift;
- float_raise(float_flag_input_denormal, &env->fp_status);
+ float_raise(float_flag_input_denormal_flushed, &env->fp_status);
} else {
expdif = EXPD(temp) - EXPBIAS;
}
@@ -3258,7 +3258,7 @@ void update_mxcsr_from_sse_status(CPUX86State *env)
uint8_t flags = get_float_exception_flags(&env->sse_status);
/*
* The MXCSR denormal flag has opposite semantics to
- * float_flag_input_denormal (the softfloat code sets that flag
+ * float_flag_input_denormal_flushed (the softfloat code sets that flag
* only when flushing input denormals to zero, but SSE sets it
* only when not flushing them to zero), so is not converted
* here.
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index 1d40383ca4f..aeab6a1d8b3 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -6231,7 +6231,7 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
/* Set Inexact (I) when flushing inputs to zero */
- if ((ieee_exception_flags & float_flag_input_denormal) &&
+ if ((ieee_exception_flags & float_flag_input_denormal_flushed) &&
(env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
if (action & CLEAR_IS_INEXACT) {
mips_exception_flags &= ~FP_INEXACT;
diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
index 691a12b2be1..59dd1ae6128 100644
--- a/target/rx/op_helper.c
+++ b/target/rx/op_helper.c
@@ -99,7 +99,7 @@ static void update_fpsw(CPURXState *env, float32 ret, uintptr_t retaddr)
if (xcpt & float_flag_inexact) {
SET_FPSW(X);
}
- if ((xcpt & (float_flag_input_denormal
+ if ((xcpt & (float_flag_input_denormal_flushed
| float_flag_output_denormal))
&& !FIELD_EX32(env->fpsw, FPSW, DN)) {
env->fpsw = FIELD_DP32(env->fpsw, FPSW, CE, 1);
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index ebde42992fc..b3d693eed0e 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -198,7 +198,7 @@ static void partsN(canonicalize)(FloatPartsN *p, float_status *status,
if (likely(frac_eqz(p))) {
p->cls = float_class_zero;
} else if (status->flush_inputs_to_zero) {
- float_raise(float_flag_input_denormal, status);
+ float_raise(float_flag_input_denormal_flushed, status);
p->cls = float_class_zero;
frac_clear(p);
} else {
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 32/36] fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (30 preceding siblings ...)
2025-01-28 20:13 ` [PULL 31/36] fpu: Rename float_flag_input_denormal to float_flag_input_denormal_flushed Peter Maydell
@ 2025-01-28 20:13 ` Peter Maydell
2025-01-28 20:13 ` [PULL 33/36] fpu: Fix a comment in softfloat-types.h Peter Maydell
` (4 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:13 UTC (permalink / raw)
To: qemu-devel
Our float_flag_output_denormal exception flag is set when
the fpu code flushes an output denormal to zero. Rename
it to float_flag_output_denormal_flushed:
* this keeps it parallel with the flag for flushing
input denormals, which we just renamed
* it makes it clearer that it doesn't mean "set when
the output is a denormal"
Commit created with
for f in `git grep -l float_flag_output_denormal`; do sed -i -e 's/float_flag_output_denormal/float_flag_output_denormal_flushed/' $f; done
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-21-peter.maydell@linaro.org
---
include/fpu/softfloat-types.h | 3 ++-
fpu/softfloat.c | 2 +-
target/arm/vfp_helper.c | 2 +-
target/i386/tcg/fpu_helper.c | 2 +-
target/m68k/fpu_helper.c | 2 +-
target/mips/tcg/msa_helper.c | 2 +-
target/rx/op_helper.c | 2 +-
target/tricore/fpu_helper.c | 6 +++---
fpu/softfloat-parts.c.inc | 2 +-
9 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 24cd290a1df..c35fdaa5ae1 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -156,7 +156,8 @@ enum {
float_flag_inexact = 0x0010,
/* We flushed an input denormal to 0 (because of flush_inputs_to_zero) */
float_flag_input_denormal_flushed = 0x0020,
- float_flag_output_denormal = 0x0040,
+ /* We flushed an output denormal to 0 (because of flush_to_zero) */
+ float_flag_output_denormal_flushed = 0x0040,
float_flag_invalid_isi = 0x0080, /* inf - inf */
float_flag_invalid_imz = 0x0100, /* inf * 0 */
float_flag_invalid_idi = 0x0200, /* inf / inf */
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 648050be6fb..26f3a8dc87e 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -5017,7 +5017,7 @@ floatx80 roundAndPackFloatx80(FloatX80RoundPrec roundingPrecision, bool zSign,
}
if ( zExp <= 0 ) {
if (status->flush_to_zero) {
- float_raise(float_flag_output_denormal, status);
+ float_raise(float_flag_output_denormal_flushed, status);
return packFloatx80(zSign, 0, 0);
}
isTiny = status->tininess_before_rounding
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 444702a4600..3c8f3e65887 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -47,7 +47,7 @@ static inline uint32_t vfp_exceptbits_from_host(int host_bits)
if (host_bits & float_flag_overflow) {
target_bits |= FPSR_OFC;
}
- if (host_bits & (float_flag_underflow | float_flag_output_denormal)) {
+ if (host_bits & (float_flag_underflow | float_flag_output_denormal_flushed)) {
target_bits |= FPSR_UFC;
}
if (host_bits & float_flag_inexact) {
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 9c33ac7898b..3d764bc138d 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -3268,7 +3268,7 @@ void update_mxcsr_from_sse_status(CPUX86State *env)
(flags & float_flag_overflow ? FPUS_OE : 0) |
(flags & float_flag_underflow ? FPUS_UE : 0) |
(flags & float_flag_inexact ? FPUS_PE : 0) |
- (flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE :
+ (flags & float_flag_output_denormal_flushed ? FPUS_UE | FPUS_PE :
0));
}
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
index e3f4a188501..339b73ad7dc 100644
--- a/target/m68k/fpu_helper.c
+++ b/target/m68k/fpu_helper.c
@@ -175,7 +175,7 @@ static int cpu_m68k_exceptbits_from_host(int host_bits)
if (host_bits & float_flag_overflow) {
target_bits |= 0x40;
}
- if (host_bits & (float_flag_underflow | float_flag_output_denormal)) {
+ if (host_bits & (float_flag_underflow | float_flag_output_denormal_flushed)) {
target_bits |= 0x20;
}
if (host_bits & float_flag_divbyzero) {
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index aeab6a1d8b3..ec38d9fde5e 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -6241,7 +6241,7 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
}
/* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
- if ((ieee_exception_flags & float_flag_output_denormal) &&
+ if ((ieee_exception_flags & float_flag_output_denormal_flushed) &&
(env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
mips_exception_flags |= FP_INEXACT;
if (action & CLEAR_FS_UNDERFLOW) {
diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
index 59dd1ae6128..b3ed822dd11 100644
--- a/target/rx/op_helper.c
+++ b/target/rx/op_helper.c
@@ -100,7 +100,7 @@ static void update_fpsw(CPURXState *env, float32 ret, uintptr_t retaddr)
SET_FPSW(X);
}
if ((xcpt & (float_flag_input_denormal_flushed
- | float_flag_output_denormal))
+ | float_flag_output_denormal_flushed))
&& !FIELD_EX32(env->fpsw, FPSW, DN)) {
env->fpsw = FIELD_DP32(env->fpsw, FPSW, CE, 1);
}
diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index 5d38aea143a..1b72dcc5f5c 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -43,7 +43,7 @@ static inline uint8_t f_get_excp_flags(CPUTriCoreState *env)
& (float_flag_invalid
| float_flag_overflow
| float_flag_underflow
- | float_flag_output_denormal
+ | float_flag_output_denormal_flushed
| float_flag_divbyzero
| float_flag_inexact);
}
@@ -99,7 +99,7 @@ static void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags)
some_excp = 1;
}
- if (flags & float_flag_underflow || flags & float_flag_output_denormal) {
+ if (flags & float_flag_underflow || flags & float_flag_output_denormal_flushed) {
env->FPU_FU = 1 << 31;
some_excp = 1;
}
@@ -109,7 +109,7 @@ static void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags)
some_excp = 1;
}
- if (flags & float_flag_inexact || flags & float_flag_output_denormal) {
+ if (flags & float_flag_inexact || flags & float_flag_output_denormal_flushed) {
env->PSW |= 1 << 26;
some_excp = 1;
}
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index b3d693eed0e..fee05d0a863 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -334,7 +334,7 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s,
}
frac_shr(p, frac_shift);
} else if (s->flush_to_zero) {
- flags |= float_flag_output_denormal;
+ flags |= float_flag_output_denormal_flushed;
p->cls = float_class_zero;
exp = 0;
frac_clear(p);
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 33/36] fpu: Fix a comment in softfloat-types.h
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (31 preceding siblings ...)
2025-01-28 20:13 ` [PULL 32/36] fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed Peter Maydell
@ 2025-01-28 20:13 ` Peter Maydell
2025-01-28 20:13 ` [PULL 34/36] target/arm: Remove redundant advsimd float16 helpers Peter Maydell
` (3 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:13 UTC (permalink / raw)
To: qemu-devel
In softfloat-types.h a comment documents that if the float_status
field flush_to_zero is set then we flush denormalised results to 0
and set the inexact flag. This isn't correct: the status flag that
we set when flush_to_zero causes us to flush an output to zero is
float_flag_output_denormal_flushed.
Correct the comment.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-22-peter.maydell@linaro.org
---
include/fpu/softfloat-types.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index c35fdaa5ae1..616c290145f 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -302,7 +302,7 @@ typedef struct float_status {
Float3NaNPropRule float_3nan_prop_rule;
FloatInfZeroNaNRule float_infzeronan_rule;
bool tininess_before_rounding;
- /* should denormalised results go to zero and set the inexact flag? */
+ /* should denormalised results go to zero and set output_denormal_flushed? */
bool flush_to_zero;
/* should denormalised inputs go to zero and set input_denormal_flushed? */
bool flush_inputs_to_zero;
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 34/36] target/arm: Remove redundant advsimd float16 helpers
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (32 preceding siblings ...)
2025-01-28 20:13 ` [PULL 33/36] fpu: Fix a comment in softfloat-types.h Peter Maydell
@ 2025-01-28 20:13 ` Peter Maydell
2025-01-28 20:13 ` [PULL 35/36] target/arm: Use FPST_A64_F16 for halfprec-to-other conversions Peter Maydell
` (2 subsequent siblings)
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:13 UTC (permalink / raw)
To: qemu-devel
The advsimd_addh etc helpers defined in helper-a64.c are identical to
the vfp_addh etc helpers defined in helper-vfp.c: both take two
float16 inputs (in a uint32_t type) plus a float_status* and are
simple wrappers around the softfloat float16_* functions.
(The duplication seems to be a historical accident: we added the
advsimd helpers in 2018 as part of the A64 implementation, and at
that time there was no f16 emulation in A32. Then later we added the
A32 f16 handling by extending the existing VFP helper macros to
generate f16 versions as well as f32 and f64, and didn't realise we
could clean things up.)
Remove the now-unnecessary advsimd helpers and make the places that
generated calls to them use the vfp helpers instead. Many of the
helper functions were already unused.
(The remaining advsimd_ helpers are those which don't have vfp
versions.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-26-peter.maydell@linaro.org
---
target/arm/tcg/helper-a64.h | 8 --------
target/arm/tcg/helper-a64.c | 9 ---------
target/arm/tcg/translate-a64.c | 16 ++++++++--------
3 files changed, 8 insertions(+), 25 deletions(-)
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
index 0c120bf3883..bac12fbe55b 100644
--- a/target/arm/tcg/helper-a64.h
+++ b/target/arm/tcg/helper-a64.h
@@ -47,14 +47,6 @@ DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, fpst)
DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
-DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
-DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
-DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
-DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
-DEF_HELPER_3(advsimd_addh, f16, f16, f16, fpst)
-DEF_HELPER_3(advsimd_subh, f16, f16, f16, fpst)
-DEF_HELPER_3(advsimd_mulh, f16, f16, f16, fpst)
-DEF_HELPER_3(advsimd_divh, f16, f16, f16, fpst)
DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, fpst)
DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, fpst)
DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, fpst)
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index 3b226daee78..05036089dd7 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -439,15 +439,6 @@ uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, float_status *fpst) \
return float16_ ## name(a, b, fpst); \
}
-ADVSIMD_HALFOP(add)
-ADVSIMD_HALFOP(sub)
-ADVSIMD_HALFOP(mul)
-ADVSIMD_HALFOP(div)
-ADVSIMD_HALFOP(min)
-ADVSIMD_HALFOP(max)
-ADVSIMD_HALFOP(minnum)
-ADVSIMD_HALFOP(maxnum)
-
#define ADVSIMD_TWOHALFOP(name) \
uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, \
float_status *fpst) \
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 2b8b253479a..703f265f20e 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -5101,28 +5101,28 @@ static const FPScalar f_scalar_fmul = {
TRANS(FMUL_s, do_fp3_scalar, a, &f_scalar_fmul)
static const FPScalar f_scalar_fmax = {
- gen_helper_advsimd_maxh,
+ gen_helper_vfp_maxh,
gen_helper_vfp_maxs,
gen_helper_vfp_maxd,
};
TRANS(FMAX_s, do_fp3_scalar, a, &f_scalar_fmax)
static const FPScalar f_scalar_fmin = {
- gen_helper_advsimd_minh,
+ gen_helper_vfp_minh,
gen_helper_vfp_mins,
gen_helper_vfp_mind,
};
TRANS(FMIN_s, do_fp3_scalar, a, &f_scalar_fmin)
static const FPScalar f_scalar_fmaxnm = {
- gen_helper_advsimd_maxnumh,
+ gen_helper_vfp_maxnumh,
gen_helper_vfp_maxnums,
gen_helper_vfp_maxnumd,
};
TRANS(FMAXNM_s, do_fp3_scalar, a, &f_scalar_fmaxnm)
static const FPScalar f_scalar_fminnm = {
- gen_helper_advsimd_minnumh,
+ gen_helper_vfp_minnumh,
gen_helper_vfp_minnums,
gen_helper_vfp_minnumd,
};
@@ -6902,10 +6902,10 @@ static bool do_fp_reduction(DisasContext *s, arg_qrr_e *a,
return true;
}
-TRANS_FEAT(FMAXNMV_h, aa64_fp16, do_fp_reduction, a, gen_helper_advsimd_maxnumh)
-TRANS_FEAT(FMINNMV_h, aa64_fp16, do_fp_reduction, a, gen_helper_advsimd_minnumh)
-TRANS_FEAT(FMAXV_h, aa64_fp16, do_fp_reduction, a, gen_helper_advsimd_maxh)
-TRANS_FEAT(FMINV_h, aa64_fp16, do_fp_reduction, a, gen_helper_advsimd_minh)
+TRANS_FEAT(FMAXNMV_h, aa64_fp16, do_fp_reduction, a, gen_helper_vfp_maxnumh)
+TRANS_FEAT(FMINNMV_h, aa64_fp16, do_fp_reduction, a, gen_helper_vfp_minnumh)
+TRANS_FEAT(FMAXV_h, aa64_fp16, do_fp_reduction, a, gen_helper_vfp_maxh)
+TRANS_FEAT(FMINV_h, aa64_fp16, do_fp_reduction, a, gen_helper_vfp_minh)
TRANS(FMAXNMV_s, do_fp_reduction, a, gen_helper_vfp_maxnums)
TRANS(FMINNMV_s, do_fp_reduction, a, gen_helper_vfp_minnums)
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 35/36] target/arm: Use FPST_A64_F16 for halfprec-to-other conversions
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (33 preceding siblings ...)
2025-01-28 20:13 ` [PULL 34/36] target/arm: Remove redundant advsimd float16 helpers Peter Maydell
@ 2025-01-28 20:13 ` Peter Maydell
2025-01-28 20:13 ` [PULL 36/36] hw/usb/canokey: Fix buffer overflow for OUT packet Peter Maydell
2025-01-29 19:17 ` [PULL 00/36] target-arm queue Stefan Hajnoczi
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:13 UTC (permalink / raw)
To: qemu-devel
We should be using the F16-specific float_status for conversions from
half-precision, because halfprec inputs never set Input Denormal.
Without FEAT_AHP, using the wrong fpst here had no effect, because
the only difference between the A64_F16 and A64 fpst is its handling
of flush-to-zero on input and output, and the helper functions
vfp_fcvt_f16_to_* and vfp_fcvt_*_to_f16 all explicitly squash the
relevant flushing flags, and flush_inputs_to_zero was the only way
that IDC could be set.
With FEAT_AHP, the FPCR.AH=1 behaviour sets IDC for
input_denormal_used, which we will only ignore in
vfp_get_fpsr_from_host() for the A64_F16 fpst; so it matters that we
use that one for f16 inputs (and the normal one for single/double to
f16 conversions).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-27-peter.maydell@linaro.org
---
target/arm/tcg/translate-a64.c | 9 ++++++---
target/arm/tcg/translate-sve.c | 4 ++--
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 703f265f20e..0b76a2cdb78 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8568,7 +8568,7 @@ static bool trans_FCVT_s_sh(DisasContext *s, arg_rr *a)
if (fp_access_check(s)) {
TCGv_i32 tcg_rn = read_fp_hreg(s, a->rn);
TCGv_i32 tcg_rd = tcg_temp_new_i32();
- TCGv_ptr tcg_fpst = fpstatus_ptr(FPST_A64);
+ TCGv_ptr tcg_fpst = fpstatus_ptr(FPST_A64_F16);
TCGv_i32 tcg_ahp = get_ahp_flag();
gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
@@ -8582,7 +8582,7 @@ static bool trans_FCVT_s_dh(DisasContext *s, arg_rr *a)
if (fp_access_check(s)) {
TCGv_i32 tcg_rn = read_fp_hreg(s, a->rn);
TCGv_i64 tcg_rd = tcg_temp_new_i64();
- TCGv_ptr tcg_fpst = fpstatus_ptr(FPST_A64);
+ TCGv_ptr tcg_fpst = fpstatus_ptr(FPST_A64_F16);
TCGv_i32 tcg_ahp = get_ahp_flag();
gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
@@ -9511,13 +9511,14 @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
return true;
}
- fpst = fpstatus_ptr(FPST_A64);
if (a->esz == MO_64) {
/* 32 -> 64 bit fp conversion */
TCGv_i64 tcg_res[2];
TCGv_i32 tcg_op = tcg_temp_new_i32();
int srcelt = a->q ? 2 : 0;
+ fpst = fpstatus_ptr(FPST_A64);
+
for (pass = 0; pass < 2; pass++) {
tcg_res[pass] = tcg_temp_new_i64();
read_vec_element_i32(s, tcg_op, a->rn, srcelt + pass, MO_32);
@@ -9532,6 +9533,8 @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
TCGv_i32 tcg_res[4];
TCGv_i32 ahp = get_ahp_flag();
+ fpst = fpstatus_ptr(FPST_A64_F16);
+
for (pass = 0; pass < 4; pass++) {
tcg_res[pass] = tcg_temp_new_i32();
read_vec_element_i32(s, tcg_res[pass], a->rn, srcelt + pass, MO_16);
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index a7dbea5acd0..e1788330aa7 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -3887,7 +3887,7 @@ TRANS_FEAT(FCMLA_zzxz, aa64_sve, gen_gvec_fpst_zzzz, fcmla_idx_fns[a->esz],
TRANS_FEAT(FCVT_sh, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_fcvt_sh, a, 0, FPST_A64)
TRANS_FEAT(FCVT_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvt_hs, a, 0, FPST_A64)
+ gen_helper_sve_fcvt_hs, a, 0, FPST_A64_F16)
TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz,
gen_helper_sve_bfcvt, a, 0, FPST_A64)
@@ -3895,7 +3895,7 @@ TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz,
TRANS_FEAT(FCVT_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_fcvt_dh, a, 0, FPST_A64)
TRANS_FEAT(FCVT_hd, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvt_hd, a, 0, FPST_A64)
+ gen_helper_sve_fcvt_hd, a, 0, FPST_A64_F16)
TRANS_FEAT(FCVT_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_fcvt_ds, a, 0, FPST_A64)
TRANS_FEAT(FCVT_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 36/36] hw/usb/canokey: Fix buffer overflow for OUT packet
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (34 preceding siblings ...)
2025-01-28 20:13 ` [PULL 35/36] target/arm: Use FPST_A64_F16 for halfprec-to-other conversions Peter Maydell
@ 2025-01-28 20:13 ` Peter Maydell
2025-01-29 19:17 ` [PULL 00/36] target-arm queue Stefan Hajnoczi
36 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-01-28 20:13 UTC (permalink / raw)
To: qemu-devel
From: Hongren Zheng <i@zenithal.me>
When USBPacket in OUT direction has larger payload
than the ep_out_buffer (of size 512), a buffer overflow
would occur.
It could be fixed by limiting the size of usb_packet_copy
to be at most buffer size. Further optimization gets rid
of the ep_out_buffer and directly uses ep_out as the target
buffer.
This is reported by a security researcher who artificially
constructed an OUT packet of size 2047. The report has gone
through the QEMU security process, and as this device is for
testing purpose and no deployment of it in virtualization
environment is observed, it is triaged not to be a security bug.
Cc: qemu-stable@nongnu.org
Fixes: d7d34918551dc48 ("hw/usb: Add CanoKey Implementation")
Reported-by: Juan Jose Lopez Jaimez <thatjiaozi@gmail.com>
Signed-off-by: Hongren Zheng <i@zenithal.me>
Message-id: Z4TfMOrZz6IQYl_h@Sun
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/usb/canokey.h | 4 ----
hw/usb/canokey.c | 6 +++---
2 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/hw/usb/canokey.h b/hw/usb/canokey.h
index e528889d332..1b60d734850 100644
--- a/hw/usb/canokey.h
+++ b/hw/usb/canokey.h
@@ -24,8 +24,6 @@
#define CANOKEY_EP_NUM 3
/* BULK/INTR IN can be up to 1352 bytes, e.g. get key info */
#define CANOKEY_EP_IN_BUFFER_SIZE 2048
-/* BULK OUT can be up to 270 bytes, e.g. PIV import cert */
-#define CANOKEY_EP_OUT_BUFFER_SIZE 512
typedef enum {
CANOKEY_EP_IN_WAIT,
@@ -59,8 +57,6 @@ typedef struct CanoKeyState {
/* OUT pointer to canokey recv buffer */
uint8_t *ep_out[CANOKEY_EP_NUM];
uint32_t ep_out_size[CANOKEY_EP_NUM];
- /* For large BULK OUT, multiple write to ep_out is needed */
- uint8_t ep_out_buffer[CANOKEY_EP_NUM][CANOKEY_EP_OUT_BUFFER_SIZE];
/* Properties */
char *file; /* canokey-file */
diff --git a/hw/usb/canokey.c b/hw/usb/canokey.c
index fae212f0530..e2d66179e0b 100644
--- a/hw/usb/canokey.c
+++ b/hw/usb/canokey.c
@@ -197,8 +197,8 @@ static void canokey_handle_data(USBDevice *dev, USBPacket *p)
switch (p->pid) {
case USB_TOKEN_OUT:
trace_canokey_handle_data_out(ep_out, p->iov.size);
- usb_packet_copy(p, key->ep_out_buffer[ep_out], p->iov.size);
out_pos = 0;
+ /* segment packet into (possibly multiple) ep_out */
while (out_pos != p->iov.size) {
/*
* key->ep_out[ep_out] set by prepare_receive
@@ -207,8 +207,8 @@ static void canokey_handle_data(USBDevice *dev, USBPacket *p)
* to be the buffer length
*/
out_len = MIN(p->iov.size - out_pos, key->ep_out_size[ep_out]);
- memcpy(key->ep_out[ep_out],
- key->ep_out_buffer[ep_out] + out_pos, out_len);
+ /* usb_packet_copy would update the pos offset internally */
+ usb_packet_copy(p, key->ep_out[ep_out], out_len);
out_pos += out_len;
/* update ep_out_size to actual len */
key->ep_out_size[ep_out] = out_len;
--
2.34.1
^ permalink raw reply related [flat|nested] 55+ messages in thread
* Re: [PULL 00/36] target-arm queue
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
` (35 preceding siblings ...)
2025-01-28 20:13 ` [PULL 36/36] hw/usb/canokey: Fix buffer overflow for OUT packet Peter Maydell
@ 2025-01-29 19:17 ` Stefan Hajnoczi
36 siblings, 0 replies; 55+ messages in thread
From: Stefan Hajnoczi @ 2025-01-29 19:17 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 116 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PULL 00/36] target-arm queue
@ 2025-07-11 13:33 Peter Maydell
2025-07-13 7:06 ` Stefan Hajnoczi
0 siblings, 1 reply; 55+ messages in thread
From: Peter Maydell @ 2025-07-11 13:33 UTC (permalink / raw)
To: qemu-devel
Hi; this should be my last major pullreq before softfreeze: it has
the nested-virt support, a new Cortex-M4 based board model, and
the CXL-on-arm patchset.
thanks
-- PMM
The following changes since commit df6fe2abf2e990f767ce755d426bc439c7bba336:
Merge tag 'pull-target-arm-20250704' of https://gitlab.com/pm215/qemu into staging (2025-07-07 09:22:41 -0400)
are available in the Git repository at:
https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20250711
for you to fetch changes up to 3a323a813fd42fc7c37ef09bc7a714d8e31691ce:
tests/functional: Add a test for the MAX78000 arm machine (2025-07-11 13:30:32 +0100)
----------------------------------------------------------------
target-arm queue:
* New board type max78000fthr
* Enable use of CXL on Arm 'virt' board
* Some more tidyup of ID register handling
* Refactor AT insns and PMU regs into separate source files
* Don't enforce NSE,NS check for EL3->EL3 returns
* hw/arm/fsl-imx8mp: Wire VIRQ and VFIQ
* Allow nested-virtualization with KVM on the 'virt' board
* system/qdev: Remove pointless NULL check in qdev_device_add_from_qdict
* hw/arm/virt-acpi-build: Don't create ITS id mappings by default
* target/arm: Remove unused helper_sme2_luti4_4b
----------------------------------------------------------------
Bernhard Beschow (1):
hw/arm/fsl-imx8mp: Wire VIRQ and VFIQ
Cornelia Huck (5):
arm/cpu: store id_afr0 into the idregs array
arm/cpu: store id_aa64afr{0,1} into the idregs array
arm/cpu: fix trailing ',' for SET_IDREG
arm/cpu: store clidr into the idregs array
arm/kvm: shorten one overly long line
Eric Auger (1):
hw/arm/arm_gicv3_kvm: Add a migration blocker with kvm nested virt
Haibo Xu (3):
hw/arm: Allow setting KVM vGIC maintenance IRQ
target/arm/kvm: Add helper to detect EL2 when using KVM
target/arm: Enable feature ARM_FEATURE_EL2 if EL2 is supported
Jackson Donaldson (13):
MAX78000: Add MAX78000FTHR Machine
MAX78000: ICC Implementation
MAX78000: Add ICC to SOC
MAX78000: UART Implementation
MAX78000: Add UART to SOC
MAX78000: GCR Implementation
MAX78000: Add GCR to SOC
MAX78000: TRNG Implementation
MAX78000: Add TRNG to SOC
MAX78000: AES implementation
MAX78000: Add AES to SOC
docs/system: arm: Add max78000 board description
tests/functional: Add a test for the MAX78000 arm machine
Jonathan Cameron (5):
hw/cxl-host: Add an index field to CXLFixedMemoryWindow
hw/cxl: Make the CXL fixed memory windows devices.
hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl
docs/cxl: Add an arm/virt example.
qtest/cxl: Add aarch64 virt test for CXL
Peter Maydell (2):
target/arm: Don't enforce NSE,NS check for EL3->EL3 returns
hw/arm/virt: Allow virt extensions with KVM
Philippe Mathieu-Daudé (1):
system/qdev: Remove pointless NULL check in qdev_device_add_from_qdict
Richard Henderson (4):
target/arm: Drop stub for define_tlb_insn_regs
target/arm: Split out AT insns to tcg/cpregs-at.c
target/arm: Split out performance monitor regs to cpregs-pmu.c
target/arm: Remove helper_sme2_luti4_4b
Shameer Kolothum (1):
hw/arm/virt-acpi-build: Don't create ITS id mappings by default
docs/system/arm/max78000.rst | 37 +
docs/system/arm/virt.rst | 9 +
docs/system/devices/cxl.rst | 11 +
docs/system/target-arm.rst | 1 +
include/hw/arm/max78000_soc.h | 50 +
include/hw/arm/virt.h | 4 +
include/hw/char/max78000_uart.h | 78 ++
include/hw/cxl/cxl.h | 5 +-
include/hw/cxl/cxl_host.h | 5 +-
include/hw/intc/arm_gicv3_common.h | 1 +
include/hw/misc/max78000_aes.h | 68 ++
include/hw/misc/max78000_gcr.h | 131 +++
include/hw/misc/max78000_icc.h | 33 +
include/hw/misc/max78000_trng.h | 35 +
target/arm/cpregs.h | 3 +
target/arm/cpu.h | 6 +-
target/arm/internals.h | 5 +
target/arm/kvm_arm.h | 7 +
target/arm/tcg/helper.h | 1 -
target/arm/cpu-sysregs.h.inc | 4 +
hw/acpi/cxl.c | 76 +-
hw/arm/fsl-imx8mp.c | 4 +
hw/arm/max78000_soc.c | 232 ++++
hw/arm/max78000fthr.c | 50 +
hw/arm/virt-acpi-build.c | 40 +-
hw/arm/virt.c | 52 +-
hw/char/max78000_uart.c | 285 +++++
hw/cxl/cxl-host-stubs.c | 7 +-
hw/cxl/cxl-host.c | 174 ++-
hw/i386/pc.c | 50 +-
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_kvm.c | 29 +
hw/intc/armv7m_nvic.c | 4 +-
hw/misc/max78000_aes.c | 223 ++++
hw/misc/max78000_gcr.c | 351 ++++++
hw/misc/max78000_icc.c | 120 ++
hw/misc/max78000_trng.c | 139 +++
system/qdev-monitor.c | 9 +-
target/arm/cpregs-pmu.c | 1309 +++++++++++++++++++++
target/arm/cpu64.c | 8 +-
target/arm/helper.c | 1813 +----------------------------
target/arm/kvm-stub.c | 5 +
target/arm/kvm.c | 24 +-
target/arm/tcg-stubs.c | 5 -
target/arm/tcg/cpregs-at.c | 519 +++++++++
target/arm/tcg/cpu-v7m.c | 16 +-
target/arm/tcg/cpu32.c | 34 +-
target/arm/tcg/cpu64.c | 68 +-
target/arm/tcg/helper-a64.c | 20 +-
target/arm/tcg/vec_helper.c | 1 -
tests/qtest/cxl-test.c | 58 +-
hw/arm/Kconfig | 15 +
hw/arm/meson.build | 2 +
hw/char/Kconfig | 3 +
hw/char/meson.build | 1 +
hw/misc/Kconfig | 12 +
hw/misc/meson.build | 4 +
target/arm/meson.build | 2 +
target/arm/tcg/meson.build | 1 +
tests/functional/meson.build | 1 +
tests/functional/test_arm_max78000fthr.py | 48 +
tests/qtest/meson.build | 1 +
62 files changed, 4300 insertions(+), 2010 deletions(-)
create mode 100644 docs/system/arm/max78000.rst
create mode 100644 include/hw/arm/max78000_soc.h
create mode 100644 include/hw/char/max78000_uart.h
create mode 100644 include/hw/misc/max78000_aes.h
create mode 100644 include/hw/misc/max78000_gcr.h
create mode 100644 include/hw/misc/max78000_icc.h
create mode 100644 include/hw/misc/max78000_trng.h
create mode 100644 hw/arm/max78000_soc.c
create mode 100644 hw/arm/max78000fthr.c
create mode 100644 hw/char/max78000_uart.c
create mode 100644 hw/misc/max78000_aes.c
create mode 100644 hw/misc/max78000_gcr.c
create mode 100644 hw/misc/max78000_icc.c
create mode 100644 hw/misc/max78000_trng.c
create mode 100644 target/arm/cpregs-pmu.c
create mode 100644 target/arm/tcg/cpregs-at.c
create mode 100755 tests/functional/test_arm_max78000fthr.py
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/36] target-arm queue
2025-07-11 13:33 Peter Maydell
@ 2025-07-13 7:06 ` Stefan Hajnoczi
0 siblings, 0 replies; 55+ messages in thread
From: Stefan Hajnoczi @ 2025-07-13 7:06 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 116 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PULL 00/36] target-arm queue
@ 2025-09-16 18:05 Peter Maydell
2025-09-17 1:43 ` Richard Henderson
2025-09-17 20:09 ` Richard Henderson
0 siblings, 2 replies; 55+ messages in thread
From: Peter Maydell @ 2025-09-16 18:05 UTC (permalink / raw)
To: qemu-devel
Hi; here's an arm pullreq; various miscellaneous new features
and bug fixes.
thanks
-- PMM
The following changes since commit 6a9fa5ef3230a7d51e0d953a59ee9ef10af705b8:
Merge tag 'pull-tcg-20250905' of https://gitlab.com/rth7680/qemu into staging (2025-09-05 09:51:27 +0200)
are available in the Git repository at:
https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20250916
for you to fetch changes up to aaf042299acf83919862c7d7dd5fc36acf4e0671:
hw/usb/network: Remove hardcoded 0x40 prefix in STRING_ETHADDR response (2025-09-16 17:32:06 +0100)
----------------------------------------------------------------
target-arm queue:
* tests, scripts: Don't import print_function from __future__
* Implement FEAT_ATS1A
* Remove deprecated pxa CPU family
* arm/kvm: report registers we failed to set
* Expose SME registers to GDB via gdbstub
* linux-user/aarch64: Generate ESR signal records
* hw/arm/raspi4b: remove redundant check in raspi_add_memory_node
* hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation
* system: drop the -old-param option
----------------------------------------------------------------
Cornelia Huck (1):
arm/kvm: report registers we failed to set
Nicolin Chen (1):
hw/arm/virt: Add an SMMU_IO_LEN macro
Osama Abdelkader (1):
hw/arm/raspi4b: remove redundant check in raspi_add_memory_node
Peter Maydell (7):
tests, scripts: Don't import print_function from __future__
target/arm: Remove deprecated pxa CPU family
target/arm: Remove XScale and iWMMXt translate.c code
target/arm: Remove iwmmxt helper functions
target/arm: Drop ARM_FEATURE_XSCALE handling
target/arm: Drop ARM_FEATURE_IWMMXT handling
system: drop the -old-param option
Richard Henderson (12):
linux-user/aarch64: Split out signal_for_exception
linux-user/aarch64: Check syndrome for EXCP_UDEF
linux-user/aarch64: Generate ESR signal records
target/arm: Add prot_check parameter to pmsav8_mpu_lookup
target/arm: Add in_prot_check to S1Translate
target/arm: Skip permission check from arm_cpu_get_phys_page_attrs_debug
target/arm: Introduce get_phys_addr_for_at
target/arm: Skip AF and DB updates for AccessType_AT
target/arm: Add prot_check parameter to do_ats_write
target/arm: Fill in HFG[RWI]TR_EL2 bits for Arm v9.5
target/arm: Remove outdated comment for ZCR_EL12
target/arm: Implement FEAT_ATS1A
Shameer Kolothum (10):
hw/arm/smmu-common: Check SMMU has PCIe Root Complex association
hw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT build
hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices
hw/arm/virt: Factor out common SMMUV3 dt bindings code
hw/pci: Introduce pci_setup_iommu_per_bus() for per-bus IOMMU ops retrieval
hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation
qemu-options.hx: Document the arm-smmuv3 device
bios-tables-test: Allow for smmuv3 test data.
qtest/bios-tables-test: Add tests for legacy smmuv3 and smmuv3 device
qtest/bios-tables-test: Update tables for smmuv3 tests
Stéphane Graber (1):
hw/usb/network: Remove hardcoded 0x40 prefix in STRING_ETHADDR response
Vacha Bhavsar (3):
target/arm: Increase MAX_PACKET_LENGTH for SME ZA remote gdb debugging
target/arm: Added support for SME register exposure to GDB
target/arm: Added test case for SME register exposure to GDB
docs/about/deprecated.rst | 34 -
docs/about/removed-features.rst | 26 +
docs/system/arm/emulation.rst | 1 +
configure | 6 +
bsd-user/arm/target_arch_elf.h | 1 -
gdbstub/internals.h | 22 +-
include/hw/arm/smmu-common.h | 1 +
include/hw/arm/virt.h | 1 +
include/hw/pci/pci.h | 2 +
include/hw/pci/pci_bridge.h | 1 +
include/hw/pci/pci_bus.h | 1 +
include/system/system.h | 1 -
target/arm/cpregs.h | 29 +-
target/arm/cpu-features.h | 5 +
target/arm/cpu.h | 30 +-
target/arm/internals.h | 26 +-
target/arm/tcg/helper.h | 95 --
target/arm/tcg/translate.h | 2 -
hw/arm/boot.c | 81 +-
hw/arm/raspi4b.c | 22 +-
hw/arm/smmu-common.c | 37 +-
hw/arm/smmuv3.c | 2 +
hw/arm/virt-acpi-build.c | 201 ++-
hw/arm/virt.c | 111 +-
hw/core/sysbus-fdt.c | 3 +
hw/pci-bridge/pci_expander_bridge.c | 1 -
hw/pci/pci.c | 31 +
hw/usb/dev-network.c | 2 +-
linux-user/aarch64/cpu_loop.c | 162 ++-
linux-user/aarch64/signal.c | 34 +-
linux-user/arm/elfload.c | 1 -
linux-user/arm/signal.c | 67 -
system/globals.c | 1 -
system/vl.c | 4 -
target/arm/cpu.c | 21 -
target/arm/gdbstub.c | 10 +-
target/arm/gdbstub64.c | 119 ++
target/arm/helper.c | 59 -
target/arm/kvm.c | 86 ++
target/arm/machine.c | 21 -
target/arm/ptw.c | 71 +-
target/arm/tcg/cpregs-at.c | 69 +-
target/arm/tcg/cpu32.c | 163 ---
target/arm/tcg/cpu64.c | 1 +
target/arm/tcg/hflags.c | 13 +-
target/arm/tcg/iwmmxt_helper.c | 672 ----------
target/arm/tcg/m_helper.c | 4 +-
target/arm/tcg/op_helper.c | 6 -
target/arm/tcg/translate.c | 1324 +-------------------
tests/qtest/bios-tables-test.c | 86 ++
qemu-options.hx | 14 +-
scripts/userfaultfd-wrlat.py | 1 -
target/arm/tcg/meson.build | 2 -
tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev | Bin 0 -> 10230 bytes
tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy | Bin 0 -> 10230 bytes
tests/data/acpi/aarch64/virt/IORT.smmuv3-dev | Bin 0 -> 364 bytes
tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy | Bin 0 -> 276 bytes
tests/guest-debug/test_gdbstub.py | 1 -
tests/tcg/aarch64/Makefile.target | 29 +
tests/tcg/aarch64/gdbstub/test-mte.py | 1 -
tests/tcg/aarch64/gdbstub/test-sme.py | 117 ++
tests/tcg/aarch64/gdbstub/test-sve-ioctl.py | 1 -
tests/tcg/aarch64/gdbstub/test-sve.py | 1 -
tests/tcg/multiarch/gdbstub/interrupt.py | 1 -
tests/tcg/multiarch/gdbstub/memory.py | 1 -
tests/tcg/multiarch/gdbstub/sha1.py | 1 -
tests/tcg/multiarch/gdbstub/test-proc-mappings.py | 1 -
.../tcg/multiarch/gdbstub/test-qxfer-auxv-read.py | 1 -
.../multiarch/gdbstub/test-qxfer-siginfo-read.py | 1 -
.../multiarch/gdbstub/test-thread-breakpoint.py | 1 -
tests/tcg/s390x/gdbstub/test-signals-s390x.py | 1 -
tests/tcg/s390x/gdbstub/test-svc.py | 1 -
72 files changed, 1151 insertions(+), 2794 deletions(-)
delete mode 100644 target/arm/tcg/iwmmxt_helper.c
create mode 100644 tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev
create mode 100644 tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy
create mode 100644 tests/data/acpi/aarch64/virt/IORT.smmuv3-dev
create mode 100644 tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy
create mode 100644 tests/tcg/aarch64/gdbstub/test-sme.py
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/36] target-arm queue
2025-09-16 18:05 Peter Maydell
@ 2025-09-17 1:43 ` Richard Henderson
2025-09-17 17:51 ` Richard Henderson
2025-09-17 20:09 ` Richard Henderson
1 sibling, 1 reply; 55+ messages in thread
From: Richard Henderson @ 2025-09-17 1:43 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
On 9/16/25 11:05, Peter Maydell wrote:
> Hi; here's an arm pullreq; various miscellaneous new features
> and bug fixes.
>
> thanks
> -- PMM
>
> The following changes since commit 6a9fa5ef3230a7d51e0d953a59ee9ef10af705b8:
>
> Merge tag 'pull-tcg-20250905' of https://gitlab.com/rth7680/qemu into staging (2025-09-05 09:51:27 +0200)
>
> are available in the Git repository at:
>
> https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20250916
>
> for you to fetch changes up to aaf042299acf83919862c7d7dd5fc36acf4e0671:
>
> hw/usb/network: Remove hardcoded 0x40 prefix in STRING_ETHADDR response (2025-09-16 17:32:06 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * tests, scripts: Don't import print_function from __future__
> * Implement FEAT_ATS1A
> * Remove deprecated pxa CPU family
> * arm/kvm: report registers we failed to set
> * Expose SME registers to GDB via gdbstub
> * linux-user/aarch64: Generate ESR signal records
> * hw/arm/raspi4b: remove redundant check in raspi_add_memory_node
> * hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation
> * system: drop the -old-param option
I don't understand why, but this causes failure on s390x host for hppa guest:
https://gitlab.com/qemu-project/qemu/-/jobs/11379271029
...
# Testing device 'elroy-pcihost'
Broken pipe
../alt/tests/qtest/libqtest.c:208: kill_qemu() detected QEMU death from signal 11
(Segmentation fault) (core dumped)
Aborted (core dumped)
Even more bizzarely, the failure bisects to
Author: Nicolin Chen <nicolinc@nvidia.com>
Date: Fri Aug 29 09:25:27 2025 +0100
hw/arm/virt: Add an SMMU_IO_LEN macro
This is useful as the subsequent support for new SMMUv3 dev will also
use the same.
which makes no sense at all. But it's repeatable, so...
r~
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/36] target-arm queue
2025-09-17 1:43 ` Richard Henderson
@ 2025-09-17 17:51 ` Richard Henderson
2025-09-18 9:41 ` Peter Maydell
0 siblings, 1 reply; 55+ messages in thread
From: Richard Henderson @ 2025-09-17 17:51 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
On 9/16/25 18:43, Richard Henderson wrote:
> On 9/16/25 11:05, Peter Maydell wrote:
>> Hi; here's an arm pullreq; various miscellaneous new features
>> and bug fixes.
>>
>> thanks
>> -- PMM
>>
>> The following changes since commit 6a9fa5ef3230a7d51e0d953a59ee9ef10af705b8:
>>
>> Merge tag 'pull-tcg-20250905' of https://gitlab.com/rth7680/qemu into staging
>> (2025-09-05 09:51:27 +0200)
>>
>> are available in the Git repository at:
>>
>> https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20250916
>>
>> for you to fetch changes up to aaf042299acf83919862c7d7dd5fc36acf4e0671:
>>
>> hw/usb/network: Remove hardcoded 0x40 prefix in STRING_ETHADDR response (2025-09-16
>> 17:32:06 +0100)
>>
>> ----------------------------------------------------------------
>> target-arm queue:
>> * tests, scripts: Don't import print_function from __future__
>> * Implement FEAT_ATS1A
>> * Remove deprecated pxa CPU family
>> * arm/kvm: report registers we failed to set
>> * Expose SME registers to GDB via gdbstub
>> * linux-user/aarch64: Generate ESR signal records
>> * hw/arm/raspi4b: remove redundant check in raspi_add_memory_node
>> * hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation
>> * system: drop the -old-param option
>
> I don't understand why, but this causes failure on s390x host for hppa guest:
>
> https://gitlab.com/qemu-project/qemu/-/jobs/11379271029
>
> ...
> # Testing device 'elroy-pcihost'
> Broken pipe
> ../alt/tests/qtest/libqtest.c:208: kill_qemu() detected QEMU death from signal 11
> (Segmentation fault) (core dumped)
> Aborted (core dumped)
>
> Even more bizzarely, the failure bisects to
>
> Author: Nicolin Chen <nicolinc@nvidia.com>
> Date: Fri Aug 29 09:25:27 2025 +0100
>
> hw/arm/virt: Add an SMMU_IO_LEN macro
>
> This is useful as the subsequent support for new SMMUv3 dev will also
> use the same.
>
> which makes no sense at all. But it's repeatable, so...
Ho hum. It appears to be flaky. I now see it without this patch set at all:
https://gitlab.com/qemu-project/qemu/-/jobs/11391070227
r~
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/36] target-arm queue
2025-09-16 18:05 Peter Maydell
2025-09-17 1:43 ` Richard Henderson
@ 2025-09-17 20:09 ` Richard Henderson
1 sibling, 0 replies; 55+ messages in thread
From: Richard Henderson @ 2025-09-17 20:09 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
On 9/16/25 11:05, Peter Maydell wrote:
> Hi; here's an arm pullreq; various miscellaneous new features
> and bug fixes.
>
> thanks
> -- PMM
>
> The following changes since commit 6a9fa5ef3230a7d51e0d953a59ee9ef10af705b8:
>
> Merge tag 'pull-tcg-20250905' ofhttps://gitlab.com/rth7680/qemu into staging (2025-09-05 09:51:27 +0200)
>
> are available in the Git repository at:
>
> https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20250916
>
> for you to fetch changes up to aaf042299acf83919862c7d7dd5fc36acf4e0671:
>
> hw/usb/network: Remove hardcoded 0x40 prefix in STRING_ETHADDR response (2025-09-16 17:32:06 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * tests, scripts: Don't import print_function from __future__
> * Implement FEAT_ATS1A
> * Remove deprecated pxa CPU family
> * arm/kvm: report registers we failed to set
> * Expose SME registers to GDB via gdbstub
> * linux-user/aarch64: Generate ESR signal records
> * hw/arm/raspi4b: remove redundant check in raspi_add_memory_node
> * hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation
> * system: drop the -old-param option
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/10.2 as appropriate.
r~
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/36] target-arm queue
2025-09-17 17:51 ` Richard Henderson
@ 2025-09-18 9:41 ` Peter Maydell
2025-09-18 10:18 ` Peter Maydell
0 siblings, 1 reply; 55+ messages in thread
From: Peter Maydell @ 2025-09-18 9:41 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Wed, 17 Sept 2025 at 18:51, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 9/16/25 18:43, Richard Henderson wrote:
> > I don't understand why, but this causes failure on s390x host for hppa guest:
> >
> > https://gitlab.com/qemu-project/qemu/-/jobs/11379271029
> >
> > ...
> > # Testing device 'elroy-pcihost'
> > Broken pipe
> > ../alt/tests/qtest/libqtest.c:208: kill_qemu() detected QEMU death from signal 11
> > (Segmentation fault) (core dumped)
> > Aborted (core dumped)
> >
> > Even more bizzarely, the failure bisects to
> >
> > Author: Nicolin Chen <nicolinc@nvidia.com>
> > Date: Fri Aug 29 09:25:27 2025 +0100
> >
> > hw/arm/virt: Add an SMMU_IO_LEN macro
> >
> > This is useful as the subsequent support for new SMMUv3 dev will also
> > use the same.
> >
> > which makes no sense at all. But it's repeatable, so...
>
> Ho hum. It appears to be flaky. I now see it without this patch set at all:
>
> https://gitlab.com/qemu-project/qemu/-/jobs/11391070227
asan reports a heap-use-after-free in the dino PCI controller
when running the device-introspect-test, which may be relevant.
The subtest the segfault happens on is half a dozen or so
devices after the dino-pci one, so it's plausible that heap
corruption leads to the subsequent crash.
I'll investigate the use-after-free...
==1771223==ERROR: AddressSanitizer: heap-use-after-free on address
0x527000018f80 at pc 0x5b4b9d3369b5 bp 0x7ffd01929980 sp
0x7ffd01929978
WRITE of size 8 at 0x527000018f80 thread T0
#0 0x5b4b9d3369b4 in pci_host_bus_register
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../hw/pci/pci.c:608:5
#1 0x5b4b9d321566 in pci_root_bus_internal_init
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../hw/pci/pci.c:677:5
#2 0x5b4b9d3215e0 in pci_root_bus_new
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../hw/pci/pci.c:706:5
#3 0x5b4b9d321fe5 in pci_register_root_bus
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../hw/pci/pci.c:751:11
#4 0x5b4b9d390521 in dino_pcihost_init
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../hw/pci-host/dino.c:473:16
-- PMM
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/36] target-arm queue
2025-09-18 9:41 ` Peter Maydell
@ 2025-09-18 10:18 ` Peter Maydell
0 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-09-18 10:18 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Thu, 18 Sept 2025 at 10:41, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Wed, 17 Sept 2025 at 18:51, Richard Henderson
> <richard.henderson@linaro.org> wrote:
> >
> > On 9/16/25 18:43, Richard Henderson wrote:
> > > I don't understand why, but this causes failure on s390x host for hppa guest:
> > >
> > > https://gitlab.com/qemu-project/qemu/-/jobs/11379271029
> > >
> > > ...
> > > # Testing device 'elroy-pcihost'
> > > Broken pipe
> > > ../alt/tests/qtest/libqtest.c:208: kill_qemu() detected QEMU death from signal 11
> > > (Segmentation fault) (core dumped)
> > > Aborted (core dumped)
> > >
> > > Even more bizzarely, the failure bisects to
> > >
> > > Author: Nicolin Chen <nicolinc@nvidia.com>
> > > Date: Fri Aug 29 09:25:27 2025 +0100
> > >
> > > hw/arm/virt: Add an SMMU_IO_LEN macro
> > >
> > > This is useful as the subsequent support for new SMMUv3 dev will also
> > > use the same.
> > >
> > > which makes no sense at all. But it's repeatable, so...
> >
> > Ho hum. It appears to be flaky. I now see it without this patch set at all:
> >
> > https://gitlab.com/qemu-project/qemu/-/jobs/11391070227
>
> asan reports a heap-use-after-free in the dino PCI controller
> when running the device-introspect-test, which may be relevant.
> The subtest the segfault happens on is half a dozen or so
> devices after the dino-pci one, so it's plausible that heap
> corruption leads to the subsequent crash.
...and fixing that one shows that the elroy-pcihost device
has the identical bug, so even more likely to be the culprit.
-- PMM
^ permalink raw reply [flat|nested] 55+ messages in thread
end of thread, other threads:[~2025-09-18 10:19 UTC | newest]
Thread overview: 55+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-01-28 20:12 [PULL 00/36] target-arm queue Peter Maydell
2025-01-28 20:12 ` [PULL 01/36] hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m' Peter Maydell
2025-01-28 20:12 ` [PULL 02/36] hw/arm/stellaris: Add 'armv7m' local variable Peter Maydell
2025-01-28 20:12 ` [PULL 03/36] hw/arm/v7m: Remove use of &first_cpu in machine_init() Peter Maydell
2025-01-28 20:12 ` [PULL 04/36] hw/char/imx_serial: Fix reset value of UFCR register Peter Maydell
2025-01-28 20:12 ` [PULL 05/36] hw/char/imx_serial: Update all state before restarting ageing timer Peter Maydell
2025-01-28 20:12 ` [PULL 06/36] hw/pci-host/designware: Expose MSI IRQ Peter Maydell
2025-01-28 20:12 ` [PULL 07/36] hw/arm/stellaris: Link each board schematic Peter Maydell
2025-01-28 20:12 ` [PULL 08/36] hw/arm/stellaris: Constify read-only arrays Peter Maydell
2025-01-28 20:12 ` [PULL 09/36] hw/arm/stellaris: Remove incorrect unimplemented i2c-0 at 0x40002000 Peter Maydell
2025-01-28 20:12 ` [PULL 10/36] hw/arm/stellaris: Replace magic numbers by definitions Peter Maydell
2025-01-28 20:12 ` [PULL 11/36] hw/arm/stellaris: Use DEVCAP macro to access DeviceCapability registers Peter Maydell
2025-01-28 20:12 ` [PULL 12/36] hw/arm/stellaris: Map both I2C controllers Peter Maydell
2025-01-28 20:12 ` [PULL 13/36] tests/functional: Add a test for the arm microbit machine Peter Maydell
2025-01-28 20:12 ` [PULL 14/36] target/arm: arm_reset_sve_state() should set FPSR, not FPCR Peter Maydell
2025-01-28 20:12 ` [PULL 15/36] target/arm: Use FPSR_ constants in vfp_exceptbits_from_host() Peter Maydell
2025-01-28 20:12 ` [PULL 16/36] target/arm: Use uint32_t " Peter Maydell
2025-01-28 20:12 ` [PULL 17/36] target/arm: Define new fp_status_a32 and fp_status_a64 Peter Maydell
2025-01-28 20:12 ` [PULL 18/36] target/arm: Use vfp.fp_status_a64 in A64-only helper functions Peter Maydell
2025-01-28 20:12 ` [PULL 19/36] target/arm: Use fp_status_a64 or fp_status_a32 in is_ebf() Peter Maydell
2025-01-28 20:12 ` [PULL 20/36] target/arm: Use fp_status_a32 in vjvct helper Peter Maydell
2025-01-28 20:12 ` [PULL 21/36] target/arm: Use fp_status_a32 in vfp_cmp helpers Peter Maydell
2025-01-28 20:13 ` [PULL 22/36] target/arm: Use FPST_A32 in A32 decoder Peter Maydell
2025-01-28 20:13 ` [PULL 23/36] target/arm: Use FPST_A64 in A64 decoder Peter Maydell
2025-01-28 20:13 ` [PULL 24/36] target/arm: Remove now-unused vfp.fp_status and FPST_FPCR Peter Maydell
2025-01-28 20:13 ` [PULL 25/36] target/arm: Define new fp_status_f16_a32 and fp_status_f16_a64 Peter Maydell
2025-01-28 20:13 ` [PULL 26/36] target/arm: Use fp_status_f16_a32 in AArch32-only helpers Peter Maydell
2025-01-28 20:13 ` [PULL 27/36] target/arm: Use fp_status_f16_a64 in AArch64-only helpers Peter Maydell
2025-01-28 20:13 ` [PULL 28/36] target/arm: Use FPST_A32_F16 in A32 decoder Peter Maydell
2025-01-28 20:13 ` [PULL 29/36] target/arm: Use FPST_A64_F16 in A64 decoder Peter Maydell
2025-01-28 20:13 ` [PULL 30/36] target/arm: Remove now-unused vfp.fp_status_f16 and FPST_FPCR_F16 Peter Maydell
2025-01-28 20:13 ` [PULL 31/36] fpu: Rename float_flag_input_denormal to float_flag_input_denormal_flushed Peter Maydell
2025-01-28 20:13 ` [PULL 32/36] fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed Peter Maydell
2025-01-28 20:13 ` [PULL 33/36] fpu: Fix a comment in softfloat-types.h Peter Maydell
2025-01-28 20:13 ` [PULL 34/36] target/arm: Remove redundant advsimd float16 helpers Peter Maydell
2025-01-28 20:13 ` [PULL 35/36] target/arm: Use FPST_A64_F16 for halfprec-to-other conversions Peter Maydell
2025-01-28 20:13 ` [PULL 36/36] hw/usb/canokey: Fix buffer overflow for OUT packet Peter Maydell
2025-01-29 19:17 ` [PULL 00/36] target-arm queue Stefan Hajnoczi
-- strict thread matches above, loose matches on Subject: below --
2025-09-16 18:05 Peter Maydell
2025-09-17 1:43 ` Richard Henderson
2025-09-17 17:51 ` Richard Henderson
2025-09-18 9:41 ` Peter Maydell
2025-09-18 10:18 ` Peter Maydell
2025-09-17 20:09 ` Richard Henderson
2025-07-11 13:33 Peter Maydell
2025-07-13 7:06 ` Stefan Hajnoczi
2024-02-02 15:36 Peter Maydell
2024-02-03 13:27 ` Peter Maydell
2024-01-26 14:33 Peter Maydell
2024-01-27 13:00 ` Peter Maydell
2020-12-10 11:47 Peter Maydell
2020-12-10 12:51 ` Peter Maydell
2020-09-14 14:06 Peter Maydell
2020-03-12 16:44 Peter Maydell
2020-03-12 20:32 ` Peter Maydell
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