[PATCH v2 0/5] riscv: dts: starfive: jh7110-common: Sync downstream U-Boot changes

From: E Shattow <e@freeshell.de>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, E Shattow <e@freeshell.de>
Subject: [PATCH v2 0/5] riscv: dts: starfive: jh7110-common: Sync downstream U-Boot changes
Date: Sun,  2 Feb 2025 17:37:06 -0800	[thread overview]
Message-ID: <20250203013730.269558-1-e@freeshell.de> (raw)

U-Boot boot loader has adopted using the Linux dt-rebasing tree for dts
with StarFive VisionFive2 board target (and related JH7110 common boards).
Sync the minimum changes from jh7110-common.dtsi needed for boot so these
can be dropped from U-Boot.

Changes since v1:
  Do not set unused eeprom label.
  Do not set no-op zero-value assigned-clock-rates, adjust commit message.

E Shattow (5):
  riscv: dts: starfive: jh7110-common: replace syscrg clock assignments
  riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2
    cycles max 100MHz
  riscv: dts: starfive: jh7110-common: assign 24MHz clock-frequency to
    uart0
  riscv: dts: starfive: jh7110-common: add eeprom node to i2c5
  riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by
    boot  loader

 .../boot/dts/starfive/jh7110-common.dtsi      | 28 +++++++++++++++----
 1 file changed, 23 insertions(+), 5 deletions(-)

base-commit: 708d55db3edbe2ccf88d94b5f2e2b404bc0ba37c
-- 
2.47.2

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